README.txt
1 //===- README.txt - Notes for improving CellSPU-specific code gen ---------===// 2 3 This code was contributed by a team from the Computer Systems Research 4 Department in The Aerospace Corporation: 5 6 - Scott Michel (head bottle washer and much of the non-floating point 7 instructions) 8 - Mark Thomas (floating point instructions) 9 - Michael AuYeung (intrinsics) 10 - Chandler Carruth (LLVM expertise) 11 - Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise) 12 13 Some minor fixes added by Kalle Raiskila. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 17 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR 18 OTHERWISE. IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES 19 OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING 20 OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT 21 LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR 22 REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL, 23 OR PUNITIVE DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR 24 SUCH DAMAGES ARE FORESEEABLE. 25 26 --------------------------------------------------------------------------- 27 --WARNING--: 28 --WARNING--: The CellSPU work is work-in-progress and "alpha" quality code. 29 --WARNING--: 30 31 If you are brave enough to try this code or help to hack on it, be sure 32 to add 'spu' to configure's --enable-targets option, e.g.: 33 34 ./configure <your_configure_flags_here> \ 35 --enable-targets=x86,x86_64,powerpc,spu 36 37 --------------------------------------------------------------------------- 38 39 TODO: 40 * In commit r142152 vector legalization was set to element promotion per 41 default. This breaks half vectors (e.g. v2i32) badly as they get element 42 promoted to much slower types (v2i64). 43 44 * Many CellSPU specific codegen tests only grep & count the number of 45 instructions, not checking their place with FileCheck. There have also 46 been some commits that change the CellSPU checks, some of which might 47 have not been thoroughly scrutinized w.r.t. to the changes they cause in SPU 48 assembly. (especially since about the time of r142152) 49 50 * Some of the i64 math have huge tablegen rules, which sometime cause 51 tablegen to run out of memory. See e.g. bug 8850. i64 arithmetics 52 should probably be done with libraries. 53 54 * Create a machine pass for performing dual-pipeline scheduling specifically 55 for CellSPU, and insert branch prediction instructions as needed. 56 57 * i32 instructions: 58 59 * i32 division (work-in-progress) 60 61 * i64 support (see i64operations.c test harness): 62 63 * shifts and comparison operators: done 64 * sign and zero extension: done 65 * addition: done 66 * subtraction: needed 67 * multiplication: done 68 69 * i128 support: 70 71 * zero extension, any extension: done 72 * sign extension: done 73 * arithmetic operators (add, sub, mul, div): needed 74 * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed 75 76 * or: done 77 78 * f64 support 79 80 * Comparison operators: 81 SETOEQ unimplemented 82 SETOGT unimplemented 83 SETOGE unimplemented 84 SETOLT unimplemented 85 SETOLE unimplemented 86 SETONE unimplemented 87 SETO done (lowered) 88 SETUO done (lowered) 89 SETUEQ unimplemented 90 SETUGT unimplemented 91 SETUGE unimplemented 92 SETULT unimplemented 93 SETULE unimplemented 94 SETUNE unimplemented 95 96 * LLVM vector suport 97 98 * VSETCC needs to be implemented. It's pretty straightforward to code, but 99 needs implementation. 100 101 * Intrinsics 102 103 * spu.h instrinsics added but not tested. Need to have an operational 104 llvm-spu-gcc in order to write a unit test harness. 105 106 ===-------------------------------------------------------------------------=== 107
