| /external/llvm/test/CodeGen/Mips/ |
| buildpairextractelementf64.ll | 7 ; CHECK: mtc1
8 ; CHECK: mtc1
|
| 2008-08-04-Bitconvert.ll | 5 ; CHECK: mtc1
|
| constantfp0.ll | 5 ; CHECK: mtc1 $zero, $f[[R0:[0-9]+]]
|
| fabs.ll | 13 ; 32: mtc1 $[[AND]], $f0
16 ; 32R2: mtc1 $[[INS]], $f0
32 ; 32: mtc1 $[[AND]], $f1
35 ; 32R2: mtc1 $[[INS]], $f1
|
| fcopysign.ll | 15 ; 32: mtc1 $[[OR]], $f1
19 ; 32R2: mtc1 $[[INS]], $f1
48 ; 32: mtc1 $[[OR]], $f0
52 ; 32R2: mtc1 $[[INS]], $f0
|
| fcopysign-f32-f64.ll | 17 ; 64: mtc1 $[[OR]], $f0
21 ; 64R2: mtc1 $[[INS]], $f0
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 107 Opc = Mips::MTC1;
345 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
349 // mtc1 Lo, $fp
350 // mtc1 Hi, $fp + 1
|
| MipsInstrFPU.td | 235 def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
236 "mtc1\t$rt, $fs",
422 // This pseudo instr gets expanded into 2 mtc1 instrs after register
440 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
441 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
443 def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
448 (CVT_D32_W (MTC1 CPURegs:$src))>;
460 (CVT_D64_W (MTC1 CPURegs:$src))>;
|
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 303 __ mtc1(t0, f14);
372 __ mtc1(t0, f6);
373 __ mtc1(t1, f7);
374 __ mtc1(t2, f4);
375 __ mtc1(t3, f5);
441 __ mtc1(t0, f12);
446 __ mtc1(t1, f14);
804 __ mtc1(t0, f8); // f8 has LS 32-bits.
805 __ mtc1(t1, f9); // f9 has MS 32-bits.
[all...] |
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssemblerMIPS.h | [all...] |
| /external/llvm/test/MC/Mips/ |
| mips-fpu-instructions.s | 148 # CHECK: mtc1 $6, $f7 # encoding: [0x00,0x38,0x86,0x44]
159 mtc1 $a2,$f7
|
| /bionic/libc/arch-mips/bionic/ |
| _setjmp.S | 55 mtc1 t1, FPR ; \
|
| setjmp.S | 56 mtc1 t1, FPR ; \
|
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 999 mtc1(at, fd);
1012 mtc1(at, FPURegister::from_code(scratch.code() + 1));
1013 mtc1(zero_reg, scratch);
1025 mtc1(t8, fd);
1032 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1042 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1053 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1064 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1079 mtc1(at, FPURegister::from_code(scratch.code() + 1));
1080 mtc1(zero_reg, scratch)
[all...] |
| codegen-mips.cc | 200 __ mtc1(t5, f0);
|
| disasm-mips.cc | 475 case MTC1:
476 Format(instr, "mtc1 'rt, 'fs");
|
| code-stubs-mips.cc | 525 __ mtc1(scratch1, f14);
528 __ mtc1(scratch1, f12);
615 __ mtc1(scratch1, dst);
692 __ mtc1(int_scratch, single_scratch);
[all...] |
| assembler-mips.cc | 1652 void Assembler::mtc1(Register rt, FPURegister fs) { function in class:v8::Assembler
[all...] |
| constants-mips.h | 363 MTC1 = ((0 << 3) + 4) << 21,
|
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Factory.cpp | 63 /* note the operands are swapped for the mtc1 instr */
875 /* note the operands are swapped for the mtc1 instr */
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 270 # CHECK: mtc1 $6, $f7
|
| mips32_le.txt | 270 # CHECK: mtc1 $6, $f7
|
| mips32r2.txt | 279 # CHECK: mtc1 $6, $f7
|
| mips32r2_le.txt | 279 # CHECK: mtc1 $6, $f7
|
| /dalvik/vm/compiler/codegen/mips/ |
| MipsLIR.h | 484 kMipsMtc1, /* mtc1 t,s [01000100100] t[20..16] s[15..11] [00000000000] */
|
