| /dalvik/vm/mterp/x86/ |
| footer.S | 272 SPILL(rIBASE)
502 movl %edx, TMP_SPILL1(%ebp) # spill self->interpStackEnd
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| README.txt | 642 This is functional, but there is no reason to spill the LR register all the way
657 reg, it would ask "what is the best class to copy this into that I *can* spill"
659 register of that class. If it is then later necessary to spill that reg, so be
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| /external/valgrind/main/coregrind/m_scheduler/ |
| scheduler.c | 629 guest state, its two copies, and the spill area. In short, all 4
645 "sh2 %p %d, spill %p %d\n",
671 the spill area. */
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 181 // Don't return a super-class that would shrink the spill size.
515 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
|
| README.txt | 631 Leaf functions that require one 4-byte spill slot have a prolog like this:
759 This seems like a cross between remat and spill folding.
1052 Since we 'know' that this is a 'neg', we can actually "fold" the spill into
1212 enough to warrant the spill.
[all...] |
| X86RegisterInfo.td | 386 // values, though they really are f80 values. This will cause us to spill
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| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| Factory.cpp | 583 * and base and dest are the same, spill some other register to
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| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Factory.cpp | 600 * and base and dest are the same, spill some other register to
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| /dalvik/vm/native/ |
| java_lang_reflect_Field.cpp | 572 const s4* valuePtr = (s4*) &args[7]; /* 64-bit vars spill into args[8] */
|
| /external/chromium/chrome/browser/autocomplete/ |
| autocomplete_popup_view_mac.mm | 70 // actual border so that it can spill a glow into the toolbar or
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| /external/jmonkeyengine/engine/src/core-plugins/com/jme3/texture/plugins/ |
| TGALoader.java | 476 // start at data[offsetBytes]... spill into next byte as needed.
|
| /external/libogg/src/ |
| framing.c | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveInterval.h | 433 /// span instructions. It doesn't pay to spill such an interval.
|
| Passes.h | 339 /// SpillPlacement analysis. Suggest optimal placement of spill code between
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 504 // We assume a single instruction only has a spill or reload, not
518 CommentOS << MMO->getSize() << "-byte Spill\n";
522 CommentOS << MMO->getSize() << "-byte Folded Spill\n";
525 // Check for spill-induced copies
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 188 // know how to spill them. If we make our prologue/epilogue code smarter at
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 12 // allocation, but because we have a spill in between the feeder and new value
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| /external/llvm/test/CodeGen/Mips/ |
| ra-allocatable.ll | 96 ; CHECK: sw $ra, {{[0-9]+}}($sp) # 4-byte Folded Spill
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| /external/llvm/test/CodeGen/X86/ |
| 2009-03-23-MultiUseSched.ll | 2 ; RUN: not grep spill %t
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| /external/v8/src/ |
| flag-definitions.h | 542 "report heap spill statistics along with heap_stats "
|
| objects-debug.cc | 842 PrintF("\n JSObject Spill Statistics (#%d):\n", number_of_objects_);
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| /external/valgrind/main/VEX/priv/ |
| host_arm_defs.h | 603 generate spill/reload of 128-bit registers since current register
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| host_ppc_defs.h | 81 extern HReg hregPPC_GPR30 ( Bool mode64 ); // used as VMX spill temp
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| /external/valgrind/main/coregrind/m_dispatch/ |
| dispatch-ppc32-linux.S | 182 stw 3,28(1) /* spill orig guest_state ptr */
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| dispatch-ppc64-linux.S | 189 std 3,104(1) /* spill orig guest_state ptr */
|
