| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 41 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
49 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
70 MachineBasicBlock::iterator MI,
76 MachineBasicBlock::iterator MI,
|
| XCoreRegisterInfo.cpp | 160 MachineInstr &MI = *II;
161 DebugLoc dl = MI.getDebugLoc();
164 while (!MI.getOperand(i).isFI()) {
166 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
169 MachineOperand &FrameOp = MI.getOperand(i);
172 MachineFunction &MF = *MI.getParent()->getParent();
181 DEBUG(MI.print(errs()));
192 if (MI.isDebugValue()) {
193 MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
194 MI.getOperand(i+1).ChangeToImmediate(Offset)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.cpp | 72 MachineInstr &MI = *II;
73 MachineFunction &MF = *MI.getParent()->getParent();
114 Offset += MI.getOperand(OpNo + 1).getImm();
118 // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
120 if (!MI.isDebugValue() && !isInt<16>(Offset)) {
121 MachineBasicBlock &MBB = *MI.getParent();
135 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false);
136 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
|
| Mips16FrameLowering.h | 31 MachineBasicBlock::iterator MI,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCFGOptimizer.cpp | 65 HexagonCFGOptimizer::InvertAndChangeJumpTarget(MachineInstr* MI,
69 switch(MI->getOpcode()) {
90 MI->setDesc(QII->get(NewOpcode));
91 MI->getOperand(1).setMBB(NewTarget);
105 MachineInstr *MI = MII;
106 int Opc = MI->getOpcode();
158 if ((MI->getOpcode() == Hexagon::JMP_c) ||
159 (MI->getOpcode() == Hexagon::JMP_cNot)) {
160 CondBranchTarget = MI->getOperand(1).getMBB();
183 InvertAndChangeJumpTarget(MI, UncondTarget)
[all...] |
| HexagonMCInstLower.cpp | 41 void llvm::HexagonLowerToMC(const MachineInstr* MI, MCInst& MCI,
43 MCI.setOpcode(MI->getOpcode());
45 for (unsigned i = 0, e = MI->getNumOperands(); i < e; i++) {
46 const MachineOperand &MO = MI->getOperand(i);
51 MI->dump();
|
| HexagonFrameLowering.h | 35 MachineBasicBlock::iterator MI,
40 MachineBasicBlock::iterator MI,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 140 MachineInstr *MI = SU->getInstr();
142 if (MI->isDebugValue())
145 unsigned Opcode = MI->getOpcode();
187 if (isLoad && NumStores && !MI->memoperands_empty()) {
188 MachineMemOperand *MO = *MI->memoperands_begin();
198 MachineInstr *MI = SU->getInstr();
200 if (MI->isDebugValue())
203 unsigned Opcode = MI->getOpcode();
214 if (isStore && NumStores < 4 && !MI->memoperands_empty()) {
215 MachineMemOperand *MO = *MI->memoperands_begin()
[all...] |
| PPCCTRLoops.cpp | 98 bool isInductionOperation(const MachineInstr *MI, unsigned IVReg) const;
102 bool isInvalidLoopOperation(const MachineInstr *MI) const;
113 bool isDead(const MachineInstr *MI,
117 void removeIfDead(MachineInstr *MI);
180 static bool isCompareEqualsImm(const MachineInstr *MI, bool &SignedCmp) {
181 if (MI->getOpcode() == PPC::CMPWI || MI->getOpcode() == PPC::CMPDI) {
184 } else if (MI->getOpcode() == PPC::CMPLWI || MI->getOpcode() == PPC::CMPLDI) {
345 MachineInstr *MI = IV_Opnd->getParent()
[all...] |
| PPCAsmPrinter.cpp | 75 virtual void EmitInstruction(const MachineInstr *MI);
77 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
79 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
82 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
86 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
88 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
90 if (MI->getOperand(0).isReg() && MI->getOperand(2).isImm())
91 Location.set(MI->getOperand(0).getReg(), MI->getOperand(2).getImm())
[all...] |
| PPCInstrInfo.cpp | 86 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
89 switch (MI.getOpcode()) {
93 SrcReg = MI.getOperand(1).getReg();
94 DstReg = MI.getOperand(0).getReg();
100 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
102 switch (MI->getOpcode()) {
108 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
109 MI->getOperand(2).isFI()) {
110 FrameIndex = MI->getOperand(2).getIndex()
[all...] |
| PPCInstrInfo.h | 95 bool isCoalescableExtInstr(const MachineInstr &MI,
98 unsigned isLoadFromStackSlot(const MachineInstr *MI,
100 unsigned isStoreToStackSlot(const MachineInstr *MI,
105 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
108 MachineBasicBlock::iterator MI) const;
150 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
|
| /external/llvm/lib/Analysis/IPA/ |
| FindUsedTypes.cpp | 70 for (Module::iterator MI = m.begin(), ME = m.end(); MI != ME; ++MI) {
71 IncorporateType(MI->getType());
72 const Function &F = *MI;
|
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.h | 154 void Observe(MachineInstr *MI, unsigned Count, unsigned InsertPosIndex);
164 /// that is both implicitly used and defined in MI
165 bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO);
167 /// GetPassthruRegs - If MI implicitly def/uses a register, then
169 void GetPassthruRegs(MachineInstr *MI, std::set<unsigned>& PassthruRegs);
174 void PrescanInstruction(MachineInstr *MI, unsigned Count,
176 void ScanInstruction(MachineInstr *MI, unsigned Count);
|
| RegisterScavenging.cpp | 129 MachineInstr *MI = MBBI;
131 if (MI == ScavengeRestore) {
137 if (MI->isDebugValue())
145 bool isPred = TII->isPredicated(MI);
148 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
149 const MachineOperand &MO = MI->getOperand(i);
175 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
176 const MachineOperand &MO = MI->getOperand(i);
212 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
269 assert(StartMI != ME && "MI already at terminator")
[all...] |
| CriticalAntiDepBreaker.cpp | 110 void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
112 if (MI->isDebugValue())
136 PrescanInstruction(MI);
137 ScanInstruction(MI, Count);
162 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
179 bool Special = MI->isCall() ||
180 MI->hasExtraSrcRegAllocReq() ||
181 TII->isPredicated(MI);
185 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
186 MachineOperand &MO = MI->getOperand(i)
[all...] |
| MachineVerifier.cpp | 200 void visitMachineBundleBefore(const MachineInstr *MI);
201 void visitMachineInstrBefore(const MachineInstr *MI);
203 void visitMachineInstrAfter(const MachineInstr *MI);
204 void visitMachineBundleAfter(const MachineInstr *MI);
210 void report(const char *msg, const MachineInstr *MI);
217 void verifyInlineAsm(const MachineInstr *MI);
378 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
379 assert(MI);
380 report(msg, MI->getParent());
382 if (Indexes && Indexes->hasIndex(MI))
[all...] |
| ScheduleDAGInstrs.cpp | 38 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
40 cl::desc("Enable use of AA during MI GAD construction"));
105 static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
109 if (!MI->hasOneMemOperand() ||
110 !(*MI->memoperands_begin())->getValue() ||
111 (*MI->memoperands_begin())->isVolatile())
114 const Value *V = (*MI->memoperands_begin())->getValue();
298 const MachineInstr *MI = SU->getInstr();
299 const MachineOperand &MO = MI->getOperand(OperIdx);
323 unsigned AOLat = TII->getOutputLatency(InstrItins, MI, OperIdx
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 213 getDebugValueLocation(const MachineInstr *MI) const {
215 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
330 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
332 const MachineOperand &MO = MI->getOperand(OpNum);
417 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum
[all...] |
| Thumb1RegisterInfo.cpp | 366 static void removeOperands(MachineInstr &MI, unsigned i) {
368 for (unsigned e = MI.getNumOperands(); i != e; ++i)
369 MI.RemoveOperand(Op);
390 MachineInstr &MI = *II;
391 MachineBasicBlock &MBB = *MI.getParent();
392 DebugLoc dl = MI.getDebugLoc();
393 unsigned Opcode = MI.getOpcode();
394 const MCInstrDesc &Desc = MI.getDesc();
398 Offset += MI.getOperand(FrameRegIdx+1).getImm();
414 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL)
[all...] |
| Thumb2InstrInfo.cpp | 388 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
391 unsigned Opcode = MI.getOpcode();
392 const MCInstrDesc &Desc = MI.getDesc();
401 Offset += MI.getOperand(FrameRegIdx+1).getImm();
404 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
406 MI.setDesc(TII.get(ARM::tMOVr));
407 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
409 do MI.RemoveOperand(FrameRegIdx+1);
410 while (MI.getNumOperands() > FrameRegIdx+1);
411 MachineInstrBuilder MIB(&MI);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.cpp | 130 MachineInstr &MI = *II;
131 MachineFunction &MF = *MI.getParent()->getParent();
135 while (!MI.getOperand(i).isFI()) {
137 assert(i < MI.getNumOperands() &&
144 dbgs() << "<--------->\n" << MI);
146 int FrameIndex = MI.getOperand(i).getIndex();
162 Offset += MI.getOperand(oi).getImm();
166 MI.getOperand(oi).ChangeToImmediate(Offset);
167 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
|
| MBlazeInstrInfo.cpp | 44 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {
45 if (MI->getOpcode() == MBlaze::LWI) {
46 if ((MI->getOperand(1).isFI()) && // is a stack slot
47 (MI->getOperand(2).isImm()) && // the imm is zero
48 (isZeroImm(MI->getOperand(2)))) {
49 FrameIndex = MI->getOperand(1).getIndex();
50 return MI->getOperand(0).getReg();
63 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {
64 if (MI->getOpcode() == MBlaze::SWI) {
65 if ((MI->getOperand(1).isFI()) && // is a stack slo
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 97 MachineInstr *MI =
101 MI->getOperand(3).setIsDead();
159 MachineInstr *MI =
164 MI->getOperand(3).setIsDead();
169 MachineInstr *MI =
173 MI->getOperand(3).setIsDead();
181 MachineBasicBlock::iterator MI,
188 if (MI != MBB.end()) DL = MI->getDebugLoc();
199 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)
[all...] |
| MSP430RegisterInfo.cpp | 170 MachineInstr &MI = *II;
171 MachineBasicBlock &MBB = *MI.getParent();
174 DebugLoc dl = MI.getDebugLoc();
175 while (!MI.getOperand(i).isFI()) {
177 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
180 int FrameIndex = MI.getOperand(i).getIndex();
194 Offset += MI.getOperand(i+1).getImm();
196 if (MI.getOpcode() == MSP430::ADD16ri) {
201 MI.setDesc(TII.get(MSP430::MOV16rr));
202 MI.getOperand(i).ChangeToRegister(BasePtr, false)
[all...] |
