| /external/llvm/lib/CodeGen/ |
| PostRASchedulerList.cpp | 164 void Observe(MachineInstr *MI, unsigned Count);
185 bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
316 MachineInstr *MI = llvm::prior(I);
320 if (MI->isCall() || TII->isSchedulingBoundary(MI, MBB, Fn)) {
325 Current = MI;
327 Scheduler.Observe(MI, CurrentCount);
329 I = MI;
331 if (MI->isBundle())
332 Count -= MI->getBundleSize()
[all...] |
| RegisterCoalescer.cpp | 100 void LRE_WillEraseInstruction(MachineInstr *MI);
202 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
205 if (MI->isCopy()) {
206 Dst = MI->getOperand(0).getReg();
207 DstSub = MI->getOperand(0).getSubReg();
208 Src = MI->getOperand(1).getReg();
209 SrcSub = MI->getOperand(1).getSubReg();
210 } else if (MI->isSubregToReg()) {
211 Dst = MI->getOperand(0).getReg();
212 DstSub = compose(tri, MI->getOperand(0).getSubReg()
[all...] |
| LiveVariables.cpp | 132 MachineInstr *MI) {
143 VRInfo.Kills.back() = MI;
174 VRInfo.Kills.push_back(MI);
182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
187 VRInfo.Kills.push_back(MI);
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
274 PhysRegUse[Reg] = MI;
276 PhysRegUse[*SubRegs] = MI;
311 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
397 } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
[all...] |
| LiveIntervalAnalysis.cpp | 166 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
167 unsigned Reg = MI.getOperand(MOIdx).getReg();
168 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
169 const MachineOperand &MO = MI.getOperand(i);
173 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
174 MI.getOperand(MOIdx).getSubReg() &&
201 MachineBasicBlock::iterator mi,
231 if (vi.Kills[0] != mi)
297 if (MultipleDefsBySameMI(*mi, MOIdx))
313 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx))
[all...] |
| /external/clang/lib/Lex/ |
| PPDirectives.cpp | 50 return &(MIChain->MI);
54 MacroInfo *MI = AllocateMacroInfo();
55 new (MI) MacroInfo(L);
56 return MI;
60 MacroInfo *MI = AllocateMacroInfo();
61 new (MI) MacroInfo(MacroToClone, BP);
62 return MI;
67 void Preprocessor::ReleaseMacroInfo(MacroInfo *MI) {
68 MacroInfoChain *MIChain = (MacroInfoChain*) MI;
83 MI->Destroy()
[all...] |
| MacroArgs.h | 62 static MacroArgs *create(const MacroInfo *MI,
87 getPreExpArgument(unsigned Arg, const MacroInfo *MI, Preprocessor &PP);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 184 static bool isCSRestore(MachineInstr *MI, const uint16_t *CSRegs) {
185 if (MI->getOpcode() == ARM::tLDRspi &&
186 MI->getOperand(1).isFI() &&
187 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
189 else if (MI->getOpcode() == ARM::tPOP) {
192 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
193 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
292 MachineBasicBlock::iterator MI,
302 if (MI != MBB.end()) DL = MI->getDebugLoc()
[all...] |
| ARMFrameLowering.cpp | 37 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
93 static bool isCSRestore(MachineInstr *MI,
97 if (MI->getOpcode() == ARM::LDMIA_RET ||
98 MI->getOpcode() == ARM::t2LDMIA_RET ||
99 MI->getOpcode() == ARM::LDMIA_UPD ||
100 MI->getOpcode() == ARM::t2LDMIA_UPD ||
101 MI->getOpcode() == ARM::VLDMDIA_UPD) {
104 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
105 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
109 if ((MI->getOpcode() == ARM::LDR_POST_IMM |
[all...] |
| ARM.h | 46 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
|
| ARMMCInstLower.cpp | 114 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
116 OutMI.setOpcode(MI->getOpcode());
118 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
119 const MachineOperand &MO = MI->getOperand(i);
|
| ARMBaseRegisterInfo.cpp | 803 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
804 const MCInstrDesc &Desc = MI->getDesc();
813 InstrOffs = MI->getOperand(Idx+1).getImm();
818 const MachineOperand &OffOp = MI->getOperand(Idx+1);
827 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
828 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
834 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
835 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
841 InstrOffs = MI->getOperand(ImmIdx).getImm();
857 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LexicalScopes.h | 183 /// openInsnRange - This scope covers instruction range starting from MI.
184 void openInsnRange(const MachineInstr *MI) {
186 FirstInsn = MI;
189 Parent->openInsnRange(MI);
194 void extendInsnRange(const MachineInstr *MI) {
195 assert (FirstInsn && "MI Range is not open!");
196 LastInsn = MI;
198 Parent->extendInsnRange(MI);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.h | 146 EmitCustomShift(MachineInstr *MI, MachineBasicBlock *MBB) const;
149 EmitCustomSelect(MachineInstr *MI, MachineBasicBlock *MBB) const;
152 EmitCustomAtomic(MachineInstr *MI, MachineBasicBlock *MBB) const;
155 EmitInstrWithCustomInserter(MachineInstr *MI,
|
| /external/llvm/lib/Target/Mips/ |
| MipsMCInstLower.h | 35 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
|
| MipsDelaySlotFiller.cpp | 79 void insertCallUses(InstrIter MI,
83 void insertDefsUses(InstrIter MI,
234 // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
235 void Filler::insertDefsUses(InstrIter MI,
238 // If MI is a call or return, just examine the explicit non-variadic operands.
239 MCInstrDesc MCID = MI->getDesc();
240 unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
241 MI->getNumOperands();
244 if (MI->isCall()
[all...] |
| MipsSEInstrInfo.cpp | 42 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
44 unsigned Opc = MI->getOpcode();
50 if ((MI->getOperand(1).isFI()) && // is a stack slot
51 (MI->getOperand(2).isImm()) && // the imm is zero
52 (isZeroImm(MI->getOperand(2)))) {
53 FrameIndex = MI->getOperand(1).getIndex();
54 return MI->getOperand(0).getReg();
67 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
69 unsigned Opc = MI->getOpcode();
75 if ((MI->getOperand(1).isFI()) && // is a stack slo
[all...] |
| MipsInstrInfo.h | 61 MachineBasicBlock::iterator MI) const;
72 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 113 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI,
119 unsigned TSFlags = (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >>
124 MachineOperand dest = MI.getOperand(0);
125 MachineOperand src = MI.getOperand(1);
137 bool NVPTXInstrInfo::isReadSpecialReg(MachineInstr &MI) const
139 switch (MI.getOpcode()) {
159 bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
162 unsigned TSFlags = (MI.getDesc().TSFlags & NVPTX::isLoadMask) >>
166 AddrSpace = getLdStCodeAddrSpace(MI);
170 bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPC.h | 38 void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.h | 41 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 67 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
71 switch (MI->getOpcode()) {
78 if (MI->getOperand(2).isFI() &&
79 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
80 FrameIndex = MI->getOperand(2).getIndex();
81 return MI->getOperand(0).getReg();
94 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96 switch (MI->getOpcode()) {
102 if (MI->getOperand(2).isFI() &
[all...] |
| HexagonHardwareLoops.cpp | 91 bool isInductionOperation(const MachineInstr *MI, unsigned IVReg) const;
95 bool isInvalidLoopOperation(const MachineInstr *MI) const;
203 static bool isHardwareLoop(const MachineInstr *MI) {
204 return MI->getOpcode() == Hexagon::LOOP0_r ||
205 MI->getOpcode() == Hexagon::LOOP0_i;
210 static bool isCompareEqualsImm(const MachineInstr *MI) {
211 return MI->getOpcode() == Hexagon::CMPEQri;
335 const MachineInstr *MI = IV_Opnd->getParent();
336 if (L->contains(MI) && isCompareEqualsImm(MI)) {
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 259 MachineInstr &MI = *II;
260 MachineBasicBlock &MBB = *MI.getParent();
265 while (!MI.getOperand(i).isFI()) {
267 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
270 MachineOperand &SPOp = MI.getOperand(i);
280 if (MI.getOpcode() == SPU::AIr32 || MI.getOpcode() == SPU::ILAr32)
283 MachineOperand &MO = MI.getOperand(OpNo);
297 if ((MI.getOpcode() == SPU::AIr32 && !isInt<10>(Offset))
299 int newOpcode = convertDFormToXForm(MI.getOpcode())
[all...] |
| SPUInstrInfo.h | 42 unsigned isLoadFromStackSlot(const MachineInstr *MI,
44 unsigned isStoreToStackSlot(const MachineInstr *MI,
|
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 122 MachineBasicBlock::iterator MI,
133 MachineBasicBlock::iterator MI,
|
