| /external/llvm/lib/CodeGen/ |
| MachineTraceMetrics.cpp | 90 const MachineInstr *MI = I;
91 if (MI->isTransient())
94 if (MI->isCall())
517 // A data dependency is represented as a defining MI and operand numbers on the
518 // defining and using MI.
592 const MachineInstr *MI;
597 LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(0), Op(0) {}
631 Deps.push_back(DataDep(I->MI, I->Op, MO.getOperandNo()));
648 LRU.MI = UseMI;
767 // Identify physreg dependencies for MI when scanning instructions upwards
[all...] |
| ExecutionDepsFix.cpp | 433 void ExeDepsFix::visitInstr(MachineInstr *MI) {
434 if (MI->isDebugValue())
438 std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(MI);
441 visitSoftInstr(MI, DomP.second);
443 visitHardInstr(MI, DomP.first);
448 processDefs(MI, !DomP.first);
451 // Update def-ages for registers defined by MI.
453 void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
454 assert(!MI->isDebugValue() && "Won't process debug values");
455 const MCInstrDesc &MCID = MI->getDesc()
[all...] |
| MachineInstr.cpp | 56 if (MachineInstr *MI = getParent())
57 if (MachineBasicBlock *MBB = MI->getParent())
98 if (MachineInstr *MI = getParent())
99 if (MachineBasicBlock *MBB = MI->getParent())
118 if (MachineInstr *MI = getParent())
119 if (MachineBasicBlock *MBB = MI->getParent())
134 if (MachineInstr *MI = getParent())
135 if (MachineBasicBlock *MBB = MI->getParent())
259 if (const MachineInstr *MI = getParent())
260 if (const MachineBasicBlock *MBB = MI->getParent()
[all...] |
| SplitKit.cpp | 488 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
489 assert(MI && "enterIntvBefore called with invalid index");
491 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
505 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
506 assert(MI && "enterIntvAfter called with invalid index");
508 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
509 llvm::next(MachineBasicBlock::iterator(MI)));
555 MachineInstr *MI = LIS.getInstructionFromIndex(Boundary);
556 assert(MI && "No instruction at index")
[all...] |
| LiveDebugVariables.cpp | 307 /// @param MI DBG_VALUE instruction
310 bool handleDebugValue(MachineInstr *MI, SlotIndex Idx);
441 bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) {
443 if (MI->getNumOperands() != 3 ||
444 !MI->getOperand(1).isImm() || !MI->getOperand(2).isMetadata()) {
445 DEBUG(dbgs() << "Can't handle " << *MI);
450 unsigned Offset = MI->getOperand(1).getImm();
451 const MDNode *Var = MI->getOperand(2).getMetadata();
452 UserValue *UV = getUserValue(Var, Offset, MI->getDebugLoc())
[all...] |
| MachineTraceMetrics.h | 242 /// Return the depth and height of MI. The depth is only valid for
245 InstrCycles getInstrCycles(const MachineInstr *MI) const {
246 return TE.Cycles.lookup(MI);
249 /// Return the slack of MI. This is the number of cycles MI can be delayed
251 /// MI must be an instruction in the trace center block.
252 unsigned getInstrSlack(const MachineInstr *MI) const;
|
| /external/clang/lib/Lex/ |
| MacroArgs.cpp | 25 MacroArgs *MacroArgs::create(const MacroInfo *MI,
28 assert(MI->isFunctionLike() &&
148 MacroArgs::getPreExpArgument(unsigned Arg, const MacroInfo *MI,
150 assert(Arg < MI->getNumArgs() && "Invalid argument number!");
153 if (PreExpArgTokens.size() < MI->getNumArgs())
154 PreExpArgTokens.resize(MI->getNumArgs());
|
| /external/llvm/include/llvm/CodeGen/ |
| AsmPrinter.h | 183 void emitPrologLabel(const MachineInstr &MI);
405 virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
435 virtual void PrintSpecial(const MachineInstr *MI, raw_ostream &OS,
438 /// PrintAsmOperand - Print the specified operand of MI, an INLINEASM
442 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
446 /// PrintAsmMemoryOperand - Print the specified operand of MI, an INLINEASM
450 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
469 void EmitInlineAsm(const MachineInstr *MI) const;
|
| SlotIndexes.h | 38 MachineInstr *mi; member in class:llvm::IndexListEntry
43 IndexListEntry(MachineInstr *mi, unsigned index) : mi(mi), index(index) {}
45 MachineInstr* getInstr() const { return mi; }
46 void setInstr(MachineInstr *mi) {
47 this->mi = mi;
330 IndexListEntry* createEntry(MachineInstr *mi, unsigned index) {
336 new (entry) IndexListEntry(mi, index)
[all...] |
| MachineRegisterInfo.h | 542 MachineInstr *MI = Op->getParent();
544 while (Op && Op->getParent() == MI);
545 return MI;
550 MachineInstr *MI = getBundleStart(Op->getParent());
552 while (Op && getBundleStart(Op->getParent()) == MI);
553 return MI;
|
| LiveRangeEdit.h | 41 virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
167 /// instruction into MBB before MI. The new instruction is mapped, but
171 MachineBasicBlock::iterator MI,
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCalls.cpp | 33 Instruction *InstCombiner::SimplifyMemTransfer(MemIntrinsic *MI) {
34 unsigned DstAlign = getKnownAlignment(MI->getArgOperand(0), TD);
35 unsigned SrcAlign = getKnownAlignment(MI->getArgOperand(1), TD);
37 unsigned CopyAlign = MI->getAlignment();
40 MI->setAlignment(ConstantInt::get(MI->getAlignmentType(),
42 return MI;
47 ConstantInt *MemOpLength = dyn_cast<ConstantInt>(MI->getArgOperand(2));
62 cast<PointerType>(MI->getArgOperand(1)->getType())->getAddressSpace();
64 cast<PointerType>(MI->getArgOperand(0)->getType())->getAddressSpace()
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 272 EmitInstrWithCustomInserter(MachineInstr *MI,
276 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
513 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
516 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
520 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
526 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
532 void SetupEntryBlockForSjLj(MachineInstr *MI,
536 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
539 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
541 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
[all...] |
| ARMBaseRegisterInfo.h | 139 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
140 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
146 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
|
| /external/webkit/Source/WebKit/android/content/ |
| address_detector.cpp | 696 MI = 26, // MI Michigan
781 MI, MI, MI, MI, MI, MI, MI, MI, MI, MI, // 480-48
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfDebug.cpp | [all...] |
| /external/clang/include/clang/Lex/ |
| Preprocessor.h | 270 MacroInfo *MI;
272 MacroExpandsInfo(Token Tok, MacroInfo *MI, SourceRange Range)
273 : Tok(Tok), MI(MI), Range(Range) { }
353 MacroInfo MI;
471 void setMacroInfo(IdentifierInfo *II, MacroInfo *MI,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 224 const MachineInstr& MI) {
227 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
228 if ((MI.getOpcode() == Mips::ADDiu) &&
229 (MI.getOperand(1).getReg() == Mips::ZERO) &&
230 (MI.getOperand(2).getImm() == 0)) {
231 DstReg = MI.getOperand(0).getReg();
233 } else if ((MI.getOpcode() == Mips::DADDiu) &&
234 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
235 (MI.getOperand(2).getImm() == 0)) {
236 DstReg = MI.getOperand(0).getReg()
[all...] |
| MipsISelLowering.h | 174 EmitInstrWithCustomInserter(MachineInstr *MI,
212 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
214 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
217 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
219 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCMCInstLower.cpp | 144 void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
146 OutMI.setOpcode(MI->getOpcode());
148 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
149 const MachineOperand &MO = MI->getOperand(i);
154 MI->dump();
|
| PPCFrameLowering.cpp | 52 static void RemoveVRSaveCode(MachineInstr *MI) {
53 MachineBasicBlock *Entry = MI->getParent();
56 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
57 MachineBasicBlock::iterator MBBI = MI;
84 MBBI = MI;
92 MI->eraseFromParent();
95 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
98 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
99 MachineFunction *MF = MI->getParent()->getParent();
100 DebugLoc dl = MI->getDebugLoc()
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| ValueMapper.cpp | 190 MI = MDs.begin(), ME = MDs.end(); MI != ME; ++MI) {
191 MDNode *Old = MI->second;
194 I->setMetadata(MI->first, New);
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
177 MI->setFlag(MachineInstr::FrameSetup);
183 MachineInstr *MI = NULL;
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
192 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
196 MI->setFlag(MachineInstr::FrameSetup);
525 MachineInstr &MI = *MBBI;
526 unsigned Opc = MI.getOpcode();
528 if (!MI.getFlag(MachineInstr::FrameSetup)) break
[all...] |
| X86InstrBuilder.h | 149 MachineInstr *MI = MIB;
150 MachineFunction &MF = *MI->getParent()->getParent();
152 const MCInstrDesc &MCID = MI->getDesc();
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.h | 186 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
194 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
229 MachineBasicBlock::iterator MI) const;
|
