| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 447 case Instruction::Sub: {
[all...] |
| InstCombineAndOrXor.cpp | 335 /// where isSub determines whether the operator is a sub. If we can fold one of
[all...] |
| InstructionCombining.cpp | 124 // not overflow. This function only handles the Add and Sub opcodes. For
132 // We reason about Add and Sub Only.
135 Opcode != Instruction::Sub) {
343 case Instruction::Sub:
491 // dyn_castNegVal - Given a 'sub' instruction, return the RHS of the instruction
[all...] |
| /external/llvm/lib/VMCore/ |
| Instructions.cpp | [all...] |
| Constants.cpp | 293 if (CE->getOpcode() == Instruction::Sub) {
[all...] |
| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 337 case 1:{Op = (isFloat?Instruction::FSub : Instruction::Sub); break; }
|
| /external/llvm/unittests/Support/ |
| ConstantRangeTest.cpp | 348 TEST_F(ConstantRangeTest, Sub) {
349 EXPECT_EQ(Full.sub(APInt(16, 4)), Full);
350 EXPECT_EQ(Full.sub(Full), Full);
351 EXPECT_EQ(Full.sub(Empty), Empty);
352 EXPECT_EQ(Full.sub(One), Full);
353 EXPECT_EQ(Full.sub(Some), Full);
354 EXPECT_EQ(Full.sub(Wrap), Full);
355 EXPECT_EQ(Empty.sub(Empty), Empty);
356 EXPECT_EQ(Empty.sub(One), Empty);
357 EXPECT_EQ(Empty.sub(Some), Empty)
[all...] |
| /external/opencv/cxcore/src/ |
| _cxipp.h | 118 IPCV_BIN_ARITHM( Sub )
[all...] |
| cxarithm.cpp | 242 ICV_DEF_BIN_ARI_ALL( CV_SUB_R, Sub, CV_FAST_CAST_8U )
259 ICV_DEF_INIT_ARITHM_FUNC_TAB( Sub, C1R )
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | 433 return Ty->isFPOrFPVectorTy() ? Instruction::FSub : Instruction::Sub;
456 case bitc::RMW_SUB: return AtomicRMWInst::Sub;
[all...] |
| /external/clang/lib/Serialization/ |
| ASTReader.cpp | [all...] |
| /external/llvm/lib/Bitcode/Writer/ |
| BitcodeWriter.cpp | 94 case Instruction::Sub:
118 case AtomicRMWInst::Sub: return bitc::RMW_SUB;
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | 231 e.opcode = Instruction::Sub;
402 case Instruction::Sub:
[all...] |
| SCCP.cpp | [all...] |
| /frameworks/compile/slang/BitWriter_2_9_func/ |
| BitcodeWriter.cpp | 84 case Instruction::Sub:
108 case AtomicRMWInst::Sub: return bitc::RMW_SUB;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| FastISel.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | 244 Imag = Builder.CreateFSub(Zero, Imag, "sub");
[all...] |
| CGExpr.cpp | [all...] |
| /external/llvm/lib/AsmParser/ |
| LLParser.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | 192 return Ty->isFPOrFPVectorTy() ? Instruction::FSub : Instruction::Sub;
[all...] |
| /external/clang/lib/Sema/ |
| SemaCodeComplete.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 363 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
477 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
717 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
[all...] |
| /external/v8/src/arm/ |
| lithium-arm.h | 329 // Can't use the DECLARE-macro here because of sub-classes.
895 DECLARE_CONCRETE_INSTRUCTION(SubI, "sub-i")
896 DECLARE_HYDROGEN_ACCESSOR(Sub)
[all...] |
