/external/llvm/lib/Target/ARM/ |
ARMExpandPseudoInsts.cpp | 42 const ARMBaseInstrInfo *TII; 384 TII->get(TableEntry->RealOpc)); 449 TII->get(TableEntry->RealOpc)); 501 TII->get(TableEntry->RealOpc)); 584 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 626 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 627 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) [all...] |
ARMConstantIslandPass.cpp | 259 const ARMBaseInstrInfo *TII; 384 TII = (const ARMBaseInstrInfo*)MF->getTarget().getInstrInfo(); 545 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY)) 805 BBI.Size += TII->GetInstSizeInBytes(I); 836 Offset += TII->GetInstSizeInBytes(I); [all...] |
Thumb1RegisterInfo.h | 28 Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI); 56 const ARMBaseInstrInfo &TII) const;
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ARMBaseInstrInfo.h | 380 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 386 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 390 int NumBytes, const TargetInstrInfo &TII, 401 const ARMBaseInstrInfo &TII); 405 const ARMBaseInstrInfo &TII);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.cpp | 112 const TargetInstrInfo *TII, 123 const MCInstrDesc &II = TII->get(Def->getMachineOpcode()); 228 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || 257 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads)) 299 const MCInstrDesc &MCID = TII->get(Opc); 358 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) 376 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) 434 const MCInstrDesc &MCID = TII->get(Opc); 448 TII->get(N->getMachineOpcode()).getImplicitDefs()) { 453 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs() [all...] |
InstrEmitter.cpp | 132 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 219 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 279 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 316 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 322 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 448 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 487 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 497 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg) [all...] |
FastISel.cpp | 216 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 559 TII.get(TargetOpcode::INLINEASM)) 624 TII.get(TargetOpcode::DBG_VALUE)) 636 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 764 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 846 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL, [all...] |
/external/llvm/lib/CodeGen/ |
DeadMachineInstructionElim.cpp | 34 const TargetInstrInfo *TII; 63 if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI()) 91 TII = MF.getTarget().getInstrInfo();
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ProcessImplicitDefs.cpp | 28 const TargetInstrInfo *TII; 92 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); 144 TII = MF.getTarget().getInstrInfo();
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LiveRangeEdit.cpp | 50 if (!TII.isTriviallyReMaterializable(DefMI, aa)) 142 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri); 190 if (!DefMI->isSafeToMove(&TII, 0, SawStore)) 200 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI); 233 if (!MI->isSafeToMove(&TII, 0, SawStore)) { 287 MI->setDesc(TII.get(TargetOpcode::KILL));
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EarlyIfConversion.cpp | 81 const TargetInstrInfo *TII; 155 TII = MF.getTarget().getInstrInfo(); 222 if (!I->isSafeToMove(TII, 0, DontMoveAcrossStore)) { 388 if (TII->AnalyzeBranch(*Head, TBB, FBB, Cond)) { 422 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg, 464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 485 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 541 TII->RemoveBranch(*Head); 568 TII->InsertBranch(*Head, Tail, 0, EmptyCond, HeadDL); 581 const TargetInstrInfo *TII; [all...] |
TwoAddressInstructionPass.cpp | 65 const TargetInstrInfo *TII; 196 if (!MI->isSafeToMove(TII, AA, SeenStore)) 332 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, 368 const TargetInstrInfo *TII) { 385 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 415 const TargetInstrInfo *TII, 426 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { 542 MachineInstr *NewMI = TII->commuteInstruction(MI); 599 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV); 641 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy [all...] |
CriticalAntiDepBreaker.h | 37 const TargetInstrInfo *TII;
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CodePlacementOpt.cpp | 34 const TargetInstrInfo *TII; 79 if (TII->AnalyzeBranch(*MBB, TBB, FBB, Cond)) 109 if (TII->AnalyzeBranch(*MBB, TBB, FBB, Cond)) 120 if (!Cond.empty() && TII->ReverseBranchCondition(Cond)) 415 TII = MF.getTarget().getInstrInfo();
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TailDuplication.cpp | 62 const TargetInstrInfo *TII; 131 TII = MF.getTarget().getInstrInfo(); 424 MachineInstr *NewMI = TII->duplicate(MI, MF); 654 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) 685 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) 723 TII->RemoveBranch(*PredBB); 726 TII->InsertBranch(*PredBB, PredTBB, PredFBB, PredCond, DebugLoc()); 773 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) 787 TII->RemoveBranch(*PredBB); 828 TII->get(TargetOpcode::COPY) [all...] |
DFAPacketizer.cpp | 131 TII = TM.getInstrInfo(); 132 ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
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/external/llvm/lib/Target/MBlaze/ |
MBlazeRegisterInfo.cpp | 45 MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii) 46 : MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {} 107 New = BuildMI(MF,Old->getDebugLoc(),TII.get(MBlaze::ADDIK),MBlaze::R1) 111 New = BuildMI(MF,Old->getDebugLoc(),TII.get(MBlaze::ADDIK),MBlaze::R1)
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MBlazeISelLowering.cpp | 251 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 295 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT) 300 BuildMI(MBB, dl, TII->get(MBlaze::ADDIK), IVAL) 304 BuildMI(MBB, dl, TII->get(MBlaze::BEQID)) 310 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST) 316 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT) 321 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST); 323 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST); 325 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST); 329 BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT [all...] |
/external/llvm/lib/Target/X86/ |
X86VZeroUpper.cpp | 44 const TargetInstrInfo *TII; // Machine instruction info. 139 TII = MF.getTarget().getInstrInfo(); 254 BuildMI(BB, I, dl, TII->get(X86::VZEROUPPER));
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X86RegisterInfo.h | 30 const TargetInstrInfo &TII; 59 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
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/external/llvm/include/llvm/CodeGen/ |
LiveRangeEdit.h | 63 const TargetInstrInfo &TII; 73 /// tii.isTriviallyReMaterializable(). 110 TII(*MF.getTarget().getInstrInfo()),
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/external/llvm/lib/Target/Hexagon/ |
HexagonRegisterInfo.h | 47 const HexagonInstrInfo &TII; 49 HexagonRegisterInfo(HexagonSubtarget &st, const HexagonInstrInfo &tii);
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/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.h | 32 const TargetInstrInfo &TII; 34 PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
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PPCCTRLoops.cpp | 62 const TargetInstrInfo *TII; 210 TII = MF.getTarget().getInstrInfo(); 642 TII->get(CopyOp), CountReg).addReg(TripCount->getReg()); 647 TII->get(isPPC64 ? PPC::NEG8 : PPC::NEG), 660 TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), 665 TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI), 669 TII->get(isPPC64 ? PPC::LI8 : PPC::LI), 676 TII->get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(CountReg, 706 TII->get((BranchTarget == LoopStart) ?
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/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.h | 28 const TargetInstrInfo &TII; 43 XCoreRegisterInfo(const TargetInstrInfo &tii);
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