| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.cpp | [all...] |
| LegalizeTypes.h | 63 /// enum from TargetLowering. This can be queried with "getTypeAction(VT)".
67 TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const {
68 return TLI.getTypeAction(*DAG.getContext(), VT);
72 bool isTypeLegal(EVT VT) const {
73 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
151 bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
152 bool CustomWidenLowerNode(SDNode *N, EVT VT);
170 SDValue PromoteTargetBoolean(SDValue Bool, EVT VT);
[all...] |
| LegalizeTypesGeneric.cpp | 384 EVT VT = N->getValueType(0);
385 assert(VT.getVectorElementType() == N->getOperand(0).getValueType() &&
387 unsigned NumElts = VT.getVectorNumElements();
393 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
|
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 761 EVT VT = N.getValueType();
764 SDValue NewMask = DAG.getConstant(0xff, VT);
765 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
766 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
768 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
809 EVT VT = N.getValueType();
811 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
812 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
813 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
[all...] |
| X86AsmPrinter.cpp | 246 EVT VT = (strcmp(Modifier+6,"64") == 0) ?
249 Reg = getX86SubSuperRegister(Reg, VT);
|
| X86RegisterInfo.cpp | 593 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
594 switch (VT.getSimpleVT().SimpleTy) {
|
| /external/clang/lib/Analysis/ |
| LiveVariables.cpp | 225 while (const ArrayType *VT = dyn_cast<ArrayType>(ty)) {
226 if (const VariableArrayType *VAT = dyn_cast<VariableArrayType>(VT))
230 ty = VT->getElementType().getTypePtr();
|
| /external/clang/lib/CodeGen/ |
| CodeGenTypes.cpp | 443 const VectorType *VT = cast<VectorType>(Ty);
444 ResultType = llvm::VectorType::get(ConvertType(VT->getElementType()),
445 VT->getNumElements());
|
| TargetInfo.cpp | 644 if (const VectorType *VT = RetTy->getAs<VectorType>()) {
659 (Size == 64 && VT->getNumElements() == 1))
868 if (const VectorType *VT = Ty->getAs<VectorType>()) {
874 (Size == 64 && VT->getNumElements() == 1))
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 193 EVT MBlazeTargetLowering::getSetCCResultType(EVT VT) const {
[all...] |
| /external/clang/lib/AST/ |
| Type.cpp | 581 if (const VectorType *VT = dyn_cast<VectorType>(CanonicalType))
582 return VT->getElementType()->isIntegerType();
717 if (const VectorType *VT = dyn_cast<VectorType>(CanonicalType))
718 return VT->getElementType()->isSignedIntegerType();
757 if (const VectorType *VT = dyn_cast<VectorType>(CanonicalType))
758 return VT->getElementType()->isUnsignedIntegerType();
773 if (const VectorType *VT = dyn_cast<VectorType>(CanonicalType))
774 return VT->getElementType()->isFloatingType();
[all...] |
| ExprConstant.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 446 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
450 if (VT == MVT::i1) {
452 } else if (VT == MVT::i32 || VT == MVT::f32) {
454 } else if (VT == MVT::i64 || VT == MVT::f64) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 228 void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 154 EVT VT) const;
|
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherGen.cpp | 27 MVT::SimpleValueType VT = MVT::Other;
38 VT = RC.getValueTypeNum(0);
43 assert(VT == RC.getValueTypeNum(0));
45 return VT;
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 80 EVT vt = CN->getValueType(0); local
82 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
84 } else if (vt == MVT::i32) {
97 EVT vt = FPN->getValueType(0); local
98 if (vt == MVT::f32) {
572 \arg VT the value type for which we want a register class
574 SDValue SPUDAGToDAGISel::getRC( MVT VT ) {
575 switch( VT.SimpleTy ) {
834 EVT VT = N->getValueType(0)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 101 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
103 bool hasType(EVT vt) const {
105 if (EVT(VTs[i]) == vt)
302 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | 783 EVT VT = *RC->vt_begin();
784 if (VT == MVT::Untyped) {
788 RCId = TLI->getRepRegClassFor(VT)->getID();
789 RCCost = TLI->getRepRegClassCostFor(VT);
[all...] |
| /external/llvm/include/llvm/ |
| Constants.h | 549 explicit ConstantDataSequential(Type *ty, ValueTy VT, const char *Data)
550 : Constant(ty, VT, 0, 0), DataElements(Data), Next(0) {}
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 138 if (VectorType *VT = dyn_cast<VectorType>(BCI->getOperand(0)->getType()))
139 if (VT->getNumElements() == VectorWidth)
|
| /external/llvm/lib/Transforms/Scalar/ |
| ScalarReplAggregates.cpp | [all...] |
| /external/llvm/lib/VMCore/ |
| Verifier.cpp | 296 int VT, unsigned ArgNo, std::string &Suffix);
[all...] |
| Instructions.cpp | 65 if (VectorType *VT = dyn_cast<VectorType>(Op0->getType())) {
67 if (VT->getElementType() != Type::getInt1Ty(Op0->getContext()))
72 if (ET->getNumElements() != VT->getNumElements())
[all...] |
| /external/clang/lib/Sema/ |
| SemaExprMember.cpp | 371 QualType VT = S.Context.getExtVectorType(vecType->getElementType(), CompSize);
378 if ((*I)->getUnderlyingType() == VT)
382 return VT; // should never get here (a typedef type should always be found).
[all...] |
