| /external/llvm/test/CodeGen/X86/ |
| 2011-12-8-bitcastintprom.ll | 3 ; Make sure that the conversion between v4i8 to v2i16 is not a simple bitcast.
|
| /external/clang/test/CodeGen/ |
| builtins-mips.c | 10 typedef signed char v4i8 __attribute__ ((vector_size(4))); typedef
19 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c;
27 v4i8_a = (v4i8) {1, 2, 3, 0xFF};
28 v4i8_b = (v4i8) {2, 4, 6, 8};
91 v4i8_a = (v4i8) {1, 2, 3, 4};
124 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
142 v4i8_a = (v4i8) {1, 2, 3, 4};
145 v4i8_a = (v4i8) {128, 64, 32, 16};
168 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7};
211 v4i8_b = (v4i8) {1, 2, 3, 4}
[all...] |
| /bionic/libc/arch-mips/string/ |
| mips-string-ops.h | 98 typedef signed char v4i8 __attribute__ ((vector_size (4))); typedef
101 ((unsigned) __builtin_mips_subu_s_qb((v4i8) __01s,(v4i8) __x))
|
| /external/llvm/lib/VMCore/ |
| ValueTypes.cpp | 124 case MVT::v4i8: return "v4i8";
175 case MVT::v4i8: return VectorType::get(Type::getInt8Ty(Context), 4);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 223 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_avar; break;
253 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_asi; break;
283 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_ari; break;
312 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_areg; break;
409 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_avar; break;
440 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_asi; break;
471 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_ari; break;
500 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_areg; break;
|
| NVPTXVector.td | 49 // Extract v4i8
54 (v4i8 V4I8Regs:$src), imm:$c))],
116 // Insert v4i8
274 def V4I8 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "16")>, OpNode, V4I8Regs,
308 def V4I8 : VecUnaryOp<V4UnaryStr<!strconcat(asmstr, "16")>, OpNode,
[all...] |
| NVPTXRegisterInfo.td | 107 : NVPTXVecRegClass<[v4i8], 32, (add (sequence "v4b8_%u", 0, 395)),
|
| NVPTXISelLowering.cpp | 100 addRegisterClass(MVT::v4i8, &NVPTX::V4I8RegsRegClass);
105 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i8 , Custom);
116 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i8 , Custom);
199 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i8 , Custom);
[all...] |
| gen-register-defs.py | 174 outFile.write('def V4I8Regs\n : NVPTXVecRegClass<[v4i8], 32, (add (sequence "v4b8_%%u", 0, %d)),\n Int8Regs, 4, ".v4.u8">;\n' % (num_regs-1))
|
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 60 v4i8 = 14, // 4 x i8 enumerator in enum:llvm::MVT::SimpleValueType
237 case v4i8 :
277 case v4i8:
311 case v4i8:
398 if (NumElements == 4) return MVT::v4i8;
|
| ValueTypes.td | 37 def v4i8 : ValueType<32 , 14>; // 4 x i8 vector value
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 72 case MVT::v4i8: return "MVT::v4i8";
|
| /external/llvm/include/llvm/ |
| IntrinsicsMips.td | 17 def mips_v4q7_ty: LLVMType<v4i8>;
|
| Intrinsics.td | 125 def llvm_v4i8_ty : LLVMType<v4i8>; // 4 x i8
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 559 // It is legal to extload from v4i8 to v4i16 or v4i32.
560 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
[all...] |
| ARMInstrNEON.td | [all...] |
