1 /* 2 * This file was generated automatically by gen-mterp.py for 'mips'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7 /* File: mips/header.S */ 8 #include "../common/asm-constants.h" 9 #include "../common/mips-defines.h" 10 #include <asm/regdef.h> 11 #include <asm/fpregdef.h> 12 13 #ifdef __mips_hard_float 14 #define HARD_FLOAT 15 #else 16 #define SOFT_FLOAT 17 #endif 18 19 #if (__mips==32) && (__mips_isa_rev>=2) 20 #define MIPS32R2 21 #endif 22 23 /* MIPS definitions and declarations 24 25 reg nick purpose 26 s0 rPC interpreted program counter, used for fetching instructions 27 s1 rFP interpreted frame pointer, used for accessing locals and args 28 s2 rSELF self (Thread) pointer 29 s3 rIBASE interpreted instruction base pointer, used for computed goto 30 s4 rINST first 16-bit code unit of current instruction 31 */ 32 33 34 /* single-purpose registers, given names for clarity */ 35 #define rPC s0 36 #define rFP s1 37 #define rSELF s2 38 #define rIBASE s3 39 #define rINST s4 40 #define rOBJ s5 41 #define rBIX s6 42 #define rTEMP s7 43 44 /* The long arguments sent to function calls in Big-endian mode should be register 45 swapped when sent to functions in little endian mode. In other words long variable 46 sent as a0(MSW), a1(LSW) for a function call in LE mode should be sent as a1, a0 in 47 Big Endian mode */ 48 49 #ifdef HAVE_LITTLE_ENDIAN 50 #define rARG0 a0 51 #define rARG1 a1 52 #define rARG2 a2 53 #define rARG3 a3 54 #define rRESULT0 v0 55 #define rRESULT1 v1 56 #else 57 #define rARG0 a1 58 #define rARG1 a0 59 #define rARG2 a3 60 #define rARG3 a2 61 #define rRESULT0 v1 62 #define rRESULT1 v0 63 #endif 64 65 66 /* save/restore the PC and/or FP from the glue struct */ 67 #define LOAD_PC_FROM_SELF() lw rPC, offThread_pc(rSELF) 68 #define SAVE_PC_TO_SELF() sw rPC, offThread_pc(rSELF) 69 #define LOAD_FP_FROM_SELF() lw rFP, offThread_curFrame(rSELF) 70 #define SAVE_FP_TO_SELF() sw rFP, offThread_curFrame(rSELF) 71 #define LOAD_PC_FP_FROM_SELF() \ 72 LOAD_PC_FROM_SELF(); \ 73 LOAD_FP_FROM_SELF() 74 #define SAVE_PC_FP_TO_SELF() \ 75 SAVE_PC_TO_SELF(); \ 76 SAVE_FP_TO_SELF() 77 78 #define EXPORT_PC() \ 79 sw rPC, (offStackSaveArea_currentPc - sizeofStackSaveArea)(rFP) 80 81 #define SAVEAREA_FROM_FP(rd, _fpreg) \ 82 subu rd, _fpreg, sizeofStackSaveArea 83 84 #define FETCH_INST() lhu rINST, (rPC) 85 86 #define FETCH_ADVANCE_INST(_count) lhu rINST, ((_count)*2)(rPC); \ 87 addu rPC, rPC, ((_count) * 2) 88 89 #define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 90 lhu _dreg, ((_count)*2)(_sreg) ; \ 91 addu _sreg, _sreg, (_count)*2 92 93 #define FETCH_ADVANCE_INST_RB(rd) addu rPC, rPC, rd; \ 94 lhu rINST, (rPC) 95 96 #define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC) 97 #define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC) 98 99 #ifdef HAVE_LITTLE_ENDIAN 100 101 #define FETCH_B(rd, _count) lbu rd, ((_count) * 2)(rPC) 102 #define FETCH_C(rd, _count) lbu rd, ((_count) * 2 + 1)(rPC) 103 104 #else 105 106 #define FETCH_B(rd, _count) lbu rd, ((_count) * 2 + 1)(rPC) 107 #define FETCH_C(rd, _count) lbu rd, ((_count) * 2)(rPC) 108 109 #endif 110 111 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF 112 113 /* 114 * Put the prefetched instruction's opcode field into the specified register. 115 */ 116 117 #define GET_PREFETCHED_OPCODE(dreg, sreg) andi dreg, sreg, 255 118 119 #define GOTO_OPCODE(rd) sll rd, rd, 7; \ 120 addu rd, rIBASE, rd; \ 121 jr rd 122 123 #define GOTO_OPCODE_BASE(_base, rd) sll rd, rd, 7; \ 124 addu rd, _base, rd; \ 125 jr rd 126 127 #define GET_VREG(rd, rix) LOAD_eas2(rd, rFP, rix) 128 129 #define GET_VREG_F(rd, rix) EAS2(AT, rFP, rix); \ 130 .set noat; l.s rd, (AT); .set at 131 132 #define SET_VREG(rd, rix) STORE_eas2(rd, rFP, rix) 133 134 #define SET_VREG_GOTO(rd, rix, dst) .set noreorder; \ 135 sll dst, dst, 7; \ 136 addu dst, rIBASE, dst; \ 137 sll t8, rix, 2; \ 138 addu t8, t8, rFP; \ 139 jr dst; \ 140 sw rd, 0(t8); \ 141 .set reorder 142 143 #define SET_VREG_F(rd, rix) EAS2(AT, rFP, rix); \ 144 .set noat; s.s rd, (AT); .set at 145 146 147 #define GET_OPA(rd) srl rd, rINST, 8 148 #ifndef MIPS32R2 149 #define GET_OPA4(rd) GET_OPA(rd); and rd, 0xf 150 #else 151 #define GET_OPA4(rd) ext rd, rINST, 8, 4 152 #endif 153 #define GET_OPB(rd) srl rd, rINST, 12 154 155 #define LOAD_rSELF_OFF(rd, off) lw rd, offThread_##off## (rSELF) 156 157 #define LOAD_rSELF_method(rd) LOAD_rSELF_OFF(rd, method) 158 #define LOAD_rSELF_methodClassDex(rd) LOAD_rSELF_OFF(rd, methodClassDex) 159 #define LOAD_rSELF_interpStackEnd(rd) LOAD_rSELF_OFF(rd, interpStackEnd) 160 #define LOAD_rSELF_retval(rd) LOAD_rSELF_OFF(rd, retval) 161 #define LOAD_rSELF_pActiveProfilers(rd) LOAD_rSELF_OFF(rd, pActiveProfilers) 162 #define LOAD_rSELF_bailPtr(rd) LOAD_rSELF_OFF(rd, bailPtr) 163 #define LOAD_rSELF_SelfSuspendCount(rd) LOAD_rSELF_OFF(rd, SelfSuspendCount) 164 165 166 /* 167 * Form an Effective Address rd = rbase + roff<<n; 168 * Uses reg AT 169 */ 170 #define EASN(rd, rbase, roff, rshift) .set noat; \ 171 sll AT, roff, rshift; \ 172 addu rd, rbase, AT; \ 173 .set at 174 175 #define EAS1(rd, rbase, roff) EASN(rd, rbase, roff, 1) 176 #define EAS2(rd, rbase, roff) EASN(rd, rbase, roff, 2) 177 #define EAS3(rd, rbase, roff) EASN(rd, rbase, roff, 3) 178 #define EAS4(rd, rbase, roff) EASN(rd, rbase, roff, 4) 179 180 /* 181 * Form an Effective Shift Right rd = rbase + roff>>n; 182 * Uses reg AT 183 */ 184 #define ESRN(rd, rbase, roff, rshift) .set noat; \ 185 srl AT, roff, rshift; \ 186 addu rd, rbase, AT; \ 187 .set at 188 189 #define LOAD_eas2(rd, rbase, roff) EAS2(AT, rbase, roff); \ 190 .set noat; lw rd, 0(AT); .set at 191 192 #define STORE_eas2(rd, rbase, roff) EAS2(AT, rbase, roff); \ 193 .set noat; sw rd, 0(AT); .set at 194 195 #define LOAD_RB_OFF(rd, rbase, off) lw rd, off(rbase) 196 #define LOADu2_RB_OFF(rd, rbase, off) lhu rd, off(rbase) 197 #define STORE_RB_OFF(rd, rbase, off) sw rd, off(rbase) 198 199 #ifdef HAVE_LITTLE_ENDIAN 200 201 #define STORE64_off(rlo, rhi, rbase, off) sw rlo, off(rbase); \ 202 sw rhi, (off+4)(rbase) 203 #define LOAD64_off(rlo, rhi, rbase, off) lw rlo, off(rbase); \ 204 lw rhi, (off+4)(rbase) 205 206 #define vSTORE64_off(rlo, rhi, rbase, off) sw rlo, off(rbase); \ 207 sw rhi, (off+4)(rbase) 208 #define vLOAD64_off(rlo, rhi, rbase, off) lw rlo, off(rbase); \ 209 lw rhi, (off+4)(rbase) 210 211 #define STORE64_off_F(rlo, rhi, rbase, off) s.s rlo, off(rbase); \ 212 s.s rhi, (off+4)(rbase) 213 #define LOAD64_off_F(rlo, rhi, rbase, off) l.s rlo, off(rbase); \ 214 l.s rhi, (off+4)(rbase) 215 #else 216 217 #define STORE64_off(rlo, rhi, rbase, off) sw rlo, (off+4)(rbase); \ 218 sw rhi, (off)(rbase) 219 #define LOAD64_off(rlo, rhi, rbase, off) lw rlo, (off+4)(rbase); \ 220 lw rhi, (off)(rbase) 221 #define vSTORE64_off(rlo, rhi, rbase, off) sw rlo, (off+4)(rbase); \ 222 sw rhi, (off)(rbase) 223 #define vLOAD64_off(rlo, rhi, rbase, off) lw rlo, (off+4)(rbase); \ 224 lw rhi, (off)(rbase) 225 #define STORE64_off_F(rlo, rhi, rbase, off) s.s rlo, (off+4)(rbase); \ 226 s.s rhi, (off)(rbase) 227 #define LOAD64_off_F(rlo, rhi, rbase, off) l.s rlo, (off+4)(rbase); \ 228 l.s rhi, (off)(rbase) 229 #endif 230 231 #define STORE64(rlo, rhi, rbase) STORE64_off(rlo, rhi, rbase, 0) 232 #define LOAD64(rlo, rhi, rbase) LOAD64_off(rlo, rhi, rbase, 0) 233 234 #define vSTORE64(rlo, rhi, rbase) vSTORE64_off(rlo, rhi, rbase, 0) 235 #define vLOAD64(rlo, rhi, rbase) vLOAD64_off(rlo, rhi, rbase, 0) 236 237 #define STORE64_F(rlo, rhi, rbase) STORE64_off_F(rlo, rhi, rbase, 0) 238 #define LOAD64_F(rlo, rhi, rbase) LOAD64_off_F(rlo, rhi, rbase, 0) 239 240 #define STORE64_lo(rd, rbase) sw rd, 0(rbase) 241 #define STORE64_hi(rd, rbase) sw rd, 4(rbase) 242 243 244 #define LOAD_offThread_exception(rd, rbase) LOAD_RB_OFF(rd, rbase, offThread_exception) 245 #define LOAD_base_offArrayObject_length(rd, rbase) LOAD_RB_OFF(rd, rbase, offArrayObject_length) 246 #define LOAD_base_offClassObject_accessFlags(rd, rbase) LOAD_RB_OFF(rd, rbase, offClassObject_accessFlags) 247 #define LOAD_base_offClassObject_descriptor(rd, rbase) LOAD_RB_OFF(rd, rbase, offClassObject_descriptor) 248 #define LOAD_base_offClassObject_super(rd, rbase) LOAD_RB_OFF(rd, rbase, offClassObject_super) 249 250 #define LOAD_base_offClassObject_vtable(rd, rbase) LOAD_RB_OFF(rd, rbase, offClassObject_vtable) 251 #define LOAD_base_offClassObject_vtableCount(rd, rbase) LOAD_RB_OFF(rd, rbase, offClassObject_vtableCount) 252 #define LOAD_base_offDvmDex_pResClasses(rd, rbase) LOAD_RB_OFF(rd, rbase, offDvmDex_pResClasses) 253 #define LOAD_base_offDvmDex_pResFields(rd, rbase) LOAD_RB_OFF(rd, rbase, offDvmDex_pResFields) 254 255 #define LOAD_base_offDvmDex_pResMethods(rd, rbase) LOAD_RB_OFF(rd, rbase, offDvmDex_pResMethods) 256 #define LOAD_base_offDvmDex_pResStrings(rd, rbase) LOAD_RB_OFF(rd, rbase, offDvmDex_pResStrings) 257 #define LOAD_base_offInstField_byteOffset(rd, rbase) LOAD_RB_OFF(rd, rbase, offInstField_byteOffset) 258 #define LOAD_base_offStaticField_value(rd, rbase) LOAD_RB_OFF(rd, rbase, offStaticField_value) 259 #define LOAD_base_offMethod_clazz(rd, rbase) LOAD_RB_OFF(rd, rbase, offMethod_clazz) 260 261 #define LOAD_base_offMethod_name(rd, rbase) LOAD_RB_OFF(rd, rbase, offMethod_name) 262 #define LOAD_base_offObject_clazz(rd, rbase) LOAD_RB_OFF(rd, rbase, offObject_clazz) 263 264 #define LOADu2_offMethod_methodIndex(rd, rbase) LOADu2_RB_OFF(rd, rbase, offMethod_methodIndex) 265 266 267 #define STORE_offThread_exception(rd, rbase) STORE_RB_OFF(rd, rbase, offThread_exception) 268 269 270 #define STACK_STORE(rd, off) sw rd, off(sp) 271 #define STACK_LOAD(rd, off) lw rd, off(sp) 272 #define CREATE_STACK(n) subu sp, sp, n 273 #define DELETE_STACK(n) addu sp, sp, n 274 275 #define SAVE_RA(offset) STACK_STORE(ra, offset) 276 #define LOAD_RA(offset) STACK_LOAD(ra, offset) 277 278 #define LOAD_ADDR(dest, addr) la dest, addr 279 #define LOAD_IMM(dest, imm) li dest, imm 280 #define MOVE_REG(dest, src) move dest, src 281 #define RETURN jr ra 282 #define STACK_SIZE 128 283 284 #define STACK_OFFSET_ARG04 16 285 #define STACK_OFFSET_ARG05 20 286 #define STACK_OFFSET_ARG06 24 287 #define STACK_OFFSET_ARG07 28 288 #define STACK_OFFSET_SCR 32 289 #define STACK_OFFSET_SCRMX 80 290 #define STACK_OFFSET_GP 84 291 #define STACK_OFFSET_rFP 112 292 293 #define JAL(n) jal n 294 #define BAL(n) bal n 295 296 #define STACK_STORE_RA() CREATE_STACK(STACK_SIZE); \ 297 STACK_STORE(gp, STACK_OFFSET_GP); \ 298 STACK_STORE(ra, 124) 299 300 #define STACK_STORE_S0() STACK_STORE_RA(); \ 301 STACK_STORE(s0, 116) 302 303 #define STACK_STORE_S0S1() STACK_STORE_S0(); \ 304 STACK_STORE(s1, STACK_OFFSET_rFP) 305 306 #define STACK_LOAD_RA() STACK_LOAD(ra, 124); \ 307 STACK_LOAD(gp, STACK_OFFSET_GP); \ 308 DELETE_STACK(STACK_SIZE) 309 310 #define STACK_LOAD_S0() STACK_LOAD(s0, 116); \ 311 STACK_LOAD_RA() 312 313 #define STACK_LOAD_S0S1() STACK_LOAD(s1, STACK_OFFSET_rFP); \ 314 STACK_LOAD_S0() 315 316 #define STACK_STORE_FULL() CREATE_STACK(STACK_SIZE); \ 317 STACK_STORE(ra, 124); \ 318 STACK_STORE(fp, 120); \ 319 STACK_STORE(s0, 116); \ 320 STACK_STORE(s1, STACK_OFFSET_rFP); \ 321 STACK_STORE(s2, 108); \ 322 STACK_STORE(s3, 104); \ 323 STACK_STORE(s4, 100); \ 324 STACK_STORE(s5, 96); \ 325 STACK_STORE(s6, 92); \ 326 STACK_STORE(s7, 88); 327 328 #define STACK_LOAD_FULL() STACK_LOAD(gp, STACK_OFFSET_GP); \ 329 STACK_LOAD(s7, 88); \ 330 STACK_LOAD(s6, 92); \ 331 STACK_LOAD(s5, 96); \ 332 STACK_LOAD(s4, 100); \ 333 STACK_LOAD(s3, 104); \ 334 STACK_LOAD(s2, 108); \ 335 STACK_LOAD(s1, STACK_OFFSET_rFP); \ 336 STACK_LOAD(s0, 116); \ 337 STACK_LOAD(fp, 120); \ 338 STACK_LOAD(ra, 124); \ 339 DELETE_STACK(STACK_SIZE) 340 341 /* 342 * first 8 words are reserved for function calls 343 * Maximum offset is STACK_OFFSET_SCRMX-STACK_OFFSET_SCR 344 */ 345 #define SCRATCH_STORE(r,off) \ 346 STACK_STORE(r, STACK_OFFSET_SCR+off); 347 #define SCRATCH_LOAD(r,off) \ 348 STACK_LOAD(r, STACK_OFFSET_SCR+off); 349 350 #if defined(WITH_JIT) 351 #include "../common/jit-config.h" 352 #endif 353 354 /* File: mips/platform.S */ 355 /* 356 * =========================================================================== 357 * CPU-version-specific defines 358 * =========================================================================== 359 */ 360 361 #if !defined(ANDROID_SMP) 362 # error "Must define ANDROID_SMP" 363 #endif 364 365 /* 366 * Macro for data memory barrier. 367 */ 368 .macro SMP_DMB 369 #if ANDROID_SMP != 0 370 sync 371 #else 372 /* not SMP */ 373 #endif 374 .endm 375 376 /* 377 * Macro for data memory barrier (store/store variant). 378 */ 379 .macro SMP_DMB_ST 380 #if ANDROID_SMP != 0 381 // FIXME: Is this really needed? 382 sync 383 #else 384 /* not SMP */ 385 #endif 386 .endm 387 388 /* File: mips/entry.S */ 389 390 /* 391 * Copyright (C) 2008 The Android Open Source Project 392 * 393 * Licensed under the Apache License, Version 2.0 (the "License"); 394 * you may not use this file except in compliance with the License. 395 * You may obtain a copy of the License at 396 * 397 * http://www.apache.org/licenses/LICENSE-2.0 398 * 399 * Unless required by applicable law or agreed to in writing, software 400 * distributed under the License is distributed on an "AS IS" BASIS, 401 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 402 * See the License for the specific language governing permissions and 403 * limitations under the License. 404 */ 405 /* 406 * Interpreter entry point. 407 */ 408 409 #define ASSIST_DEBUGGER 1 410 411 .text 412 .align 2 413 .global dvmMterpStdRun 414 .ent dvmMterpStdRun 415 .frame sp, STACK_SIZE, ra 416 /* 417 * On entry: 418 * r0 Thread* self 419 * 420 * The return comes via a call to dvmMterpStdBail(). 421 */ 422 423 dvmMterpStdRun: 424 .set noreorder 425 .cpload t9 426 .set reorder 427 /* Save to the stack. Frame size = STACK_SIZE */ 428 STACK_STORE_FULL() 429 /* This directive will make sure all subsequent jal restore gp at a known offset */ 430 .cprestore STACK_OFFSET_GP 431 432 addu fp, sp, STACK_SIZE # Move Frame Pointer to the base of frame 433 /* save stack pointer, add magic word for debuggerd */ 434 sw sp, offThread_bailPtr(a0) # Save SP 435 436 /* set up "named" registers, figure out entry point */ 437 move rSELF, a0 # set rSELF 438 LOAD_PC_FROM_SELF() 439 LOAD_FP_FROM_SELF() 440 lw rIBASE, offThread_curHandlerTable(rSELF) 441 442 #if defined(WITH_JIT) 443 .LentryInstr: 444 /* Entry is always a possible trace start */ 445 lw a0, offThread_pJitProfTable(rSELF) 446 FETCH_INST() # load rINST from rPC 447 sw zero, offThread_inJitCodeCache(rSELF) 448 #if !defined(WITH_SELF_VERIFICATION) 449 bnez a0, common_updateProfile # profiling is enabled 450 #else 451 lw a2, offThread_shadowSpace(rSELF) # to find out the jit exit state 452 beqz a0, 1f # profiling is disabled 453 lw a3, offShadowSpace_jitExitState(a2) # jit exit state 454 li t0, kSVSTraceSelect 455 bne a3, t0, 2f 456 li a2, kJitTSelectRequestHot # ask for trace selection 457 b common_selectTrace # go build the trace 458 2: 459 li a4, kSVSNoProfile 460 beq a3, a4, 1f # don't profile the next instruction? 461 b common_updateProfile # collect profiles 462 #endif 463 1: 464 GET_INST_OPCODE(t0) # extract opcode from rINST 465 GOTO_OPCODE(t0) # jump to next instruction 466 #else 467 /* start executing the instruction at rPC */ 468 FETCH_INST() # load rINST from rPC 469 GET_INST_OPCODE(t0) # extract opcode from rINST 470 GOTO_OPCODE(t0) # jump to next instruction 471 #endif 472 473 .Lbad_arg: 474 la a0, .LstrBadEntryPoint 475 #a1 holds value of entryPoint 476 JAL(printf) 477 JAL(dvmAbort) 478 479 .end dvmMterpStdRun 480 481 .global dvmMterpStdBail 482 .ent dvmMterpStdBail 483 484 /* Restore the stack pointer and all the registers stored at sp from the save 485 * point established on entry. Return to whoever called dvmMterpStdRun. 486 * 487 * On entry: 488 * a0 Thread* self 489 */ 490 dvmMterpStdBail: 491 lw sp, offThread_bailPtr(a0) # Restore sp 492 STACK_LOAD_FULL() 493 jr ra 494 495 .end dvmMterpStdBail 496 497 498 .global dvmAsmInstructionStart 499 .type dvmAsmInstructionStart, %function 500 dvmAsmInstructionStart = .L_OP_NOP 501 .text 502 503 /* ------------------------------ */ 504 .balign 128 505 .L_OP_NOP: /* 0x00 */ 506 /* File: mips/OP_NOP.S */ 507 FETCH_ADVANCE_INST(1) # advance to next instr, load rINST 508 GET_INST_OPCODE(t0) 509 GOTO_OPCODE(t0) # execute it 510 511 #ifdef ASSIST_DEBUGGER 512 /* insert fake function header to help gdb find the stack frame */ 513 .type dalvik_inst, @function 514 dalvik_inst: 515 .ent dalvik_inst 516 .end dalvik_inst 517 #endif 518 519 520 /* ------------------------------ */ 521 .balign 128 522 .L_OP_MOVE: /* 0x01 */ 523 /* File: mips/OP_MOVE.S */ 524 /* for move, move-object, long-to-int */ 525 /* op vA, vB */ 526 GET_OPB(a1) # a1 <- B from 15:12 527 GET_OPA4(a0) # a0 <- A from 11:8 528 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 529 GET_VREG(a2, a1) # a2 <- fp[B] 530 GET_INST_OPCODE(t0) # t0 <- opcode from rINST 531 SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 532 533 534 /* ------------------------------ */ 535 .balign 128 536 .L_OP_MOVE_FROM16: /* 0x02 */ 537 /* File: mips/OP_MOVE_FROM16.S */ 538 /* for: move/from16, move-object/from16 */ 539 /* op vAA, vBBBB */ 540 FETCH(a1, 1) # a1 <- BBBB 541 GET_OPA(a0) # a0 <- AA 542 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 543 GET_VREG(a2, a1) # a2 <- fp[BBBB] 544 GET_INST_OPCODE(t0) # extract opcode from rINST 545 SET_VREG_GOTO(a2, a0, t0) # fp[AA] <- a2 546 547 548 /* ------------------------------ */ 549 .balign 128 550 .L_OP_MOVE_16: /* 0x03 */ 551 /* File: mips/OP_MOVE_16.S */ 552 /* for: move/16, move-object/16 */ 553 /* op vAAAA, vBBBB */ 554 FETCH(a1, 2) # a1 <- BBBB 555 FETCH(a0, 1) # a0 <- AAAA 556 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 557 GET_VREG(a2, a1) # a2 <- fp[BBBB] 558 GET_INST_OPCODE(t0) # extract opcode from rINST 559 SET_VREG_GOTO(a2, a0, t0) # fp[AAAA] <- a2 and jump 560 561 562 /* ------------------------------ */ 563 .balign 128 564 .L_OP_MOVE_WIDE: /* 0x04 */ 565 /* File: mips/OP_MOVE_WIDE.S */ 566 /* move-wide vA, vB */ 567 /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ 568 GET_OPA4(a2) # a2 <- A(+) 569 GET_OPB(a3) # a3 <- B 570 EAS2(a3, rFP, a3) # a3 <- &fp[B] 571 EAS2(a2, rFP, a2) # a2 <- &fp[A] 572 LOAD64(a0, a1, a3) # a0/a1 <- fp[B] 573 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 574 GET_INST_OPCODE(t0) # extract opcode from rINST 575 STORE64(a0, a1, a2) # fp[A] <- a0/a1 576 GOTO_OPCODE(t0) # jump to next instruction 577 578 579 /* ------------------------------ */ 580 .balign 128 581 .L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 582 /* File: mips/OP_MOVE_WIDE_FROM16.S */ 583 /* move-wide/from16 vAA, vBBBB */ 584 /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ 585 FETCH(a3, 1) # a3 <- BBBB 586 GET_OPA(a2) # a2 <- AA 587 EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] 588 EAS2(a2, rFP, a2) # a2 <- &fp[AA] 589 LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] 590 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 591 GET_INST_OPCODE(t0) # extract opcode from rINST 592 STORE64(a0, a1, a2) # fp[AA] <- a0/a1 593 GOTO_OPCODE(t0) # jump to next instruction 594 595 596 /* ------------------------------ */ 597 .balign 128 598 .L_OP_MOVE_WIDE_16: /* 0x06 */ 599 /* File: mips/OP_MOVE_WIDE_16.S */ 600 /* move-wide/16 vAAAA, vBBBB */ 601 /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ 602 FETCH(a3, 2) # a3 <- BBBB 603 FETCH(a2, 1) # a2 <- AAAA 604 EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] 605 EAS2(a2, rFP, a2) # a2 <- &fp[AAAA] 606 LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] 607 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 608 GET_INST_OPCODE(t0) # extract opcode from rINST 609 STORE64(a0, a1, a2) # fp[AAAA] <- a0/a1 610 GOTO_OPCODE(t0) # jump to next instruction 611 612 613 /* ------------------------------ */ 614 .balign 128 615 .L_OP_MOVE_OBJECT: /* 0x07 */ 616 /* File: mips/OP_MOVE_OBJECT.S */ 617 /* File: mips/OP_MOVE.S */ 618 /* for move, move-object, long-to-int */ 619 /* op vA, vB */ 620 GET_OPB(a1) # a1 <- B from 15:12 621 GET_OPA4(a0) # a0 <- A from 11:8 622 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 623 GET_VREG(a2, a1) # a2 <- fp[B] 624 GET_INST_OPCODE(t0) # t0 <- opcode from rINST 625 SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 626 627 628 629 /* ------------------------------ */ 630 .balign 128 631 .L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 632 /* File: mips/OP_MOVE_OBJECT_FROM16.S */ 633 /* File: mips/OP_MOVE_FROM16.S */ 634 /* for: move/from16, move-object/from16 */ 635 /* op vAA, vBBBB */ 636 FETCH(a1, 1) # a1 <- BBBB 637 GET_OPA(a0) # a0 <- AA 638 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 639 GET_VREG(a2, a1) # a2 <- fp[BBBB] 640 GET_INST_OPCODE(t0) # extract opcode from rINST 641 SET_VREG_GOTO(a2, a0, t0) # fp[AA] <- a2 642 643 644 645 /* ------------------------------ */ 646 .balign 128 647 .L_OP_MOVE_OBJECT_16: /* 0x09 */ 648 /* File: mips/OP_MOVE_OBJECT_16.S */ 649 /* File: mips/OP_MOVE_16.S */ 650 /* for: move/16, move-object/16 */ 651 /* op vAAAA, vBBBB */ 652 FETCH(a1, 2) # a1 <- BBBB 653 FETCH(a0, 1) # a0 <- AAAA 654 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 655 GET_VREG(a2, a1) # a2 <- fp[BBBB] 656 GET_INST_OPCODE(t0) # extract opcode from rINST 657 SET_VREG_GOTO(a2, a0, t0) # fp[AAAA] <- a2 and jump 658 659 660 661 /* ------------------------------ */ 662 .balign 128 663 .L_OP_MOVE_RESULT: /* 0x0a */ 664 /* File: mips/OP_MOVE_RESULT.S */ 665 /* for: move-result, move-result-object */ 666 /* op vAA */ 667 GET_OPA(a2) # a2 <- AA 668 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 669 LOAD_rSELF_retval(a0) # a0 <- self->retval.i 670 GET_INST_OPCODE(t0) # extract opcode from rINST 671 SET_VREG_GOTO(a0, a2, t0) # fp[AA] <- a0 672 673 674 /* ------------------------------ */ 675 .balign 128 676 .L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 677 /* File: mips/OP_MOVE_RESULT_WIDE.S */ 678 /* move-result-wide vAA */ 679 GET_OPA(a2) # a2 <- AA 680 addu a3, rSELF, offThread_retval # a3 <- &self->retval 681 EAS2(a2, rFP, a2) # a2 <- &fp[AA] 682 LOAD64(a0, a1, a3) # a0/a1 <- retval.j 683 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 684 GET_INST_OPCODE(t0) # extract opcode from rINST 685 STORE64(a0, a1, a2) # fp[AA] <- a0/a1 686 GOTO_OPCODE(t0) # jump to next instruction 687 688 689 /* ------------------------------ */ 690 .balign 128 691 .L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 692 /* File: mips/OP_MOVE_RESULT_OBJECT.S */ 693 /* File: mips/OP_MOVE_RESULT.S */ 694 /* for: move-result, move-result-object */ 695 /* op vAA */ 696 GET_OPA(a2) # a2 <- AA 697 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 698 LOAD_rSELF_retval(a0) # a0 <- self->retval.i 699 GET_INST_OPCODE(t0) # extract opcode from rINST 700 SET_VREG_GOTO(a0, a2, t0) # fp[AA] <- a0 701 702 703 704 /* ------------------------------ */ 705 .balign 128 706 .L_OP_MOVE_EXCEPTION: /* 0x0d */ 707 /* File: mips/OP_MOVE_EXCEPTION.S */ 708 /* move-exception vAA */ 709 GET_OPA(a2) # a2 <- AA 710 LOAD_offThread_exception(a3, rSELF) # a3 <- dvmGetException bypass 711 li a1, 0 # a1 <- 0 712 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 713 SET_VREG(a3, a2) # fp[AA] <- exception obj 714 GET_INST_OPCODE(t0) # extract opcode from rINST 715 STORE_offThread_exception(a1, rSELF) # dvmClearException bypass 716 GOTO_OPCODE(t0) # jump to next instruction 717 718 719 /* ------------------------------ */ 720 .balign 128 721 .L_OP_RETURN_VOID: /* 0x0e */ 722 /* File: mips/OP_RETURN_VOID.S */ 723 b common_returnFromMethod 724 725 726 /* ------------------------------ */ 727 .balign 128 728 .L_OP_RETURN: /* 0x0f */ 729 /* File: mips/OP_RETURN.S */ 730 /* 731 * Return a 32-bit value. Copies the return value into the "thread" 732 * structure, then jumps to the return handler. 733 * 734 * for: return, return-object 735 */ 736 /* op vAA */ 737 GET_OPA(a2) # a2 <- AA 738 GET_VREG(a0, a2) # a0 <- vAA 739 sw a0, offThread_retval(rSELF) # retval.i <- vAA 740 b common_returnFromMethod 741 742 743 /* ------------------------------ */ 744 .balign 128 745 .L_OP_RETURN_WIDE: /* 0x10 */ 746 /* File: mips/OP_RETURN_WIDE.S */ 747 /* 748 * Return a 64-bit value. Copies the return value into the "thread" 749 * structure, then jumps to the return handler. 750 */ 751 /* return-wide vAA */ 752 GET_OPA(a2) # a2 <- AA 753 EAS2(a2, rFP, a2) # a2 <- &fp[AA] 754 addu a3, rSELF, offThread_retval # a3 <- &self->retval 755 LOAD64(a0, a1, a2) # a0/a1 <- vAA/vAA+1 756 STORE64(a0, a1, a3) # retval <- a0/a1 757 b common_returnFromMethod 758 759 760 /* ------------------------------ */ 761 .balign 128 762 .L_OP_RETURN_OBJECT: /* 0x11 */ 763 /* File: mips/OP_RETURN_OBJECT.S */ 764 /* File: mips/OP_RETURN.S */ 765 /* 766 * Return a 32-bit value. Copies the return value into the "thread" 767 * structure, then jumps to the return handler. 768 * 769 * for: return, return-object 770 */ 771 /* op vAA */ 772 GET_OPA(a2) # a2 <- AA 773 GET_VREG(a0, a2) # a0 <- vAA 774 sw a0, offThread_retval(rSELF) # retval.i <- vAA 775 b common_returnFromMethod 776 777 778 779 /* ------------------------------ */ 780 .balign 128 781 .L_OP_CONST_4: /* 0x12 */ 782 /* File: mips/OP_CONST_4.S */ 783 # const/4 vA, /* +B */ 784 sll a1, rINST, 16 # a1 <- Bxxx0000 785 GET_OPA(a0) # a0 <- A+ 786 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 787 sra a1, a1, 28 # a1 <- sssssssB (sign-extended) 788 and a0, a0, 15 789 GET_INST_OPCODE(t0) # ip <- opcode from rINST 790 SET_VREG_GOTO(a1, a0, t0) # fp[A] <- a1 791 792 793 /* ------------------------------ */ 794 .balign 128 795 .L_OP_CONST_16: /* 0x13 */ 796 /* File: mips/OP_CONST_16.S */ 797 # const/16 vAA, /* +BBBB */ 798 FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) 799 GET_OPA(a3) # a3 <- AA 800 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 801 GET_INST_OPCODE(t0) # extract opcode from rINST 802 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 803 804 805 /* ------------------------------ */ 806 .balign 128 807 .L_OP_CONST: /* 0x14 */ 808 /* File: mips/OP_CONST.S */ 809 # const vAA, /* +BBBBbbbb */ 810 GET_OPA(a3) # a3 <- AA 811 FETCH(a0, 1) # a0 <- bbbb (low) 812 FETCH(a1, 2) # a1 <- BBBB (high) 813 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 814 sll a1, a1, 16 815 or a0, a1, a0 # a0 <- BBBBbbbb 816 GET_INST_OPCODE(t0) # extract opcode from rINST 817 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 818 819 820 /* ------------------------------ */ 821 .balign 128 822 .L_OP_CONST_HIGH16: /* 0x15 */ 823 /* File: mips/OP_CONST_HIGH16.S */ 824 # const/high16 vAA, /* +BBBB0000 */ 825 FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended) 826 GET_OPA(a3) # a3 <- AA 827 sll a0, a0, 16 # a0 <- BBBB0000 828 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 829 GET_INST_OPCODE(t0) # extract opcode from rINST 830 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 831 832 833 /* ------------------------------ */ 834 .balign 128 835 .L_OP_CONST_WIDE_16: /* 0x16 */ 836 /* File: mips/OP_CONST_WIDE_16.S */ 837 # const-wide/16 vAA, /* +BBBB */ 838 FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) 839 GET_OPA(a3) # a3 <- AA 840 sra a1, a0, 31 # a1 <- ssssssss 841 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 842 EAS2(a3, rFP, a3) # a3 <- &fp[AA] 843 GET_INST_OPCODE(t0) # extract opcode from rINST 844 STORE64(a0, a1, a3) # vAA <- a0/a1 845 GOTO_OPCODE(t0) # jump to next instruction 846 847 848 /* ------------------------------ */ 849 .balign 128 850 .L_OP_CONST_WIDE_32: /* 0x17 */ 851 /* File: mips/OP_CONST_WIDE_32.S */ 852 # const-wide/32 vAA, /* +BBBBbbbb */ 853 FETCH(a0, 1) # a0 <- 0000bbbb (low) 854 GET_OPA(a3) # a3 <- AA 855 FETCH_S(a2, 2) # a2 <- ssssBBBB (high) 856 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 857 sll a2, a2, 16 858 or a0, a0, a2 # a0 <- BBBBbbbb 859 EAS2(a3, rFP, a3) # a3 <- &fp[AA] 860 sra a1, a0, 31 # a1 <- ssssssss 861 GET_INST_OPCODE(t0) # extract opcode from rINST 862 STORE64(a0, a1, a3) # vAA <- a0/a1 863 GOTO_OPCODE(t0) # jump to next instruction 864 865 866 /* ------------------------------ */ 867 .balign 128 868 .L_OP_CONST_WIDE: /* 0x18 */ 869 /* File: mips/OP_CONST_WIDE.S */ 870 # const-wide vAA, /* +HHHHhhhhBBBBbbbb */ 871 FETCH(a0, 1) # a0 <- bbbb (low) 872 FETCH(a1, 2) # a1 <- BBBB (low middle) 873 FETCH(a2, 3) # a2 <- hhhh (high middle) 874 sll a1, 16 # 875 or a0, a1 # a0 <- BBBBbbbb (low word) 876 FETCH(a3, 4) # a3 <- HHHH (high) 877 GET_OPA(t1) # t1 <- AA 878 sll a3, 16 879 or a1, a3, a2 # a1 <- HHHHhhhh (high word) 880 FETCH_ADVANCE_INST(5) # advance rPC, load rINST 881 EAS2(t1, rFP, t1) # t1 <- &fp[AA] 882 GET_INST_OPCODE(t0) # extract opcode from rINST 883 STORE64(a0, a1, t1) # vAA <- a0/a1 884 GOTO_OPCODE(t0) # jump to next instruction 885 886 887 /* ------------------------------ */ 888 .balign 128 889 .L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 890 /* File: mips/OP_CONST_WIDE_HIGH16.S */ 891 # const-wide/high16 vAA, /* +BBBB000000000000 */ 892 FETCH(a1, 1) # a1 <- 0000BBBB (zero-extended) 893 GET_OPA(a3) # a3 <- AA 894 li a0, 0 # a0 <- 00000000 895 sll a1, 16 # a1 <- BBBB0000 896 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 897 EAS2(a3, rFP, a3) # a3 <- &fp[AA] 898 GET_INST_OPCODE(t0) # extract opcode from rINST 899 STORE64(a0, a1, a3) # vAA <- a0/a1 900 GOTO_OPCODE(t0) # jump to next instruction 901 902 903 /* ------------------------------ */ 904 .balign 128 905 .L_OP_CONST_STRING: /* 0x1a */ 906 /* File: mips/OP_CONST_STRING.S */ 907 # const/string vAA, String /* BBBB */ 908 FETCH(a1, 1) # a1 <- BBBB 909 LOAD_rSELF_methodClassDex(a2) # a2 <- self->methodClassDex 910 GET_OPA(rOBJ) # rOBJ <- AA 911 LOAD_base_offDvmDex_pResStrings(a2, a2) # a2 <- dvmDex->pResStrings 912 LOAD_eas2(v0, a2, a1) # v0 <- pResStrings[BBBB] 913 # not yet resolved? 914 bnez v0, .LOP_CONST_STRING_resolve 915 /* 916 * Continuation if the String has not yet been resolved. 917 * a1: BBBB (String ref) 918 * rOBJ: target register 919 */ 920 EXPORT_PC() 921 LOAD_rSELF_method(a0) # a0 <- self->method 922 LOAD_base_offMethod_clazz(a0, a0) # a0 <- method->clazz 923 JAL(dvmResolveString) # v0 <- String reference 924 # failed? 925 beqz v0, common_exceptionThrown # yup, handle the exception 926 927 .LOP_CONST_STRING_resolve: 928 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 929 GET_INST_OPCODE(t0) # extract opcode from rINST 930 SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0 931 932 933 934 935 936 937 /* ------------------------------ */ 938 .balign 128 939 .L_OP_CONST_STRING_JUMBO: /* 0x1b */ 940 /* File: mips/OP_CONST_STRING_JUMBO.S */ 941 # const/string vAA, String /* BBBBBBBB */ 942 FETCH(a0, 1) # a0 <- bbbb (low) 943 FETCH(a1, 2) # a1 <- BBBB (high) 944 LOAD_rSELF_methodClassDex(a2) # a2 <- self->methodClassDex 945 GET_OPA(rOBJ) # rOBJ <- AA 946 LOAD_base_offDvmDex_pResStrings(a2, a2) # a2 <- dvmDex->pResStrings 947 sll a1, a1, 16 948 or a1, a1, a0 # a1 <- BBBBbbbb 949 LOAD_eas2(v0, a2, a1) # v0 <- pResStrings[BBBB] 950 bnez v0, .LOP_CONST_STRING_JUMBO_resolve 951 952 /* 953 * Continuation if the String has not yet been resolved. 954 * a1: BBBBBBBB (String ref) 955 * rOBJ: target register 956 */ 957 EXPORT_PC() 958 LOAD_rSELF_method(a0) # a0 <- self->method 959 LOAD_base_offMethod_clazz(a0, a0) # a0 <- method->clazz 960 JAL(dvmResolveString) # v0 <- String reference 961 # failed? 962 beqz v0, common_exceptionThrown # yup, handle the exception 963 964 .LOP_CONST_STRING_JUMBO_resolve: 965 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 966 GET_INST_OPCODE(t1) # extract opcode from rINST 967 SET_VREG_GOTO(v0, rOBJ, t1) # vAA <- v0 968 969 970 /* ------------------------------ */ 971 .balign 128 972 .L_OP_CONST_CLASS: /* 0x1c */ 973 /* File: mips/OP_CONST_CLASS.S */ 974 # const/class vAA, Class /* BBBB */ 975 FETCH(a1, 1) # a1 <- BBBB 976 LOAD_rSELF_methodClassDex(a2) # a2 <- self->methodClassDex 977 GET_OPA(rOBJ) # rOBJ <- AA 978 LOAD_base_offDvmDex_pResClasses(a2, a2) # a2 <- dvmDex->pResClasses 979 LOAD_eas2(v0, a2, a1) # v0 <- pResClasses[BBBB] 980 981 bnez v0, .LOP_CONST_CLASS_resolve # v0!=0 => resolved-ok 982 /* 983 * Continuation if the Class has not yet been resolved. 984 * a1: BBBB (Class ref) 985 * rOBJ: target register 986 */ 987 EXPORT_PC() 988 LOAD_rSELF_method(a0) # a0 <- self->method 989 li a2, 1 # a2 <- true 990 LOAD_base_offMethod_clazz(a0, a0) # a0 <- method->clazz 991 JAL(dvmResolveClass) # v0 <- Class reference 992 # failed==0? 993 beqz v0, common_exceptionThrown # yup, handle the exception 994 995 .LOP_CONST_CLASS_resolve: 996 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 997 GET_INST_OPCODE(t0) # extract opcode from rINST 998 SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0 999 1000 1001 1002 /* ------------------------------ */ 1003 .balign 128 1004 .L_OP_MONITOR_ENTER: /* 0x1d */ 1005 /* File: mips/OP_MONITOR_ENTER.S */ 1006 /* 1007 * Synchronize on an object. 1008 */ 1009 /* monitor-enter vAA */ 1010 GET_OPA(a2) # a2 <- AA 1011 GET_VREG(a1, a2) # a1 <- vAA (object) 1012 move a0, rSELF # a0 <- self 1013 EXPORT_PC() # export PC so we can grab stack trace 1014 # null object? 1015 beqz a1, common_errNullObject # null object, throw an exception 1016 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1017 JAL(dvmLockObject) # call(self, obj) 1018 GET_INST_OPCODE(t0) # extract opcode from rINST 1019 GOTO_OPCODE(t0) # jump to next instruction 1020 1021 1022 /* ------------------------------ */ 1023 .balign 128 1024 .L_OP_MONITOR_EXIT: /* 0x1e */ 1025 /* File: mips/OP_MONITOR_EXIT.S */ 1026 /* 1027 * Unlock an object. 1028 * 1029 * Exceptions that occur when unlocking a monitor need to appear as 1030 * if they happened at the following instruction. See the Dalvik 1031 * instruction spec. 1032 */ 1033 /* monitor-exit vAA */ 1034 GET_OPA(a2) # a2 <- AA 1035 EXPORT_PC() # before fetch: export the PC 1036 GET_VREG(a1, a2) # a1 <- vAA (object) 1037 # null object? 1038 beqz a1, 1f 1039 move a0, rSELF # a0 <- self 1040 JAL(dvmUnlockObject) # v0 <- success for unlock(self, obj) 1041 # failed? 1042 FETCH_ADVANCE_INST(1) # before throw: advance rPC, load rINST 1043 beqz v0, common_exceptionThrown # yes, exception is pending 1044 GET_INST_OPCODE(t0) # extract opcode from rINST 1045 GOTO_OPCODE(t0) # jump to next instruction 1046 1: 1047 FETCH_ADVANCE_INST(1) # before throw: advance rPC, load rINST 1048 b common_errNullObject 1049 1050 /* ------------------------------ */ 1051 .balign 128 1052 .L_OP_CHECK_CAST: /* 0x1f */ 1053 /* File: mips/OP_CHECK_CAST.S */ 1054 /* 1055 * Check to see if a cast from one class to another is allowed. 1056 */ 1057 # check-cast vAA, class /* BBBB */ 1058 GET_OPA(a3) # a3 <- AA 1059 FETCH(a2, 1) # a2 <- BBBB 1060 GET_VREG(rOBJ, a3) # rOBJ <- object 1061 LOAD_rSELF_methodClassDex(a0) # a0 <- pDvmDex 1062 LOAD_base_offDvmDex_pResClasses(a0, a0) # a0 <- pDvmDex->pResClasses 1063 # is object null? 1064 beqz rOBJ, .LOP_CHECK_CAST_okay # null obj, cast always succeeds 1065 LOAD_eas2(a1, a0, a2) # a1 <- resolved class 1066 LOAD_base_offObject_clazz(a0, rOBJ) # a0 <- obj->clazz 1067 # have we resolved this before? 1068 beqz a1, .LOP_CHECK_CAST_resolve # not resolved, do it now 1069 .LOP_CHECK_CAST_resolved: 1070 # same class (trivial success)? 1071 bne a0, a1, .LOP_CHECK_CAST_fullcheck # no, do full check 1072 .LOP_CHECK_CAST_okay: 1073 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1074 GET_INST_OPCODE(t0) # extract opcode from rINST 1075 GOTO_OPCODE(t0) # jump to next instruction 1076 1077 /* 1078 * Trivial test failed, need to perform full check. This is common. 1079 * a0 holds obj->clazz 1080 * a1 holds class resolved from BBBB 1081 * rOBJ holds object 1082 */ 1083 .LOP_CHECK_CAST_fullcheck: 1084 move rBIX,a1 # avoid ClassObject getting clobbered 1085 JAL(dvmInstanceofNonTrivial) # v0 <- boolean result 1086 # failed? 1087 bnez v0, .LOP_CHECK_CAST_okay # no, success 1088 b .LOP_CHECK_CAST_castfailure 1089 1090 /* ------------------------------ */ 1091 .balign 128 1092 .L_OP_INSTANCE_OF: /* 0x20 */ 1093 /* File: mips/OP_INSTANCE_OF.S */ 1094 /* 1095 * Check to see if an object reference is an instance of a class. 1096 * 1097 * Most common situation is a non-null object, being compared against 1098 * an already-resolved class. 1099 */ 1100 # instance-of vA, vB, class /* CCCC */ 1101 GET_OPB(a3) # a3 <- B 1102 GET_OPA4(rOBJ) # rOBJ <- A+ 1103 GET_VREG(a0, a3) # a0 <- vB (object) 1104 LOAD_rSELF_methodClassDex(a2) # a2 <- pDvmDex 1105 # is object null? 1106 beqz a0, .LOP_INSTANCE_OF_store # null obj, not an instance, store a0 1107 FETCH(a3, 1) # a3 <- CCCC 1108 LOAD_base_offDvmDex_pResClasses(a2, a2) # a2 <- pDvmDex->pResClasses 1109 LOAD_eas2(a1, a2, a3) # a1 <- resolved class 1110 LOAD_base_offObject_clazz(a0, a0) # a0 <- obj->clazz 1111 # have we resolved this before? 1112 beqz a1, .LOP_INSTANCE_OF_resolve # not resolved, do it now 1113 .LOP_INSTANCE_OF_resolved: # a0=obj->clazz, a1=resolved class 1114 # same class (trivial success)? 1115 beq a0, a1, .LOP_INSTANCE_OF_trivial # yes, trivial finish 1116 b .LOP_INSTANCE_OF_fullcheck # no, do full check 1117 1118 /* 1119 * Trivial test succeeded, save and bail. 1120 * rOBJ holds A 1121 */ 1122 .LOP_INSTANCE_OF_trivial: 1123 li a0, 1 # indicate success 1124 # fall thru 1125 /* 1126 * a0 holds boolean result 1127 * rOBJ holds A 1128 */ 1129 .LOP_INSTANCE_OF_store: 1130 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1131 SET_VREG(a0, rOBJ) # vA <- a0 1132 GET_INST_OPCODE(t0) # extract opcode from rINST 1133 GOTO_OPCODE(t0) # jump to next instruction 1134 1135 1136 /* ------------------------------ */ 1137 .balign 128 1138 .L_OP_ARRAY_LENGTH: /* 0x21 */ 1139 /* File: mips/OP_ARRAY_LENGTH.S */ 1140 /* 1141 * Return the length of an array. 1142 */ 1143 GET_OPB(a1) # a1 <- B 1144 GET_OPA4(a2) # a2 <- A+ 1145 GET_VREG(a0, a1) # a0 <- vB (object ref) 1146 # is object null? 1147 beqz a0, common_errNullObject # yup, fail 1148 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1149 LOAD_base_offArrayObject_length(a3, a0) # a3 <- array length 1150 GET_INST_OPCODE(t0) # extract opcode from rINST 1151 SET_VREG_GOTO(a3, a2, t0) # vA <- length 1152 1153 1154 /* ------------------------------ */ 1155 .balign 128 1156 .L_OP_NEW_INSTANCE: /* 0x22 */ 1157 /* File: mips/OP_NEW_INSTANCE.S */ 1158 /* 1159 * Create a new instance of a class. 1160 */ 1161 # new-instance vAA, class /* BBBB */ 1162 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 1163 FETCH(a1, 1) # a1 <- BBBB 1164 LOAD_base_offDvmDex_pResClasses(a3, a3) # a3 <- pDvmDex->pResClasses 1165 LOAD_eas2(a0, a3, a1) # a0 <- resolved class 1166 #if defined(WITH_JIT) 1167 EAS2(rBIX, a3, a1) # rBIX <- &resolved_class 1168 #endif 1169 EXPORT_PC() # req'd for init, resolve, alloc 1170 # already resolved? 1171 beqz a0, .LOP_NEW_INSTANCE_resolve # no, resolve it now 1172 .LOP_NEW_INSTANCE_resolved: # a0=class 1173 lbu a1, offClassObject_status(a0) # a1 <- ClassStatus enum 1174 # has class been initialized? 1175 li t0, CLASS_INITIALIZED 1176 move rOBJ, a0 # save a0 1177 bne a1, t0, .LOP_NEW_INSTANCE_needinit # no, init class now 1178 1179 .LOP_NEW_INSTANCE_initialized: # a0=class 1180 LOAD_base_offClassObject_accessFlags(a3, a0) # a3 <- clazz->accessFlags 1181 li a1, ALLOC_DONT_TRACK # flags for alloc call 1182 # a0=class 1183 JAL(dvmAllocObject) # v0 <- new object 1184 GET_OPA(a3) # a3 <- AA 1185 #if defined(WITH_JIT) 1186 /* 1187 * The JIT needs the class to be fully resolved before it can 1188 * include this instruction in a trace. 1189 */ 1190 lhu a1, offThread_subMode(rSELF) 1191 beqz v0, common_exceptionThrown # yes, handle the exception 1192 and a1, kSubModeJitTraceBuild # under construction? 1193 bnez a1, .LOP_NEW_INSTANCE_jitCheck 1194 #else 1195 # failed? 1196 beqz v0, common_exceptionThrown # yes, handle the exception 1197 #endif 1198 b .LOP_NEW_INSTANCE_continue 1199 1200 1201 /* ------------------------------ */ 1202 .balign 128 1203 .L_OP_NEW_ARRAY: /* 0x23 */ 1204 /* File: mips/OP_NEW_ARRAY.S */ 1205 /* 1206 * Allocate an array of objects, specified with the array class 1207 * and a count. 1208 * 1209 * The verifier guarantees that this is an array class, so we don't 1210 * check for it here. 1211 */ 1212 /* new-array vA, vB, class@CCCC */ 1213 GET_OPB(a0) # a0 <- B 1214 FETCH(a2, 1) # a2 <- CCCC 1215 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 1216 GET_VREG(a1, a0) # a1 <- vB (array length) 1217 LOAD_base_offDvmDex_pResClasses(a3, a3) # a3 <- pDvmDex->pResClasses 1218 LOAD_eas2(a0, a3, a2) # a0 <- resolved class 1219 # check length 1220 bltz a1, common_errNegativeArraySize # negative length, bail - len in a1 1221 EXPORT_PC() # req'd for resolve, alloc 1222 # already resolved? 1223 beqz a0, .LOP_NEW_ARRAY_resolve 1224 1225 /* 1226 * Finish allocation. 1227 * 1228 * a0 holds class 1229 * a1 holds array length 1230 */ 1231 .LOP_NEW_ARRAY_finish: 1232 li a2, ALLOC_DONT_TRACK # don't track in local refs table 1233 JAL(dvmAllocArrayByClass) # v0 <- call(clazz, length, flags) 1234 GET_OPA4(a2) # a2 <- A+ 1235 # failed? 1236 beqz v0, common_exceptionThrown # yes, handle the exception 1237 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1238 GET_INST_OPCODE(t0) # extract opcode from rINST 1239 SET_VREG(v0, a2) # vA <- v0 1240 GOTO_OPCODE(t0) # jump to next instruction 1241 1242 /* ------------------------------ */ 1243 .balign 128 1244 .L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1245 /* File: mips/OP_FILLED_NEW_ARRAY.S */ 1246 /* 1247 * Create a new array with elements filled from registers. 1248 * 1249 * for: filled-new-array, filled-new-array/range 1250 */ 1251 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 1252 # op {vCCCC..v(CCCC+AA-1)}, type /* BBBB */ 1253 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 1254 FETCH(a1, 1) # a1 <- BBBB 1255 LOAD_base_offDvmDex_pResClasses(a3, a3) # a3 <- pDvmDex->pResClasses 1256 EXPORT_PC() # need for resolve and alloc 1257 LOAD_eas2(a0, a3, a1) # a0 <- resolved class 1258 GET_OPA(rOBJ) # rOBJ <- AA or BA 1259 # already resolved? 1260 bnez a0, .LOP_FILLED_NEW_ARRAY_continue # yes, continue on 1261 LOAD_rSELF_method(a3) # a3 <- self->method 1262 li a2, 0 # a2 <- false 1263 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 1264 JAL(dvmResolveClass) # v0 <- call(clazz, ref) 1265 move a0, v0 1266 # got null? 1267 beqz v0, common_exceptionThrown # yes, handle exception 1268 b .LOP_FILLED_NEW_ARRAY_continue 1269 1270 /* ------------------------------ */ 1271 .balign 128 1272 .L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1273 /* File: mips/OP_FILLED_NEW_ARRAY_RANGE.S */ 1274 /* File: mips/OP_FILLED_NEW_ARRAY.S */ 1275 /* 1276 * Create a new array with elements filled from registers. 1277 * 1278 * for: filled-new-array, filled-new-array/range 1279 */ 1280 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 1281 # op {vCCCC..v(CCCC+AA-1)}, type /* BBBB */ 1282 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 1283 FETCH(a1, 1) # a1 <- BBBB 1284 LOAD_base_offDvmDex_pResClasses(a3, a3) # a3 <- pDvmDex->pResClasses 1285 EXPORT_PC() # need for resolve and alloc 1286 LOAD_eas2(a0, a3, a1) # a0 <- resolved class 1287 GET_OPA(rOBJ) # rOBJ <- AA or BA 1288 # already resolved? 1289 bnez a0, .LOP_FILLED_NEW_ARRAY_RANGE_continue # yes, continue on 1290 LOAD_rSELF_method(a3) # a3 <- self->method 1291 li a2, 0 # a2 <- false 1292 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 1293 JAL(dvmResolveClass) # v0 <- call(clazz, ref) 1294 move a0, v0 1295 # got null? 1296 beqz v0, common_exceptionThrown # yes, handle exception 1297 b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1298 1299 1300 /* ------------------------------ */ 1301 .balign 128 1302 .L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1303 /* File: mips/OP_FILL_ARRAY_DATA.S */ 1304 /* fill-array-data vAA, +BBBBBBBB */ 1305 FETCH(a0, 1) # a0 <- bbbb (lo) 1306 FETCH(a1, 2) # a1 <- BBBB (hi) 1307 GET_OPA(a3) # a3 <- AA 1308 sll a1, a1, 16 # a1 <- BBBBbbbb 1309 or a1, a0, a1 # a1 <- BBBBbbbb 1310 GET_VREG(a0, a3) # a0 <- vAA (array object) 1311 EAS1(a1, rPC, a1) # a1 <- PC + BBBBbbbb*2 (array data off.) 1312 EXPORT_PC() 1313 JAL(dvmInterpHandleFillArrayData) # fill the array with predefined data 1314 # 0 means an exception is thrown 1315 beqz v0, common_exceptionThrown # has exception 1316 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 1317 GET_INST_OPCODE(t0) # extract opcode from rINST 1318 GOTO_OPCODE(t0) # jump to next instruction 1319 1320 /* ------------------------------ */ 1321 .balign 128 1322 .L_OP_THROW: /* 0x27 */ 1323 /* File: mips/OP_THROW.S */ 1324 /* 1325 * Throw an exception object in the current thread. 1326 */ 1327 /* throw vAA */ 1328 GET_OPA(a2) # a2 <- AA 1329 GET_VREG(a1, a2) # a1 <- vAA (exception object) 1330 EXPORT_PC() # exception handler can throw 1331 # null object? 1332 beqz a1, common_errNullObject # yes, throw an NPE instead 1333 # bypass dvmSetException, just store it 1334 STORE_offThread_exception(a1, rSELF) # thread->exception <- obj 1335 b common_exceptionThrown 1336 1337 1338 /* ------------------------------ */ 1339 .balign 128 1340 .L_OP_GOTO: /* 0x28 */ 1341 /* File: mips/OP_GOTO.S */ 1342 /* 1343 * Unconditional branch, 8-bit offset. 1344 * 1345 * The branch distance is a signed code-unit offset, which we need to 1346 * double to get a byte offset. 1347 */ 1348 /* goto +AA */ 1349 sll a0, rINST, 16 # a0 <- AAxx0000 1350 sra a1, a0, 24 # a1 <- ssssssAA (sign-extended) 1351 addu a2, a1, a1 # a2 <- byte offset 1352 /* If backwards branch refresh rBASE */ 1353 bgez a1, 1f 1354 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh handler base 1355 1: 1356 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1357 #if defined(WITH_JIT) 1358 lw a0, offThread_pJitProfTable(rSELF) 1359 bltz a1, common_testUpdateProfile # (a0) check for trace hotness 1360 #endif 1361 GET_INST_OPCODE(t0) # extract opcode from rINST 1362 GOTO_OPCODE(t0) # jump to next instruction 1363 1364 /* ------------------------------ */ 1365 .balign 128 1366 .L_OP_GOTO_16: /* 0x29 */ 1367 /* File: mips/OP_GOTO_16.S */ 1368 /* 1369 * Unconditional branch, 16-bit offset. 1370 * 1371 * The branch distance is a signed code-unit offset, which we need to 1372 * double to get a byte offset. 1373 */ 1374 /* goto/16 +AAAA */ 1375 FETCH_S(a0, 1) # a0 <- ssssAAAA (sign-extended) 1376 addu a1, a0, a0 # a1 <- byte offset, flags set 1377 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1378 bgez a1, 1f 1379 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh handler base 1380 1: 1381 #if defined(WITH_JIT) 1382 lw a0, offThread_pJitProfTable(rSELF) 1383 bltz a1, common_testUpdateProfile # (a0) hot trace head? 1384 #endif 1385 GET_INST_OPCODE(t0) # extract opcode from rINST 1386 GOTO_OPCODE(t0) # jump to next instruction 1387 1388 /* ------------------------------ */ 1389 .balign 128 1390 .L_OP_GOTO_32: /* 0x2a */ 1391 /* File: mips/OP_GOTO_32.S */ 1392 /* 1393 * Unconditional branch, 32-bit offset. 1394 * 1395 * The branch distance is a signed code-unit offset, which we need to 1396 * double to get a byte offset. 1397 * 1398 * Unlike most opcodes, this one is allowed to branch to itself, so 1399 * our "backward branch" test must be "<=0" instead of "<0". 1400 */ 1401 /* goto/32 +AAAAAAAA */ 1402 FETCH(a0, 1) # a0 <- aaaa (lo) 1403 FETCH(a1, 2) # a1 <- AAAA (hi) 1404 sll a1, a1, 16 1405 or a0, a0, a1 # a0 <- AAAAaaaa 1406 addu a1, a0, a0 # a1 <- byte offset 1407 #if defined(WITH_JIT) 1408 lw a0, offThread_pJitProfTable(rSELF) 1409 bgtz a1, 1f 1410 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh handler base 1411 1: 1412 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1413 blez a1, common_testUpdateProfile # (a0) hot trace head? 1414 #else 1415 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1416 bgtz a0, 2f 1417 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh handler base 1418 2: 1419 #endif 1420 GET_INST_OPCODE(t0) # extract opcode from rINST 1421 GOTO_OPCODE(t0) # jump to next instruction 1422 1423 /* ------------------------------ */ 1424 .balign 128 1425 .L_OP_PACKED_SWITCH: /* 0x2b */ 1426 /* File: mips/OP_PACKED_SWITCH.S */ 1427 /* 1428 * Handle a packed-switch or sparse-switch instruction. In both cases 1429 * we decode it and hand it off to a helper function. 1430 * 1431 * We don't really expect backward branches in a switch statement, but 1432 * they're perfectly legal, so we check for them here. 1433 * 1434 * When the JIT is present, all targets are considered treated as 1435 * a potential trace heads regardless of branch direction. 1436 * 1437 * for: packed-switch, sparse-switch 1438 */ 1439 /* op vAA, +BBBB */ 1440 FETCH(a0, 1) # a0 <- bbbb (lo) 1441 FETCH(a1, 2) # a1 <- BBBB (hi) 1442 GET_OPA(a3) # a3 <- AA 1443 sll t0, a1, 16 1444 or a0, a0, t0 # a0 <- BBBBbbbb 1445 GET_VREG(a1, a3) # a1 <- vAA 1446 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 1447 JAL(dvmInterpHandlePackedSwitch) # a0 <- code-unit branch offset 1448 addu a1, v0, v0 # a1 <- byte offset 1449 bgtz a1, 1f 1450 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh handler base 1451 1: 1452 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1453 #if defined(WITH_JIT) 1454 lw a0, offThread_pJitProfTable(rSELF) 1455 bnez a0, common_updateProfile 1456 #endif 1457 GET_INST_OPCODE(t0) # extract opcode from rINST 1458 GOTO_OPCODE(t0) # jump to next instruction 1459 1460 /* ------------------------------ */ 1461 .balign 128 1462 .L_OP_SPARSE_SWITCH: /* 0x2c */ 1463 /* File: mips/OP_SPARSE_SWITCH.S */ 1464 /* File: mips/OP_PACKED_SWITCH.S */ 1465 /* 1466 * Handle a packed-switch or sparse-switch instruction. In both cases 1467 * we decode it and hand it off to a helper function. 1468 * 1469 * We don't really expect backward branches in a switch statement, but 1470 * they're perfectly legal, so we check for them here. 1471 * 1472 * When the JIT is present, all targets are considered treated as 1473 * a potential trace heads regardless of branch direction. 1474 * 1475 * for: packed-switch, sparse-switch 1476 */ 1477 /* op vAA, +BBBB */ 1478 FETCH(a0, 1) # a0 <- bbbb (lo) 1479 FETCH(a1, 2) # a1 <- BBBB (hi) 1480 GET_OPA(a3) # a3 <- AA 1481 sll t0, a1, 16 1482 or a0, a0, t0 # a0 <- BBBBbbbb 1483 GET_VREG(a1, a3) # a1 <- vAA 1484 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 1485 JAL(dvmInterpHandleSparseSwitch) # a0 <- code-unit branch offset 1486 addu a1, v0, v0 # a1 <- byte offset 1487 bgtz a1, 1f 1488 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh handler base 1489 1: 1490 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1491 #if defined(WITH_JIT) 1492 lw a0, offThread_pJitProfTable(rSELF) 1493 bnez a0, common_updateProfile 1494 #endif 1495 GET_INST_OPCODE(t0) # extract opcode from rINST 1496 GOTO_OPCODE(t0) # jump to next instruction 1497 1498 1499 /* ------------------------------ */ 1500 .balign 128 1501 .L_OP_CMPL_FLOAT: /* 0x2d */ 1502 /* File: mips/OP_CMPL_FLOAT.S */ 1503 /* 1504 * Compare two floating-point values. Puts 0, 1, or -1 into the 1505 * destination register based on the results of the comparison. 1506 * 1507 * Provide a "naninst" instruction that puts 1 or -1 into a1 depending 1508 * on what value we'd like to return when one of the operands is NaN. 1509 * 1510 * The operation we're implementing is: 1511 * if (x == y) 1512 * return 0; 1513 * else if (x < y) 1514 * return -1; 1515 * else if (x > y) 1516 * return 1; 1517 * else 1518 * return {-1,1}; // one or both operands was NaN 1519 * 1520 * for: cmpl-float, cmpg-float 1521 */ 1522 /* op vAA, vBB, vCC */ 1523 1524 /* "clasic" form */ 1525 FETCH(a0, 1) # a0 <- CCBB 1526 and a2, a0, 255 # a2 <- BB 1527 srl a3, a0, 8 1528 #ifdef SOFT_FLOAT 1529 GET_VREG(rOBJ, a2) # rOBJ <- vBB 1530 GET_VREG(rBIX, a3) # rBIX <- vCC 1531 move a0, rOBJ # a0 <- vBB 1532 move a1, rBIX # a1 <- vCC 1533 JAL(__eqsf2) # a0 <- (vBB == vCC) 1534 li rTEMP, 0 # set rTEMP to 0 1535 beqz v0, OP_CMPL_FLOAT_finish 1536 move a0, rOBJ # a0 <- vBB 1537 move a1, rBIX # a1 <- vCC 1538 JAL(__ltsf2) # a0 <- (vBB < vCC) 1539 li rTEMP, -1 1540 bltz v0, OP_CMPL_FLOAT_finish 1541 move a0, rOBJ # a0 <- vBB 1542 move a1, rBIX # a1 <- vCC 1543 b OP_CMPL_FLOAT_continue 1544 #else 1545 GET_VREG_F(fs0, a2) 1546 GET_VREG_F(fs1, a3) 1547 c.olt.s fcc0, fs0, fs1 # Is fs0 < fs1 1548 li rTEMP, -1 1549 bc1t fcc0, OP_CMPL_FLOAT_finish 1550 c.olt.s fcc0, fs1, fs0 1551 li rTEMP, 1 1552 bc1t fcc0, OP_CMPL_FLOAT_finish 1553 c.eq.s fcc0, fs0, fs1 1554 li rTEMP, 0 1555 bc1t fcc0, OP_CMPL_FLOAT_finish 1556 b OP_CMPL_FLOAT_nan 1557 1558 #endif 1559 1560 1561 /* ------------------------------ */ 1562 .balign 128 1563 .L_OP_CMPG_FLOAT: /* 0x2e */ 1564 /* File: mips/OP_CMPG_FLOAT.S */ 1565 /* File: mips/OP_CMPL_FLOAT.S */ 1566 /* 1567 * Compare two floating-point values. Puts 0, 1, or -1 into the 1568 * destination register based on the results of the comparison. 1569 * 1570 * Provide a "naninst" instruction that puts 1 or -1 into a1 depending 1571 * on what value we'd like to return when one of the operands is NaN. 1572 * 1573 * The operation we're implementing is: 1574 * if (x == y) 1575 * return 0; 1576 * else if (x < y) 1577 * return -1; 1578 * else if (x > y) 1579 * return 1; 1580 * else 1581 * return {-1,1}; // one or both operands was NaN 1582 * 1583 * for: cmpl-float, cmpg-float 1584 */ 1585 /* op vAA, vBB, vCC */ 1586 1587 /* "clasic" form */ 1588 FETCH(a0, 1) # a0 <- CCBB 1589 and a2, a0, 255 # a2 <- BB 1590 srl a3, a0, 8 1591 #ifdef SOFT_FLOAT 1592 GET_VREG(rOBJ, a2) # rOBJ <- vBB 1593 GET_VREG(rBIX, a3) # rBIX <- vCC 1594 move a0, rOBJ # a0 <- vBB 1595 move a1, rBIX # a1 <- vCC 1596 JAL(__eqsf2) # a0 <- (vBB == vCC) 1597 li rTEMP, 0 # set rTEMP to 0 1598 beqz v0, OP_CMPG_FLOAT_finish 1599 move a0, rOBJ # a0 <- vBB 1600 move a1, rBIX # a1 <- vCC 1601 JAL(__ltsf2) # a0 <- (vBB < vCC) 1602 li rTEMP, -1 1603 bltz v0, OP_CMPG_FLOAT_finish 1604 move a0, rOBJ # a0 <- vBB 1605 move a1, rBIX # a1 <- vCC 1606 b OP_CMPG_FLOAT_continue 1607 #else 1608 GET_VREG_F(fs0, a2) 1609 GET_VREG_F(fs1, a3) 1610 c.olt.s fcc0, fs0, fs1 # Is fs0 < fs1 1611 li rTEMP, -1 1612 bc1t fcc0, OP_CMPG_FLOAT_finish 1613 c.olt.s fcc0, fs1, fs0 1614 li rTEMP, 1 1615 bc1t fcc0, OP_CMPG_FLOAT_finish 1616 c.eq.s fcc0, fs0, fs1 1617 li rTEMP, 0 1618 bc1t fcc0, OP_CMPG_FLOAT_finish 1619 b OP_CMPG_FLOAT_nan 1620 1621 #endif 1622 1623 1624 1625 /* ------------------------------ */ 1626 .balign 128 1627 .L_OP_CMPL_DOUBLE: /* 0x2f */ 1628 /* File: mips/OP_CMPL_DOUBLE.S */ 1629 /* 1630 * Compare two floating-point values. Puts 0, 1, or -1 into the 1631 * destination register based on the results of the comparison. 1632 * 1633 * Provide a "naninst" instruction that puts 1 or -1 into a1 depending 1634 * on what value we'd like to return when one of the operands is NaN. 1635 * 1636 * See OP_CMPL_FLOAT for an explanation. 1637 * 1638 * For: cmpl-double, cmpg-double 1639 */ 1640 /* op vAA, vBB, vCC */ 1641 1642 FETCH(a0, 1) # a0 <- CCBB 1643 and rOBJ, a0, 255 # s0 <- BB 1644 srl rBIX, a0, 8 # t0 <- CC 1645 EAS2(rOBJ, rFP, rOBJ) # s0 <- &fp[BB] 1646 EAS2(rBIX, rFP, rBIX) # t0 <- &fp[CC] 1647 #ifdef SOFT_FLOAT 1648 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1 1649 LOAD64(rARG2, rARG3, rBIX) # a2/a3 <- vCC/vCC+1 1650 JAL(__eqdf2) # cmp <=: C clear if <, Z set if eq 1651 li rTEMP, 0 1652 beqz v0, OP_CMPL_DOUBLE_finish 1653 1654 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1 1655 LOAD64(rARG2, rARG3, rBIX) # a2/a3 <- vCC/vCC+1 1656 JAL(__ltdf2) 1657 li rTEMP, -1 1658 bltz v0, OP_CMPL_DOUBLE_finish 1659 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1 1660 b OP_CMPL_DOUBLE_continue 1661 #else 1662 LOAD64_F(fs0, fs0f, rOBJ) 1663 LOAD64_F(fs1, fs1f, rBIX) 1664 c.olt.d fcc0, fs0, fs1 1665 li rTEMP, -1 1666 bc1t fcc0, OP_CMPL_DOUBLE_finish 1667 c.olt.d fcc0, fs1, fs0 1668 li rTEMP, 1 1669 bc1t fcc0, OP_CMPL_DOUBLE_finish 1670 c.eq.d fcc0, fs0, fs1 1671 li rTEMP, 0 1672 bc1t fcc0, OP_CMPL_DOUBLE_finish 1673 b OP_CMPL_DOUBLE_nan 1674 #endif 1675 1676 /* ------------------------------ */ 1677 .balign 128 1678 .L_OP_CMPG_DOUBLE: /* 0x30 */ 1679 /* File: mips/OP_CMPG_DOUBLE.S */ 1680 /* File: mips/OP_CMPL_DOUBLE.S */ 1681 /* 1682 * Compare two floating-point values. Puts 0, 1, or -1 into the 1683 * destination register based on the results of the comparison. 1684 * 1685 * Provide a "naninst" instruction that puts 1 or -1 into a1 depending 1686 * on what value we'd like to return when one of the operands is NaN. 1687 * 1688 * See OP_CMPL_FLOAT for an explanation. 1689 * 1690 * For: cmpl-double, cmpg-double 1691 */ 1692 /* op vAA, vBB, vCC */ 1693 1694 FETCH(a0, 1) # a0 <- CCBB 1695 and rOBJ, a0, 255 # s0 <- BB 1696 srl rBIX, a0, 8 # t0 <- CC 1697 EAS2(rOBJ, rFP, rOBJ) # s0 <- &fp[BB] 1698 EAS2(rBIX, rFP, rBIX) # t0 <- &fp[CC] 1699 #ifdef SOFT_FLOAT 1700 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1 1701 LOAD64(rARG2, rARG3, rBIX) # a2/a3 <- vCC/vCC+1 1702 JAL(__eqdf2) # cmp <=: C clear if <, Z set if eq 1703 li rTEMP, 0 1704 beqz v0, OP_CMPG_DOUBLE_finish 1705 1706 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1 1707 LOAD64(rARG2, rARG3, rBIX) # a2/a3 <- vCC/vCC+1 1708 JAL(__ltdf2) 1709 li rTEMP, -1 1710 bltz v0, OP_CMPG_DOUBLE_finish 1711 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1 1712 b OP_CMPG_DOUBLE_continue 1713 #else 1714 LOAD64_F(fs0, fs0f, rOBJ) 1715 LOAD64_F(fs1, fs1f, rBIX) 1716 c.olt.d fcc0, fs0, fs1 1717 li rTEMP, -1 1718 bc1t fcc0, OP_CMPG_DOUBLE_finish 1719 c.olt.d fcc0, fs1, fs0 1720 li rTEMP, 1 1721 bc1t fcc0, OP_CMPG_DOUBLE_finish 1722 c.eq.d fcc0, fs0, fs1 1723 li rTEMP, 0 1724 bc1t fcc0, OP_CMPG_DOUBLE_finish 1725 b OP_CMPG_DOUBLE_nan 1726 #endif 1727 1728 1729 /* ------------------------------ */ 1730 .balign 128 1731 .L_OP_CMP_LONG: /* 0x31 */ 1732 /* File: mips/OP_CMP_LONG.S */ 1733 /* 1734 * Compare two 64-bit values 1735 * x = y return 0 1736 * x < y return -1 1737 * x > y return 1 1738 * 1739 * I think I can improve on the ARM code by the following observation 1740 * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 1741 * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 1742 * subu v0, t0, t1 # v0= -1:1:0 for [ < > = ] 1743 */ 1744 /* cmp-long vAA, vBB, vCC */ 1745 FETCH(a0, 1) # a0 <- CCBB 1746 GET_OPA(rOBJ) # rOBJ <- AA 1747 and a2, a0, 255 # a2 <- BB 1748 srl a3, a0, 8 # a3 <- CC 1749 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 1750 EAS2(a3, rFP, a3) # a3 <- &fp[CC] 1751 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 1752 LOAD64(a2, a3, a3) # a2/a3 <- vCC/vCC+1 1753 1754 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1755 slt t0, a1, a3 # compare hi 1756 sgt t1, a1, a3 1757 subu v0, t1, t0 # v0 <- (-1, 1, 0) 1758 bnez v0, .LOP_CMP_LONG_finish 1759 # at this point x.hi==y.hi 1760 sltu t0, a0, a2 # compare lo 1761 sgtu t1, a0, a2 1762 subu v0, t1, t0 # v0 <- (-1, 1, 0) for [< > =] 1763 1764 .LOP_CMP_LONG_finish: 1765 SET_VREG(v0, rOBJ) # vAA <- v0 1766 GET_INST_OPCODE(t0) # extract opcode from rINST 1767 GOTO_OPCODE(t0) # jump to next instruction 1768 1769 1770 /* ------------------------------ */ 1771 .balign 128 1772 .L_OP_IF_EQ: /* 0x32 */ 1773 /* File: mips/OP_IF_EQ.S */ 1774 /* File: mips/bincmp.S */ 1775 /* 1776 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1777 * fragment that specifies the *reverse* comparison to perform, e.g. 1778 * for "if-le" you would use "gt". 1779 * 1780 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1781 */ 1782 /* if-cmp vA, vB, +CCCC */ 1783 GET_OPA4(a0) # a0 <- A+ 1784 GET_OPB(a1) # a1 <- B 1785 GET_VREG(a3, a1) # a3 <- vB 1786 GET_VREG(a2, a0) # a2 <- vA 1787 bne a2, a3, 1f # branch to 1 if comparison failed 1788 FETCH_S(a1, 1) # a1<- branch offset, in code units 1789 b 2f 1790 1: 1791 li a1, 2 # a1- BYTE branch dist for not-taken 1792 2: 1793 addu a2, a1, a1 # convert to bytes 1794 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1795 #if defined(WITH_JIT) 1796 lw a0, offThread_pJitProfTable(rSELF) 1797 bgez a2, 3f 1798 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1799 3: 1800 bnez a0, common_updateProfile 1801 #else 1802 bgez a2, 4f 1803 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1804 4: 1805 #endif 1806 GET_INST_OPCODE(t0) # extract opcode from rINST 1807 GOTO_OPCODE(t0) # jump to next instruction 1808 1809 1810 /* ------------------------------ */ 1811 .balign 128 1812 .L_OP_IF_NE: /* 0x33 */ 1813 /* File: mips/OP_IF_NE.S */ 1814 /* File: mips/bincmp.S */ 1815 /* 1816 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1817 * fragment that specifies the *reverse* comparison to perform, e.g. 1818 * for "if-le" you would use "gt". 1819 * 1820 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1821 */ 1822 /* if-cmp vA, vB, +CCCC */ 1823 GET_OPA4(a0) # a0 <- A+ 1824 GET_OPB(a1) # a1 <- B 1825 GET_VREG(a3, a1) # a3 <- vB 1826 GET_VREG(a2, a0) # a2 <- vA 1827 beq a2, a3, 1f # branch to 1 if comparison failed 1828 FETCH_S(a1, 1) # a1<- branch offset, in code units 1829 b 2f 1830 1: 1831 li a1, 2 # a1- BYTE branch dist for not-taken 1832 2: 1833 addu a2, a1, a1 # convert to bytes 1834 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1835 #if defined(WITH_JIT) 1836 lw a0, offThread_pJitProfTable(rSELF) 1837 bgez a2, 3f 1838 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1839 3: 1840 bnez a0, common_updateProfile 1841 #else 1842 bgez a2, 4f 1843 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1844 4: 1845 #endif 1846 GET_INST_OPCODE(t0) # extract opcode from rINST 1847 GOTO_OPCODE(t0) # jump to next instruction 1848 1849 1850 /* ------------------------------ */ 1851 .balign 128 1852 .L_OP_IF_LT: /* 0x34 */ 1853 /* File: mips/OP_IF_LT.S */ 1854 /* File: mips/bincmp.S */ 1855 /* 1856 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1857 * fragment that specifies the *reverse* comparison to perform, e.g. 1858 * for "if-le" you would use "gt". 1859 * 1860 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1861 */ 1862 /* if-cmp vA, vB, +CCCC */ 1863 GET_OPA4(a0) # a0 <- A+ 1864 GET_OPB(a1) # a1 <- B 1865 GET_VREG(a3, a1) # a3 <- vB 1866 GET_VREG(a2, a0) # a2 <- vA 1867 bge a2, a3, 1f # branch to 1 if comparison failed 1868 FETCH_S(a1, 1) # a1<- branch offset, in code units 1869 b 2f 1870 1: 1871 li a1, 2 # a1- BYTE branch dist for not-taken 1872 2: 1873 addu a2, a1, a1 # convert to bytes 1874 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1875 #if defined(WITH_JIT) 1876 lw a0, offThread_pJitProfTable(rSELF) 1877 bgez a2, 3f 1878 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1879 3: 1880 bnez a0, common_updateProfile 1881 #else 1882 bgez a2, 4f 1883 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1884 4: 1885 #endif 1886 GET_INST_OPCODE(t0) # extract opcode from rINST 1887 GOTO_OPCODE(t0) # jump to next instruction 1888 1889 1890 /* ------------------------------ */ 1891 .balign 128 1892 .L_OP_IF_GE: /* 0x35 */ 1893 /* File: mips/OP_IF_GE.S */ 1894 /* File: mips/bincmp.S */ 1895 /* 1896 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1897 * fragment that specifies the *reverse* comparison to perform, e.g. 1898 * for "if-le" you would use "gt". 1899 * 1900 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1901 */ 1902 /* if-cmp vA, vB, +CCCC */ 1903 GET_OPA4(a0) # a0 <- A+ 1904 GET_OPB(a1) # a1 <- B 1905 GET_VREG(a3, a1) # a3 <- vB 1906 GET_VREG(a2, a0) # a2 <- vA 1907 blt a2, a3, 1f # branch to 1 if comparison failed 1908 FETCH_S(a1, 1) # a1<- branch offset, in code units 1909 b 2f 1910 1: 1911 li a1, 2 # a1- BYTE branch dist for not-taken 1912 2: 1913 addu a2, a1, a1 # convert to bytes 1914 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1915 #if defined(WITH_JIT) 1916 lw a0, offThread_pJitProfTable(rSELF) 1917 bgez a2, 3f 1918 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1919 3: 1920 bnez a0, common_updateProfile 1921 #else 1922 bgez a2, 4f 1923 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1924 4: 1925 #endif 1926 GET_INST_OPCODE(t0) # extract opcode from rINST 1927 GOTO_OPCODE(t0) # jump to next instruction 1928 1929 1930 /* ------------------------------ */ 1931 .balign 128 1932 .L_OP_IF_GT: /* 0x36 */ 1933 /* File: mips/OP_IF_GT.S */ 1934 /* File: mips/bincmp.S */ 1935 /* 1936 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1937 * fragment that specifies the *reverse* comparison to perform, e.g. 1938 * for "if-le" you would use "gt". 1939 * 1940 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1941 */ 1942 /* if-cmp vA, vB, +CCCC */ 1943 GET_OPA4(a0) # a0 <- A+ 1944 GET_OPB(a1) # a1 <- B 1945 GET_VREG(a3, a1) # a3 <- vB 1946 GET_VREG(a2, a0) # a2 <- vA 1947 ble a2, a3, 1f # branch to 1 if comparison failed 1948 FETCH_S(a1, 1) # a1<- branch offset, in code units 1949 b 2f 1950 1: 1951 li a1, 2 # a1- BYTE branch dist for not-taken 1952 2: 1953 addu a2, a1, a1 # convert to bytes 1954 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1955 #if defined(WITH_JIT) 1956 lw a0, offThread_pJitProfTable(rSELF) 1957 bgez a2, 3f 1958 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1959 3: 1960 bnez a0, common_updateProfile 1961 #else 1962 bgez a2, 4f 1963 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1964 4: 1965 #endif 1966 GET_INST_OPCODE(t0) # extract opcode from rINST 1967 GOTO_OPCODE(t0) # jump to next instruction 1968 1969 1970 /* ------------------------------ */ 1971 .balign 128 1972 .L_OP_IF_LE: /* 0x37 */ 1973 /* File: mips/OP_IF_LE.S */ 1974 /* File: mips/bincmp.S */ 1975 /* 1976 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1977 * fragment that specifies the *reverse* comparison to perform, e.g. 1978 * for "if-le" you would use "gt". 1979 * 1980 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1981 */ 1982 /* if-cmp vA, vB, +CCCC */ 1983 GET_OPA4(a0) # a0 <- A+ 1984 GET_OPB(a1) # a1 <- B 1985 GET_VREG(a3, a1) # a3 <- vB 1986 GET_VREG(a2, a0) # a2 <- vA 1987 bgt a2, a3, 1f # branch to 1 if comparison failed 1988 FETCH_S(a1, 1) # a1<- branch offset, in code units 1989 b 2f 1990 1: 1991 li a1, 2 # a1- BYTE branch dist for not-taken 1992 2: 1993 addu a2, a1, a1 # convert to bytes 1994 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1995 #if defined(WITH_JIT) 1996 lw a0, offThread_pJitProfTable(rSELF) 1997 bgez a2, 3f 1998 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 1999 3: 2000 bnez a0, common_updateProfile 2001 #else 2002 bgez a2, 4f 2003 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 2004 4: 2005 #endif 2006 GET_INST_OPCODE(t0) # extract opcode from rINST 2007 GOTO_OPCODE(t0) # jump to next instruction 2008 2009 2010 /* ------------------------------ */ 2011 .balign 128 2012 .L_OP_IF_EQZ: /* 0x38 */ 2013 /* File: mips/OP_IF_EQZ.S */ 2014 /* File: mips/zcmp.S */ 2015 /* 2016 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2017 * fragment that specifies the *reverse* comparison to perform, e.g. 2018 * for "if-le" you would use "gt". 2019 * 2020 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2021 */ 2022 /* if-cmp vAA, +BBBB */ 2023 GET_OPA(a0) # a0 <- AA 2024 GET_VREG(a2, a0) # a2 <- vAA 2025 FETCH_S(a1, 1) # a1 <- branch offset, in code units 2026 bne a2, zero, 1f # branch to 1 if comparison failed 2027 b 2f 2028 1: 2029 li a1, 2 # a1- BYTE branch dist for not-taken 2030 2: 2031 addu a1, a1, a1 # convert to bytes 2032 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2033 #if defined(WITH_JIT) 2034 lw a0, offThread_pJitProfTable(rSELF) 2035 bgez a1, 3f 2036 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh table base 2037 3: 2038 bnez a0, common_updateProfile # test for JIT off at target 2039 #else 2040 bgez a1, 4f 2041 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rtable base 2042 4: 2043 #endif 2044 GET_INST_OPCODE(t0) # extract opcode from rINST 2045 GOTO_OPCODE(t0) # jump to next instruction 2046 2047 2048 /* ------------------------------ */ 2049 .balign 128 2050 .L_OP_IF_NEZ: /* 0x39 */ 2051 /* File: mips/OP_IF_NEZ.S */ 2052 /* File: mips/zcmp.S */ 2053 /* 2054 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2055 * fragment that specifies the *reverse* comparison to perform, e.g. 2056 * for "if-le" you would use "gt". 2057 * 2058 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2059 */ 2060 /* if-cmp vAA, +BBBB */ 2061 GET_OPA(a0) # a0 <- AA 2062 GET_VREG(a2, a0) # a2 <- vAA 2063 FETCH_S(a1, 1) # a1 <- branch offset, in code units 2064 beq a2, zero, 1f # branch to 1 if comparison failed 2065 b 2f 2066 1: 2067 li a1, 2 # a1- BYTE branch dist for not-taken 2068 2: 2069 addu a1, a1, a1 # convert to bytes 2070 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2071 #if defined(WITH_JIT) 2072 lw a0, offThread_pJitProfTable(rSELF) 2073 bgez a1, 3f 2074 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh table base 2075 3: 2076 bnez a0, common_updateProfile # test for JIT off at target 2077 #else 2078 bgez a1, 4f 2079 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rtable base 2080 4: 2081 #endif 2082 GET_INST_OPCODE(t0) # extract opcode from rINST 2083 GOTO_OPCODE(t0) # jump to next instruction 2084 2085 2086 /* ------------------------------ */ 2087 .balign 128 2088 .L_OP_IF_LTZ: /* 0x3a */ 2089 /* File: mips/OP_IF_LTZ.S */ 2090 /* File: mips/zcmp.S */ 2091 /* 2092 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2093 * fragment that specifies the *reverse* comparison to perform, e.g. 2094 * for "if-le" you would use "gt". 2095 * 2096 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2097 */ 2098 /* if-cmp vAA, +BBBB */ 2099 GET_OPA(a0) # a0 <- AA 2100 GET_VREG(a2, a0) # a2 <- vAA 2101 FETCH_S(a1, 1) # a1 <- branch offset, in code units 2102 bge a2, zero, 1f # branch to 1 if comparison failed 2103 b 2f 2104 1: 2105 li a1, 2 # a1- BYTE branch dist for not-taken 2106 2: 2107 addu a1, a1, a1 # convert to bytes 2108 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2109 #if defined(WITH_JIT) 2110 lw a0, offThread_pJitProfTable(rSELF) 2111 bgez a1, 3f 2112 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh table base 2113 3: 2114 bnez a0, common_updateProfile # test for JIT off at target 2115 #else 2116 bgez a1, 4f 2117 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rtable base 2118 4: 2119 #endif 2120 GET_INST_OPCODE(t0) # extract opcode from rINST 2121 GOTO_OPCODE(t0) # jump to next instruction 2122 2123 2124 /* ------------------------------ */ 2125 .balign 128 2126 .L_OP_IF_GEZ: /* 0x3b */ 2127 /* File: mips/OP_IF_GEZ.S */ 2128 /* File: mips/zcmp.S */ 2129 /* 2130 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2131 * fragment that specifies the *reverse* comparison to perform, e.g. 2132 * for "if-le" you would use "gt". 2133 * 2134 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2135 */ 2136 /* if-cmp vAA, +BBBB */ 2137 GET_OPA(a0) # a0 <- AA 2138 GET_VREG(a2, a0) # a2 <- vAA 2139 FETCH_S(a1, 1) # a1 <- branch offset, in code units 2140 blt a2, zero, 1f # branch to 1 if comparison failed 2141 b 2f 2142 1: 2143 li a1, 2 # a1- BYTE branch dist for not-taken 2144 2: 2145 addu a1, a1, a1 # convert to bytes 2146 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2147 #if defined(WITH_JIT) 2148 lw a0, offThread_pJitProfTable(rSELF) 2149 bgez a1, 3f 2150 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh table base 2151 3: 2152 bnez a0, common_updateProfile # test for JIT off at target 2153 #else 2154 bgez a1, 4f 2155 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rtable base 2156 4: 2157 #endif 2158 GET_INST_OPCODE(t0) # extract opcode from rINST 2159 GOTO_OPCODE(t0) # jump to next instruction 2160 2161 2162 /* ------------------------------ */ 2163 .balign 128 2164 .L_OP_IF_GTZ: /* 0x3c */ 2165 /* File: mips/OP_IF_GTZ.S */ 2166 /* File: mips/zcmp.S */ 2167 /* 2168 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2169 * fragment that specifies the *reverse* comparison to perform, e.g. 2170 * for "if-le" you would use "gt". 2171 * 2172 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2173 */ 2174 /* if-cmp vAA, +BBBB */ 2175 GET_OPA(a0) # a0 <- AA 2176 GET_VREG(a2, a0) # a2 <- vAA 2177 FETCH_S(a1, 1) # a1 <- branch offset, in code units 2178 ble a2, zero, 1f # branch to 1 if comparison failed 2179 b 2f 2180 1: 2181 li a1, 2 # a1- BYTE branch dist for not-taken 2182 2: 2183 addu a1, a1, a1 # convert to bytes 2184 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2185 #if defined(WITH_JIT) 2186 lw a0, offThread_pJitProfTable(rSELF) 2187 bgez a1, 3f 2188 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh table base 2189 3: 2190 bnez a0, common_updateProfile # test for JIT off at target 2191 #else 2192 bgez a1, 4f 2193 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rtable base 2194 4: 2195 #endif 2196 GET_INST_OPCODE(t0) # extract opcode from rINST 2197 GOTO_OPCODE(t0) # jump to next instruction 2198 2199 2200 /* ------------------------------ */ 2201 .balign 128 2202 .L_OP_IF_LEZ: /* 0x3d */ 2203 /* File: mips/OP_IF_LEZ.S */ 2204 /* File: mips/zcmp.S */ 2205 /* 2206 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2207 * fragment that specifies the *reverse* comparison to perform, e.g. 2208 * for "if-le" you would use "gt". 2209 * 2210 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2211 */ 2212 /* if-cmp vAA, +BBBB */ 2213 GET_OPA(a0) # a0 <- AA 2214 GET_VREG(a2, a0) # a2 <- vAA 2215 FETCH_S(a1, 1) # a1 <- branch offset, in code units 2216 bgt a2, zero, 1f # branch to 1 if comparison failed 2217 b 2f 2218 1: 2219 li a1, 2 # a1- BYTE branch dist for not-taken 2220 2: 2221 addu a1, a1, a1 # convert to bytes 2222 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2223 #if defined(WITH_JIT) 2224 lw a0, offThread_pJitProfTable(rSELF) 2225 bgez a1, 3f 2226 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh table base 2227 3: 2228 bnez a0, common_updateProfile # test for JIT off at target 2229 #else 2230 bgez a1, 4f 2231 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rtable base 2232 4: 2233 #endif 2234 GET_INST_OPCODE(t0) # extract opcode from rINST 2235 GOTO_OPCODE(t0) # jump to next instruction 2236 2237 2238 /* ------------------------------ */ 2239 .balign 128 2240 .L_OP_UNUSED_3E: /* 0x3e */ 2241 /* File: mips/OP_UNUSED_3E.S */ 2242 /* File: mips/unused.S */ 2243 BAL(common_abort) 2244 2245 2246 2247 /* ------------------------------ */ 2248 .balign 128 2249 .L_OP_UNUSED_3F: /* 0x3f */ 2250 /* File: mips/OP_UNUSED_3F.S */ 2251 /* File: mips/unused.S */ 2252 BAL(common_abort) 2253 2254 2255 2256 /* ------------------------------ */ 2257 .balign 128 2258 .L_OP_UNUSED_40: /* 0x40 */ 2259 /* File: mips/OP_UNUSED_40.S */ 2260 /* File: mips/unused.S */ 2261 BAL(common_abort) 2262 2263 2264 2265 /* ------------------------------ */ 2266 .balign 128 2267 .L_OP_UNUSED_41: /* 0x41 */ 2268 /* File: mips/OP_UNUSED_41.S */ 2269 /* File: mips/unused.S */ 2270 BAL(common_abort) 2271 2272 2273 2274 /* ------------------------------ */ 2275 .balign 128 2276 .L_OP_UNUSED_42: /* 0x42 */ 2277 /* File: mips/OP_UNUSED_42.S */ 2278 /* File: mips/unused.S */ 2279 BAL(common_abort) 2280 2281 2282 2283 /* ------------------------------ */ 2284 .balign 128 2285 .L_OP_UNUSED_43: /* 0x43 */ 2286 /* File: mips/OP_UNUSED_43.S */ 2287 /* File: mips/unused.S */ 2288 BAL(common_abort) 2289 2290 2291 2292 /* ------------------------------ */ 2293 .balign 128 2294 .L_OP_AGET: /* 0x44 */ 2295 /* File: mips/OP_AGET.S */ 2296 /* 2297 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2298 * 2299 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2300 * instructions. We use a pair of FETCH_Bs instead. 2301 * 2302 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2303 */ 2304 /* op vAA, vBB, vCC */ 2305 FETCH_B(a2, 1) # a2 <- BB 2306 GET_OPA(rOBJ) # rOBJ <- AA 2307 FETCH_C(a3, 1) # a3 <- CC 2308 GET_VREG(a0, a2) # a0 <- vBB (array object) 2309 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2310 # null array object? 2311 beqz a0, common_errNullObject # yes, bail 2312 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2313 .if 2 2314 EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width 2315 .else 2316 addu a0, a0, a1 2317 .endif 2318 # a1 >= a3; compare unsigned index 2319 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2320 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2321 lw a2, offArrayObject_contents(a0) # a2 <- vBB[vCC] 2322 GET_INST_OPCODE(t0) # extract opcode from rINST 2323 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2324 2325 2326 /* ------------------------------ */ 2327 .balign 128 2328 .L_OP_AGET_WIDE: /* 0x45 */ 2329 /* File: mips/OP_AGET_WIDE.S */ 2330 /* 2331 * Array get, 64 bits. vAA <- vBB[vCC]. 2332 * 2333 * Arrays of long/double are 64-bit aligned. 2334 */ 2335 /* aget-wide vAA, vBB, vCC */ 2336 FETCH(a0, 1) # a0 <- CCBB 2337 GET_OPA(rOBJ) # rOBJ <- AA 2338 and a2, a0, 255 # a2 <- BB 2339 srl a3, a0, 8 # a3 <- CC 2340 GET_VREG(a0, a2) # a0 <- vBB (array object) 2341 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2342 # null array object? 2343 beqz a0, common_errNullObject # yes, bail 2344 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2345 EAS3(a0, a0, a1) # a0 <- arrayObj + index*width 2346 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2347 2348 .LOP_AGET_WIDE_finish: 2349 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2350 LOAD64_off(a2, a3, a0, offArrayObject_contents) 2351 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[AA] 2352 GET_INST_OPCODE(t0) # extract opcode from rINST 2353 STORE64(a2, a3, rOBJ) # vAA/vAA+1 <- a2/a3 2354 GOTO_OPCODE(t0) # jump to next instruction 2355 2356 2357 /* ------------------------------ */ 2358 .balign 128 2359 .L_OP_AGET_OBJECT: /* 0x46 */ 2360 /* File: mips/OP_AGET_OBJECT.S */ 2361 /* File: mips/OP_AGET.S */ 2362 /* 2363 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2364 * 2365 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2366 * instructions. We use a pair of FETCH_Bs instead. 2367 * 2368 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2369 */ 2370 /* op vAA, vBB, vCC */ 2371 FETCH_B(a2, 1) # a2 <- BB 2372 GET_OPA(rOBJ) # rOBJ <- AA 2373 FETCH_C(a3, 1) # a3 <- CC 2374 GET_VREG(a0, a2) # a0 <- vBB (array object) 2375 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2376 # null array object? 2377 beqz a0, common_errNullObject # yes, bail 2378 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2379 .if 2 2380 EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width 2381 .else 2382 addu a0, a0, a1 2383 .endif 2384 # a1 >= a3; compare unsigned index 2385 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2386 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2387 lw a2, offArrayObject_contents(a0) # a2 <- vBB[vCC] 2388 GET_INST_OPCODE(t0) # extract opcode from rINST 2389 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2390 2391 2392 2393 /* ------------------------------ */ 2394 .balign 128 2395 .L_OP_AGET_BOOLEAN: /* 0x47 */ 2396 /* File: mips/OP_AGET_BOOLEAN.S */ 2397 /* File: mips/OP_AGET.S */ 2398 /* 2399 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2400 * 2401 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2402 * instructions. We use a pair of FETCH_Bs instead. 2403 * 2404 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2405 */ 2406 /* op vAA, vBB, vCC */ 2407 FETCH_B(a2, 1) # a2 <- BB 2408 GET_OPA(rOBJ) # rOBJ <- AA 2409 FETCH_C(a3, 1) # a3 <- CC 2410 GET_VREG(a0, a2) # a0 <- vBB (array object) 2411 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2412 # null array object? 2413 beqz a0, common_errNullObject # yes, bail 2414 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2415 .if 0 2416 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2417 .else 2418 addu a0, a0, a1 2419 .endif 2420 # a1 >= a3; compare unsigned index 2421 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2422 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2423 lbu a2, offArrayObject_contents(a0) # a2 <- vBB[vCC] 2424 GET_INST_OPCODE(t0) # extract opcode from rINST 2425 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2426 2427 2428 2429 /* ------------------------------ */ 2430 .balign 128 2431 .L_OP_AGET_BYTE: /* 0x48 */ 2432 /* File: mips/OP_AGET_BYTE.S */ 2433 /* File: mips/OP_AGET.S */ 2434 /* 2435 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2436 * 2437 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2438 * instructions. We use a pair of FETCH_Bs instead. 2439 * 2440 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2441 */ 2442 /* op vAA, vBB, vCC */ 2443 FETCH_B(a2, 1) # a2 <- BB 2444 GET_OPA(rOBJ) # rOBJ <- AA 2445 FETCH_C(a3, 1) # a3 <- CC 2446 GET_VREG(a0, a2) # a0 <- vBB (array object) 2447 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2448 # null array object? 2449 beqz a0, common_errNullObject # yes, bail 2450 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2451 .if 0 2452 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2453 .else 2454 addu a0, a0, a1 2455 .endif 2456 # a1 >= a3; compare unsigned index 2457 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2458 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2459 lb a2, offArrayObject_contents(a0) # a2 <- vBB[vCC] 2460 GET_INST_OPCODE(t0) # extract opcode from rINST 2461 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2462 2463 2464 2465 /* ------------------------------ */ 2466 .balign 128 2467 .L_OP_AGET_CHAR: /* 0x49 */ 2468 /* File: mips/OP_AGET_CHAR.S */ 2469 /* File: mips/OP_AGET.S */ 2470 /* 2471 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2472 * 2473 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2474 * instructions. We use a pair of FETCH_Bs instead. 2475 * 2476 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2477 */ 2478 /* op vAA, vBB, vCC */ 2479 FETCH_B(a2, 1) # a2 <- BB 2480 GET_OPA(rOBJ) # rOBJ <- AA 2481 FETCH_C(a3, 1) # a3 <- CC 2482 GET_VREG(a0, a2) # a0 <- vBB (array object) 2483 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2484 # null array object? 2485 beqz a0, common_errNullObject # yes, bail 2486 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2487 .if 1 2488 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2489 .else 2490 addu a0, a0, a1 2491 .endif 2492 # a1 >= a3; compare unsigned index 2493 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2494 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2495 lhu a2, offArrayObject_contents(a0) # a2 <- vBB[vCC] 2496 GET_INST_OPCODE(t0) # extract opcode from rINST 2497 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2498 2499 2500 2501 /* ------------------------------ */ 2502 .balign 128 2503 .L_OP_AGET_SHORT: /* 0x4a */ 2504 /* File: mips/OP_AGET_SHORT.S */ 2505 /* File: mips/OP_AGET.S */ 2506 /* 2507 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2508 * 2509 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2510 * instructions. We use a pair of FETCH_Bs instead. 2511 * 2512 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2513 */ 2514 /* op vAA, vBB, vCC */ 2515 FETCH_B(a2, 1) # a2 <- BB 2516 GET_OPA(rOBJ) # rOBJ <- AA 2517 FETCH_C(a3, 1) # a3 <- CC 2518 GET_VREG(a0, a2) # a0 <- vBB (array object) 2519 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2520 # null array object? 2521 beqz a0, common_errNullObject # yes, bail 2522 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2523 .if 1 2524 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2525 .else 2526 addu a0, a0, a1 2527 .endif 2528 # a1 >= a3; compare unsigned index 2529 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2530 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2531 lh a2, offArrayObject_contents(a0) # a2 <- vBB[vCC] 2532 GET_INST_OPCODE(t0) # extract opcode from rINST 2533 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2534 2535 2536 2537 /* ------------------------------ */ 2538 .balign 128 2539 .L_OP_APUT: /* 0x4b */ 2540 /* File: mips/OP_APUT.S */ 2541 /* 2542 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2543 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2544 */ 2545 /* op vAA, vBB, vCC */ 2546 FETCH_B(a2, 1) # a2 <- BB 2547 GET_OPA(rOBJ) # rOBJ <- AA 2548 FETCH_C(a3, 1) # a3 <- CC 2549 GET_VREG(a0, a2) # a0 <- vBB (array object) 2550 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2551 # null array object? 2552 beqz a0, common_errNullObject # yes, bail 2553 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2554 .if 2 2555 EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width 2556 .else 2557 addu a0, a0, a1 2558 .endif 2559 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2560 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2561 GET_VREG(a2, rOBJ) # a2 <- vAA 2562 GET_INST_OPCODE(t0) # extract opcode from rINST 2563 sw a2, offArrayObject_contents(a0) # vBB[vCC] <- a2 2564 GOTO_OPCODE(t0) # jump to next instruction 2565 2566 2567 /* ------------------------------ */ 2568 .balign 128 2569 .L_OP_APUT_WIDE: /* 0x4c */ 2570 /* File: mips/OP_APUT_WIDE.S */ 2571 /* 2572 * Array put, 64 bits. vBB[vCC] <- vAA. 2573 * 2574 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2575 */ 2576 /* aput-wide vAA, vBB, vCC */ 2577 FETCH(a0, 1) # a0 <- CCBB 2578 GET_OPA(t0) # t0 <- AA 2579 and a2, a0, 255 # a2 <- BB 2580 srl a3, a0, 8 # a3 <- CC 2581 GET_VREG(a0, a2) # a0 <- vBB (array object) 2582 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2583 # null array object? 2584 beqz a0, common_errNullObject # yes, bail 2585 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2586 EAS3(a0, a0, a1) # a0 <- arrayObj + index*width 2587 EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA] 2588 # compare unsigned index, length 2589 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2590 2591 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2592 LOAD64(a2, a3, rOBJ) # a2/a3 <- vAA/vAA+1 2593 GET_INST_OPCODE(t0) # extract opcode from rINST 2594 STORE64_off(a2, a3, a0, offArrayObject_contents) # a2/a3 <- vBB[vCC] 2595 GOTO_OPCODE(t0) # jump to next instruction 2596 2597 2598 /* ------------------------------ */ 2599 .balign 128 2600 .L_OP_APUT_OBJECT: /* 0x4d */ 2601 /* File: mips/OP_APUT_OBJECT.S */ 2602 /* 2603 * Store an object into an array. vBB[vCC] <- vAA. 2604 * 2605 */ 2606 /* op vAA, vBB, vCC */ 2607 FETCH(a0, 1) # a0 <- CCBB 2608 GET_OPA(t1) # t1 <- AA 2609 and a2, a0, 255 # a2 <- BB 2610 srl a3, a0, 8 # a3 <- CC 2611 GET_VREG(rINST, a2) # rINST <- vBB (array object) 2612 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2613 GET_VREG(rBIX, t1) # rBIX <- vAA 2614 # null array object? 2615 beqz rINST, common_errNullObject # yes, bail 2616 2617 LOAD_base_offArrayObject_length(a3, rINST) # a3 <- arrayObj->length 2618 EAS2(rOBJ, rINST, a1) # rOBJ <- arrayObj + index*width 2619 # compare unsigned index, length 2620 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2621 /* 2622 * On entry: 2623 * rINST = vBB (arrayObj) 2624 * rBIX = vAA (obj) 2625 * rOBJ = offset into array (vBB + vCC * width) 2626 */ 2627 bnez rBIX, .LOP_APUT_OBJECT_checks # yes, skip type checks 2628 .LOP_APUT_OBJECT_finish: 2629 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2630 GET_INST_OPCODE(t0) # extract opcode from rINST 2631 sw rBIX, offArrayObject_contents(rOBJ) # vBB[vCC] <- vAA 2632 GOTO_OPCODE(t0) # jump to next instruction 2633 2634 2635 /* ------------------------------ */ 2636 .balign 128 2637 .L_OP_APUT_BOOLEAN: /* 0x4e */ 2638 /* File: mips/OP_APUT_BOOLEAN.S */ 2639 /* File: mips/OP_APUT.S */ 2640 /* 2641 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2642 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2643 */ 2644 /* op vAA, vBB, vCC */ 2645 FETCH_B(a2, 1) # a2 <- BB 2646 GET_OPA(rOBJ) # rOBJ <- AA 2647 FETCH_C(a3, 1) # a3 <- CC 2648 GET_VREG(a0, a2) # a0 <- vBB (array object) 2649 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2650 # null array object? 2651 beqz a0, common_errNullObject # yes, bail 2652 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2653 .if 0 2654 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2655 .else 2656 addu a0, a0, a1 2657 .endif 2658 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2659 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2660 GET_VREG(a2, rOBJ) # a2 <- vAA 2661 GET_INST_OPCODE(t0) # extract opcode from rINST 2662 sb a2, offArrayObject_contents(a0) # vBB[vCC] <- a2 2663 GOTO_OPCODE(t0) # jump to next instruction 2664 2665 2666 2667 /* ------------------------------ */ 2668 .balign 128 2669 .L_OP_APUT_BYTE: /* 0x4f */ 2670 /* File: mips/OP_APUT_BYTE.S */ 2671 /* File: mips/OP_APUT.S */ 2672 /* 2673 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2674 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2675 */ 2676 /* op vAA, vBB, vCC */ 2677 FETCH_B(a2, 1) # a2 <- BB 2678 GET_OPA(rOBJ) # rOBJ <- AA 2679 FETCH_C(a3, 1) # a3 <- CC 2680 GET_VREG(a0, a2) # a0 <- vBB (array object) 2681 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2682 # null array object? 2683 beqz a0, common_errNullObject # yes, bail 2684 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2685 .if 0 2686 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2687 .else 2688 addu a0, a0, a1 2689 .endif 2690 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2691 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2692 GET_VREG(a2, rOBJ) # a2 <- vAA 2693 GET_INST_OPCODE(t0) # extract opcode from rINST 2694 sb a2, offArrayObject_contents(a0) # vBB[vCC] <- a2 2695 GOTO_OPCODE(t0) # jump to next instruction 2696 2697 2698 2699 /* ------------------------------ */ 2700 .balign 128 2701 .L_OP_APUT_CHAR: /* 0x50 */ 2702 /* File: mips/OP_APUT_CHAR.S */ 2703 /* File: mips/OP_APUT.S */ 2704 /* 2705 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2706 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2707 */ 2708 /* op vAA, vBB, vCC */ 2709 FETCH_B(a2, 1) # a2 <- BB 2710 GET_OPA(rOBJ) # rOBJ <- AA 2711 FETCH_C(a3, 1) # a3 <- CC 2712 GET_VREG(a0, a2) # a0 <- vBB (array object) 2713 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2714 # null array object? 2715 beqz a0, common_errNullObject # yes, bail 2716 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2717 .if 1 2718 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2719 .else 2720 addu a0, a0, a1 2721 .endif 2722 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2723 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2724 GET_VREG(a2, rOBJ) # a2 <- vAA 2725 GET_INST_OPCODE(t0) # extract opcode from rINST 2726 sh a2, offArrayObject_contents(a0) # vBB[vCC] <- a2 2727 GOTO_OPCODE(t0) # jump to next instruction 2728 2729 2730 2731 /* ------------------------------ */ 2732 .balign 128 2733 .L_OP_APUT_SHORT: /* 0x51 */ 2734 /* File: mips/OP_APUT_SHORT.S */ 2735 /* File: mips/OP_APUT.S */ 2736 /* 2737 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2738 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2739 */ 2740 /* op vAA, vBB, vCC */ 2741 FETCH_B(a2, 1) # a2 <- BB 2742 GET_OPA(rOBJ) # rOBJ <- AA 2743 FETCH_C(a3, 1) # a3 <- CC 2744 GET_VREG(a0, a2) # a0 <- vBB (array object) 2745 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2746 # null array object? 2747 beqz a0, common_errNullObject # yes, bail 2748 LOAD_base_offArrayObject_length(a3, a0) # a3 <- arrayObj->length 2749 .if 1 2750 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2751 .else 2752 addu a0, a0, a1 2753 .endif 2754 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2755 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2756 GET_VREG(a2, rOBJ) # a2 <- vAA 2757 GET_INST_OPCODE(t0) # extract opcode from rINST 2758 sh a2, offArrayObject_contents(a0) # vBB[vCC] <- a2 2759 GOTO_OPCODE(t0) # jump to next instruction 2760 2761 2762 2763 /* ------------------------------ */ 2764 .balign 128 2765 .L_OP_IGET: /* 0x52 */ 2766 /* File: mips/OP_IGET.S */ 2767 /* 2768 * General 32-bit instance field get. 2769 * 2770 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2771 */ 2772 # op vA, vB, field /* CCCC */ 2773 GET_OPB(a0) # a0 <- B 2774 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 2775 FETCH(a1, 1) # a1 <- field ref CCCC 2776 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 2777 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 2778 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 2779 # is resolved entry null? 2780 bnez a0, .LOP_IGET_finish # no, already resolved 2781 LOAD_rSELF_method(a2) # a2 <- current method 2782 EXPORT_PC() # resolve() could throw 2783 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 2784 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 2785 # test results 2786 move a0, v0 2787 bnez v0, .LOP_IGET_finish 2788 b common_exceptionThrown 2789 2790 /* ------------------------------ */ 2791 .balign 128 2792 .L_OP_IGET_WIDE: /* 0x53 */ 2793 /* File: mips/OP_IGET_WIDE.S */ 2794 /* 2795 * Wide 32-bit instance field get. 2796 */ 2797 # iget-wide vA, vB, field /* CCCC */ 2798 GET_OPB(a0) # a0 <- B 2799 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 2800 FETCH(a1, 1) # a1 <- field ref CCCC 2801 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pResFields 2802 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 2803 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 2804 # is resolved entry null? 2805 bnez a0, .LOP_IGET_WIDE_finish # no, already resolved 2806 LOAD_rSELF_method(a2) # a2 <- current method 2807 EXPORT_PC() # resolve() could throw 2808 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 2809 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 2810 # test return code 2811 move a0, v0 2812 bnez v0, .LOP_IGET_WIDE_finish 2813 b common_exceptionThrown 2814 2815 /* ------------------------------ */ 2816 .balign 128 2817 .L_OP_IGET_OBJECT: /* 0x54 */ 2818 /* File: mips/OP_IGET_OBJECT.S */ 2819 /* File: mips/OP_IGET.S */ 2820 /* 2821 * General 32-bit instance field get. 2822 * 2823 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2824 */ 2825 # op vA, vB, field /* CCCC */ 2826 GET_OPB(a0) # a0 <- B 2827 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 2828 FETCH(a1, 1) # a1 <- field ref CCCC 2829 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 2830 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 2831 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 2832 # is resolved entry null? 2833 bnez a0, .LOP_IGET_OBJECT_finish # no, already resolved 2834 LOAD_rSELF_method(a2) # a2 <- current method 2835 EXPORT_PC() # resolve() could throw 2836 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 2837 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 2838 # test results 2839 move a0, v0 2840 bnez v0, .LOP_IGET_OBJECT_finish 2841 b common_exceptionThrown 2842 2843 2844 /* ------------------------------ */ 2845 .balign 128 2846 .L_OP_IGET_BOOLEAN: /* 0x55 */ 2847 /* File: mips/OP_IGET_BOOLEAN.S */ 2848 /* File: mips/OP_IGET.S */ 2849 /* 2850 * General 32-bit instance field get. 2851 * 2852 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2853 */ 2854 # op vA, vB, field /* CCCC */ 2855 GET_OPB(a0) # a0 <- B 2856 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 2857 FETCH(a1, 1) # a1 <- field ref CCCC 2858 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 2859 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 2860 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 2861 # is resolved entry null? 2862 bnez a0, .LOP_IGET_BOOLEAN_finish # no, already resolved 2863 LOAD_rSELF_method(a2) # a2 <- current method 2864 EXPORT_PC() # resolve() could throw 2865 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 2866 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 2867 # test results 2868 move a0, v0 2869 bnez v0, .LOP_IGET_BOOLEAN_finish 2870 b common_exceptionThrown 2871 2872 2873 /* ------------------------------ */ 2874 .balign 128 2875 .L_OP_IGET_BYTE: /* 0x56 */ 2876 /* File: mips/OP_IGET_BYTE.S */ 2877 /* File: mips/OP_IGET.S */ 2878 /* 2879 * General 32-bit instance field get. 2880 * 2881 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2882 */ 2883 # op vA, vB, field /* CCCC */ 2884 GET_OPB(a0) # a0 <- B 2885 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 2886 FETCH(a1, 1) # a1 <- field ref CCCC 2887 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 2888 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 2889 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 2890 # is resolved entry null? 2891 bnez a0, .LOP_IGET_BYTE_finish # no, already resolved 2892 LOAD_rSELF_method(a2) # a2 <- current method 2893 EXPORT_PC() # resolve() could throw 2894 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 2895 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 2896 # test results 2897 move a0, v0 2898 bnez v0, .LOP_IGET_BYTE_finish 2899 b common_exceptionThrown 2900 2901 2902 /* ------------------------------ */ 2903 .balign 128 2904 .L_OP_IGET_CHAR: /* 0x57 */ 2905 /* File: mips/OP_IGET_CHAR.S */ 2906 /* File: mips/OP_IGET.S */ 2907 /* 2908 * General 32-bit instance field get. 2909 * 2910 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2911 */ 2912 # op vA, vB, field /* CCCC */ 2913 GET_OPB(a0) # a0 <- B 2914 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 2915 FETCH(a1, 1) # a1 <- field ref CCCC 2916 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 2917 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 2918 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 2919 # is resolved entry null? 2920 bnez a0, .LOP_IGET_CHAR_finish # no, already resolved 2921 LOAD_rSELF_method(a2) # a2 <- current method 2922 EXPORT_PC() # resolve() could throw 2923 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 2924 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 2925 # test results 2926 move a0, v0 2927 bnez v0, .LOP_IGET_CHAR_finish 2928 b common_exceptionThrown 2929 2930 2931 /* ------------------------------ */ 2932 .balign 128 2933 .L_OP_IGET_SHORT: /* 0x58 */ 2934 /* File: mips/OP_IGET_SHORT.S */ 2935 /* File: mips/OP_IGET.S */ 2936 /* 2937 * General 32-bit instance field get. 2938 * 2939 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2940 */ 2941 # op vA, vB, field /* CCCC */ 2942 GET_OPB(a0) # a0 <- B 2943 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 2944 FETCH(a1, 1) # a1 <- field ref CCCC 2945 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 2946 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 2947 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 2948 # is resolved entry null? 2949 bnez a0, .LOP_IGET_SHORT_finish # no, already resolved 2950 LOAD_rSELF_method(a2) # a2 <- current method 2951 EXPORT_PC() # resolve() could throw 2952 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 2953 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 2954 # test results 2955 move a0, v0 2956 bnez v0, .LOP_IGET_SHORT_finish 2957 b common_exceptionThrown 2958 2959 2960 /* ------------------------------ */ 2961 .balign 128 2962 .L_OP_IPUT: /* 0x59 */ 2963 /* File: mips/OP_IPUT.S */ 2964 /* 2965 * General 32-bit instance field put. 2966 * 2967 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2968 */ 2969 # op vA, vB, field /* CCCC */ 2970 GET_OPB(a0) # a0 <- B 2971 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 2972 FETCH(a1, 1) # a1 <- field ref CCCC 2973 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 2974 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 2975 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 2976 # is resolved entry null? 2977 bnez a0, .LOP_IPUT_finish # no, already resolved 2978 LOAD_rSELF_method(a2) # a2 <- current method 2979 EXPORT_PC() # resolve() could throw 2980 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 2981 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 2982 # success? 2983 move a0, v0 2984 bnez v0, .LOP_IPUT_finish # yes, finish up 2985 b common_exceptionThrown 2986 2987 /* ------------------------------ */ 2988 .balign 128 2989 .L_OP_IPUT_WIDE: /* 0x5a */ 2990 /* File: mips/OP_IPUT_WIDE.S */ 2991 # iput-wide vA, vB, field /* CCCC */ 2992 GET_OPB(a0) # a0 <- B 2993 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 2994 FETCH(a1, 1) # a1 <- field ref CCCC 2995 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pResFields 2996 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 2997 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 2998 # is resolved entry null? 2999 bnez a0, .LOP_IPUT_WIDE_finish # no, already resolved 3000 LOAD_rSELF_method(a2) # a2 <- current method 3001 EXPORT_PC() # resolve() could throw 3002 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3003 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 3004 # success? 3005 move a0, v0 3006 bnez v0, .LOP_IPUT_WIDE_finish # yes, finish up 3007 b common_exceptionThrown 3008 3009 /* ------------------------------ */ 3010 .balign 128 3011 .L_OP_IPUT_OBJECT: /* 0x5b */ 3012 /* File: mips/OP_IPUT_OBJECT.S */ 3013 /* 3014 * 32-bit instance field put. 3015 * 3016 * for: iput-object, iput-object-volatile 3017 */ 3018 # op vA, vB, field /* CCCC */ 3019 GET_OPB(a0) # a0 <- B 3020 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 3021 FETCH(a1, 1) # a1 <- field ref CCCC 3022 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 3023 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 3024 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 3025 # is resolved entry null? 3026 bnez a0, .LOP_IPUT_OBJECT_finish # no, already resolved 3027 LOAD_rSELF_method(a2) # a2 <- current method 3028 EXPORT_PC() # resolve() could throw 3029 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3030 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 3031 # success? 3032 move a0, v0 3033 bnez v0, .LOP_IPUT_OBJECT_finish # yes, finish up 3034 b common_exceptionThrown 3035 3036 /* ------------------------------ */ 3037 .balign 128 3038 .L_OP_IPUT_BOOLEAN: /* 0x5c */ 3039 /* File: mips/OP_IPUT_BOOLEAN.S */ 3040 /* File: mips/OP_IPUT.S */ 3041 /* 3042 * General 32-bit instance field put. 3043 * 3044 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 3045 */ 3046 # op vA, vB, field /* CCCC */ 3047 GET_OPB(a0) # a0 <- B 3048 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 3049 FETCH(a1, 1) # a1 <- field ref CCCC 3050 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 3051 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 3052 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 3053 # is resolved entry null? 3054 bnez a0, .LOP_IPUT_BOOLEAN_finish # no, already resolved 3055 LOAD_rSELF_method(a2) # a2 <- current method 3056 EXPORT_PC() # resolve() could throw 3057 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3058 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 3059 # success? 3060 move a0, v0 3061 bnez v0, .LOP_IPUT_BOOLEAN_finish # yes, finish up 3062 b common_exceptionThrown 3063 3064 3065 /* ------------------------------ */ 3066 .balign 128 3067 .L_OP_IPUT_BYTE: /* 0x5d */ 3068 /* File: mips/OP_IPUT_BYTE.S */ 3069 /* File: mips/OP_IPUT.S */ 3070 /* 3071 * General 32-bit instance field put. 3072 * 3073 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 3074 */ 3075 # op vA, vB, field /* CCCC */ 3076 GET_OPB(a0) # a0 <- B 3077 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 3078 FETCH(a1, 1) # a1 <- field ref CCCC 3079 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 3080 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 3081 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 3082 # is resolved entry null? 3083 bnez a0, .LOP_IPUT_BYTE_finish # no, already resolved 3084 LOAD_rSELF_method(a2) # a2 <- current method 3085 EXPORT_PC() # resolve() could throw 3086 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3087 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 3088 # success? 3089 move a0, v0 3090 bnez v0, .LOP_IPUT_BYTE_finish # yes, finish up 3091 b common_exceptionThrown 3092 3093 3094 /* ------------------------------ */ 3095 .balign 128 3096 .L_OP_IPUT_CHAR: /* 0x5e */ 3097 /* File: mips/OP_IPUT_CHAR.S */ 3098 /* File: mips/OP_IPUT.S */ 3099 /* 3100 * General 32-bit instance field put. 3101 * 3102 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 3103 */ 3104 # op vA, vB, field /* CCCC */ 3105 GET_OPB(a0) # a0 <- B 3106 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 3107 FETCH(a1, 1) # a1 <- field ref CCCC 3108 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 3109 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 3110 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 3111 # is resolved entry null? 3112 bnez a0, .LOP_IPUT_CHAR_finish # no, already resolved 3113 LOAD_rSELF_method(a2) # a2 <- current method 3114 EXPORT_PC() # resolve() could throw 3115 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3116 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 3117 # success? 3118 move a0, v0 3119 bnez v0, .LOP_IPUT_CHAR_finish # yes, finish up 3120 b common_exceptionThrown 3121 3122 3123 /* ------------------------------ */ 3124 .balign 128 3125 .L_OP_IPUT_SHORT: /* 0x5f */ 3126 /* File: mips/OP_IPUT_SHORT.S */ 3127 /* File: mips/OP_IPUT.S */ 3128 /* 3129 * General 32-bit instance field put. 3130 * 3131 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 3132 */ 3133 # op vA, vB, field /* CCCC */ 3134 GET_OPB(a0) # a0 <- B 3135 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 3136 FETCH(a1, 1) # a1 <- field ref CCCC 3137 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 3138 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 3139 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 3140 # is resolved entry null? 3141 bnez a0, .LOP_IPUT_SHORT_finish # no, already resolved 3142 LOAD_rSELF_method(a2) # a2 <- current method 3143 EXPORT_PC() # resolve() could throw 3144 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3145 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 3146 # success? 3147 move a0, v0 3148 bnez v0, .LOP_IPUT_SHORT_finish # yes, finish up 3149 b common_exceptionThrown 3150 3151 3152 /* ------------------------------ */ 3153 .balign 128 3154 .L_OP_SGET: /* 0x60 */ 3155 /* File: mips/OP_SGET.S */ 3156 /* 3157 * General 32-bit SGET handler. 3158 * 3159 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3160 */ 3161 # op vAA, field /* BBBB */ 3162 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3163 FETCH(a1, 1) # a1 <- field ref BBBB 3164 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3165 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3166 # is resolved entry !null? 3167 bnez a0, .LOP_SGET_finish 3168 3169 /* 3170 * Continuation if the field has not yet been resolved. 3171 * a1: BBBB field ref 3172 * rBIX: dvmDex->pResFields 3173 */ 3174 LOAD_rSELF_method(a2) # a2 <- current method 3175 #if defined(WITH_JIT) 3176 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3177 #endif 3178 EXPORT_PC() # resolve() could throw, so export now 3179 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3180 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3181 move a0, v0 3182 # success? 3183 beqz v0, common_exceptionThrown # no, handle exception 3184 #if defined(WITH_JIT) 3185 /* 3186 * If the JIT is actively building a trace we need to make sure 3187 * that the field is fully resolved before including this instruction. 3188 */ 3189 JAL(common_verifyField) 3190 #endif 3191 b .LOP_SGET_finish # resume 3192 3193 /* ------------------------------ */ 3194 .balign 128 3195 .L_OP_SGET_WIDE: /* 0x61 */ 3196 /* File: mips/OP_SGET_WIDE.S */ 3197 /* 3198 * 64-bit SGET handler. 3199 */ 3200 # sget-wide vAA, field /* BBBB */ 3201 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3202 FETCH(a1, 1) # a1 <- field ref BBBB 3203 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3204 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3205 # is resolved entry null? 3206 bnez a0, .LOP_SGET_WIDE_finish 3207 3208 /* 3209 * Continuation if the field has not yet been resolved. 3210 * a1: BBBB field ref 3211 * rBIX: dvmDex->pResFields 3212 * 3213 * Returns StaticField pointer in v0. 3214 */ 3215 LOAD_rSELF_method(a2) # a2 <- current method 3216 #if defined(WITH_JIT) 3217 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3218 #endif 3219 EXPORT_PC() # resolve() could throw, so export now 3220 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3221 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3222 move a0, v0 3223 # success? 3224 beqz v0, common_exceptionThrown # no, handle exception 3225 #if defined(WITH_JIT) 3226 /* 3227 * If the JIT is actively building a trace we need to make sure 3228 * that the field is fully resolved before including this instruction. 3229 */ 3230 JAL(common_verifyField) 3231 #endif 3232 3233 b .LOP_SGET_WIDE_finish # resume 3234 3235 /* ------------------------------ */ 3236 .balign 128 3237 .L_OP_SGET_OBJECT: /* 0x62 */ 3238 /* File: mips/OP_SGET_OBJECT.S */ 3239 /* File: mips/OP_SGET.S */ 3240 /* 3241 * General 32-bit SGET handler. 3242 * 3243 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3244 */ 3245 # op vAA, field /* BBBB */ 3246 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3247 FETCH(a1, 1) # a1 <- field ref BBBB 3248 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3249 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3250 # is resolved entry !null? 3251 bnez a0, .LOP_SGET_OBJECT_finish 3252 3253 /* 3254 * Continuation if the field has not yet been resolved. 3255 * a1: BBBB field ref 3256 * rBIX: dvmDex->pResFields 3257 */ 3258 LOAD_rSELF_method(a2) # a2 <- current method 3259 #if defined(WITH_JIT) 3260 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3261 #endif 3262 EXPORT_PC() # resolve() could throw, so export now 3263 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3264 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3265 move a0, v0 3266 # success? 3267 beqz v0, common_exceptionThrown # no, handle exception 3268 #if defined(WITH_JIT) 3269 /* 3270 * If the JIT is actively building a trace we need to make sure 3271 * that the field is fully resolved before including this instruction. 3272 */ 3273 JAL(common_verifyField) 3274 #endif 3275 b .LOP_SGET_OBJECT_finish # resume 3276 3277 3278 /* ------------------------------ */ 3279 .balign 128 3280 .L_OP_SGET_BOOLEAN: /* 0x63 */ 3281 /* File: mips/OP_SGET_BOOLEAN.S */ 3282 /* File: mips/OP_SGET.S */ 3283 /* 3284 * General 32-bit SGET handler. 3285 * 3286 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3287 */ 3288 # op vAA, field /* BBBB */ 3289 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3290 FETCH(a1, 1) # a1 <- field ref BBBB 3291 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3292 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3293 # is resolved entry !null? 3294 bnez a0, .LOP_SGET_BOOLEAN_finish 3295 3296 /* 3297 * Continuation if the field has not yet been resolved. 3298 * a1: BBBB field ref 3299 * rBIX: dvmDex->pResFields 3300 */ 3301 LOAD_rSELF_method(a2) # a2 <- current method 3302 #if defined(WITH_JIT) 3303 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3304 #endif 3305 EXPORT_PC() # resolve() could throw, so export now 3306 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3307 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3308 move a0, v0 3309 # success? 3310 beqz v0, common_exceptionThrown # no, handle exception 3311 #if defined(WITH_JIT) 3312 /* 3313 * If the JIT is actively building a trace we need to make sure 3314 * that the field is fully resolved before including this instruction. 3315 */ 3316 JAL(common_verifyField) 3317 #endif 3318 b .LOP_SGET_BOOLEAN_finish # resume 3319 3320 3321 /* ------------------------------ */ 3322 .balign 128 3323 .L_OP_SGET_BYTE: /* 0x64 */ 3324 /* File: mips/OP_SGET_BYTE.S */ 3325 /* File: mips/OP_SGET.S */ 3326 /* 3327 * General 32-bit SGET handler. 3328 * 3329 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3330 */ 3331 # op vAA, field /* BBBB */ 3332 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3333 FETCH(a1, 1) # a1 <- field ref BBBB 3334 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3335 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3336 # is resolved entry !null? 3337 bnez a0, .LOP_SGET_BYTE_finish 3338 3339 /* 3340 * Continuation if the field has not yet been resolved. 3341 * a1: BBBB field ref 3342 * rBIX: dvmDex->pResFields 3343 */ 3344 LOAD_rSELF_method(a2) # a2 <- current method 3345 #if defined(WITH_JIT) 3346 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3347 #endif 3348 EXPORT_PC() # resolve() could throw, so export now 3349 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3350 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3351 move a0, v0 3352 # success? 3353 beqz v0, common_exceptionThrown # no, handle exception 3354 #if defined(WITH_JIT) 3355 /* 3356 * If the JIT is actively building a trace we need to make sure 3357 * that the field is fully resolved before including this instruction. 3358 */ 3359 JAL(common_verifyField) 3360 #endif 3361 b .LOP_SGET_BYTE_finish # resume 3362 3363 3364 /* ------------------------------ */ 3365 .balign 128 3366 .L_OP_SGET_CHAR: /* 0x65 */ 3367 /* File: mips/OP_SGET_CHAR.S */ 3368 /* File: mips/OP_SGET.S */ 3369 /* 3370 * General 32-bit SGET handler. 3371 * 3372 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3373 */ 3374 # op vAA, field /* BBBB */ 3375 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3376 FETCH(a1, 1) # a1 <- field ref BBBB 3377 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3378 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3379 # is resolved entry !null? 3380 bnez a0, .LOP_SGET_CHAR_finish 3381 3382 /* 3383 * Continuation if the field has not yet been resolved. 3384 * a1: BBBB field ref 3385 * rBIX: dvmDex->pResFields 3386 */ 3387 LOAD_rSELF_method(a2) # a2 <- current method 3388 #if defined(WITH_JIT) 3389 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3390 #endif 3391 EXPORT_PC() # resolve() could throw, so export now 3392 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3393 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3394 move a0, v0 3395 # success? 3396 beqz v0, common_exceptionThrown # no, handle exception 3397 #if defined(WITH_JIT) 3398 /* 3399 * If the JIT is actively building a trace we need to make sure 3400 * that the field is fully resolved before including this instruction. 3401 */ 3402 JAL(common_verifyField) 3403 #endif 3404 b .LOP_SGET_CHAR_finish # resume 3405 3406 3407 /* ------------------------------ */ 3408 .balign 128 3409 .L_OP_SGET_SHORT: /* 0x66 */ 3410 /* File: mips/OP_SGET_SHORT.S */ 3411 /* File: mips/OP_SGET.S */ 3412 /* 3413 * General 32-bit SGET handler. 3414 * 3415 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3416 */ 3417 # op vAA, field /* BBBB */ 3418 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3419 FETCH(a1, 1) # a1 <- field ref BBBB 3420 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3421 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3422 # is resolved entry !null? 3423 bnez a0, .LOP_SGET_SHORT_finish 3424 3425 /* 3426 * Continuation if the field has not yet been resolved. 3427 * a1: BBBB field ref 3428 * rBIX: dvmDex->pResFields 3429 */ 3430 LOAD_rSELF_method(a2) # a2 <- current method 3431 #if defined(WITH_JIT) 3432 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3433 #endif 3434 EXPORT_PC() # resolve() could throw, so export now 3435 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3436 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3437 move a0, v0 3438 # success? 3439 beqz v0, common_exceptionThrown # no, handle exception 3440 #if defined(WITH_JIT) 3441 /* 3442 * If the JIT is actively building a trace we need to make sure 3443 * that the field is fully resolved before including this instruction. 3444 */ 3445 JAL(common_verifyField) 3446 #endif 3447 b .LOP_SGET_SHORT_finish # resume 3448 3449 3450 /* ------------------------------ */ 3451 .balign 128 3452 .L_OP_SPUT: /* 0x67 */ 3453 /* File: mips/OP_SPUT.S */ 3454 /* 3455 * General 32-bit SPUT handler. 3456 * 3457 * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3458 */ 3459 # op vAA, field /* BBBB */ 3460 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3461 FETCH(a1, 1) # a1 <- field ref BBBB 3462 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3463 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3464 bnez a0, .LOP_SPUT_finish # is resolved entry null? 3465 /* 3466 * Continuation if the field has not yet been resolved. 3467 * a1: BBBB field ref 3468 * rBIX: dvmDex->pResFields 3469 */ 3470 LOAD_rSELF_method(a2) # a2 <- current method 3471 #if defined(WITH_JIT) 3472 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3473 #endif 3474 EXPORT_PC() # resolve() may throw, so export now 3475 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3476 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3477 move a0, v0 3478 beqz v0, common_exceptionThrown # success? no, handle exception 3479 #if defined(WITH_JIT) 3480 /* 3481 * If the JIT is actively building a trace we need to make sure 3482 * that the field is fully resolved before including this instruction. 3483 */ 3484 JAL(common_verifyField) 3485 #endif 3486 b .LOP_SPUT_finish # resume 3487 3488 /* ------------------------------ */ 3489 .balign 128 3490 .L_OP_SPUT_WIDE: /* 0x68 */ 3491 /* File: mips/OP_SPUT_WIDE.S */ 3492 /* 3493 * 64-bit SPUT handler. 3494 */ 3495 # sput-wide vAA, field /* BBBB */ 3496 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3497 FETCH(a1, 1) # a1 <- field ref BBBB 3498 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3499 GET_OPA(t0) # t0 <- AA 3500 LOAD_eas2(a2, rBIX, a1) # a2 <- resolved StaticField ptr 3501 EAS2(rOBJ, rFP, t0) # rOBJ<- &fp[AA] 3502 # is resolved entry null? 3503 beqz a2, .LOP_SPUT_WIDE_resolve # yes, do resolve 3504 .LOP_SPUT_WIDE_finish: # field ptr in a2, AA in rOBJ 3505 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 3506 LOAD64(a0, a1, rOBJ) # a0/a1 <- vAA/vAA+1 3507 GET_INST_OPCODE(rBIX) # extract opcode from rINST 3508 .if 0 3509 addu a2, offStaticField_value # a2<- pointer to data 3510 JAL(dvmQuasiAtomicSwap64Sync) # stores a0/a1 into addr a2 3511 .else 3512 STORE64_off(a0, a1, a2, offStaticField_value) # field <- vAA/vAA+1 3513 .endif 3514 GOTO_OPCODE(rBIX) # jump to next instruction 3515 3516 /* ------------------------------ */ 3517 .balign 128 3518 .L_OP_SPUT_OBJECT: /* 0x69 */ 3519 /* File: mips/OP_SPUT_OBJECT.S */ 3520 /* 3521 * General 32-bit SPUT handler. 3522 * 3523 * for: sput-object, sput-object-volatile 3524 */ 3525 /* op vAA, field@BBBB */ 3526 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3527 FETCH(a1, 1) # a1 <- field ref BBBB 3528 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3529 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3530 bnez a0, .LOP_SPUT_OBJECT_finish # is resolved entry null? 3531 3532 /* Continuation if the field has not yet been resolved. 3533 * a1: BBBB field ref 3534 * rBIX: dvmDex->pResFields 3535 */ 3536 LOAD_rSELF_method(a2) # a2 <- current method 3537 #if defined(WITH_JIT) 3538 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3539 #endif 3540 EXPORT_PC() # resolve() may throw, so export now 3541 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3542 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3543 move a0, v0 3544 beqz v0, common_exceptionThrown # success? no, handle exception 3545 #if defined(WITH_JIT) 3546 /* 3547 * If the JIT is actively building a trace we need to make sure 3548 * that the field is fully resolved before including this instruction. 3549 */ 3550 JAL(common_verifyField) 3551 #endif 3552 b .LOP_SPUT_OBJECT_finish # resume 3553 3554 3555 /* ------------------------------ */ 3556 .balign 128 3557 .L_OP_SPUT_BOOLEAN: /* 0x6a */ 3558 /* File: mips/OP_SPUT_BOOLEAN.S */ 3559 /* File: mips/OP_SPUT.S */ 3560 /* 3561 * General 32-bit SPUT handler. 3562 * 3563 * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3564 */ 3565 # op vAA, field /* BBBB */ 3566 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3567 FETCH(a1, 1) # a1 <- field ref BBBB 3568 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3569 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3570 bnez a0, .LOP_SPUT_BOOLEAN_finish # is resolved entry null? 3571 /* 3572 * Continuation if the field has not yet been resolved. 3573 * a1: BBBB field ref 3574 * rBIX: dvmDex->pResFields 3575 */ 3576 LOAD_rSELF_method(a2) # a2 <- current method 3577 #if defined(WITH_JIT) 3578 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3579 #endif 3580 EXPORT_PC() # resolve() may throw, so export now 3581 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3582 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3583 move a0, v0 3584 beqz v0, common_exceptionThrown # success? no, handle exception 3585 #if defined(WITH_JIT) 3586 /* 3587 * If the JIT is actively building a trace we need to make sure 3588 * that the field is fully resolved before including this instruction. 3589 */ 3590 JAL(common_verifyField) 3591 #endif 3592 b .LOP_SPUT_BOOLEAN_finish # resume 3593 3594 3595 /* ------------------------------ */ 3596 .balign 128 3597 .L_OP_SPUT_BYTE: /* 0x6b */ 3598 /* File: mips/OP_SPUT_BYTE.S */ 3599 /* File: mips/OP_SPUT.S */ 3600 /* 3601 * General 32-bit SPUT handler. 3602 * 3603 * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3604 */ 3605 # op vAA, field /* BBBB */ 3606 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3607 FETCH(a1, 1) # a1 <- field ref BBBB 3608 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3609 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3610 bnez a0, .LOP_SPUT_BYTE_finish # is resolved entry null? 3611 /* 3612 * Continuation if the field has not yet been resolved. 3613 * a1: BBBB field ref 3614 * rBIX: dvmDex->pResFields 3615 */ 3616 LOAD_rSELF_method(a2) # a2 <- current method 3617 #if defined(WITH_JIT) 3618 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3619 #endif 3620 EXPORT_PC() # resolve() may throw, so export now 3621 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3622 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3623 move a0, v0 3624 beqz v0, common_exceptionThrown # success? no, handle exception 3625 #if defined(WITH_JIT) 3626 /* 3627 * If the JIT is actively building a trace we need to make sure 3628 * that the field is fully resolved before including this instruction. 3629 */ 3630 JAL(common_verifyField) 3631 #endif 3632 b .LOP_SPUT_BYTE_finish # resume 3633 3634 3635 /* ------------------------------ */ 3636 .balign 128 3637 .L_OP_SPUT_CHAR: /* 0x6c */ 3638 /* File: mips/OP_SPUT_CHAR.S */ 3639 /* File: mips/OP_SPUT.S */ 3640 /* 3641 * General 32-bit SPUT handler. 3642 * 3643 * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3644 */ 3645 # op vAA, field /* BBBB */ 3646 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3647 FETCH(a1, 1) # a1 <- field ref BBBB 3648 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3649 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3650 bnez a0, .LOP_SPUT_CHAR_finish # is resolved entry null? 3651 /* 3652 * Continuation if the field has not yet been resolved. 3653 * a1: BBBB field ref 3654 * rBIX: dvmDex->pResFields 3655 */ 3656 LOAD_rSELF_method(a2) # a2 <- current method 3657 #if defined(WITH_JIT) 3658 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3659 #endif 3660 EXPORT_PC() # resolve() may throw, so export now 3661 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3662 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3663 move a0, v0 3664 beqz v0, common_exceptionThrown # success? no, handle exception 3665 #if defined(WITH_JIT) 3666 /* 3667 * If the JIT is actively building a trace we need to make sure 3668 * that the field is fully resolved before including this instruction. 3669 */ 3670 JAL(common_verifyField) 3671 #endif 3672 b .LOP_SPUT_CHAR_finish # resume 3673 3674 3675 /* ------------------------------ */ 3676 .balign 128 3677 .L_OP_SPUT_SHORT: /* 0x6d */ 3678 /* File: mips/OP_SPUT_SHORT.S */ 3679 /* File: mips/OP_SPUT.S */ 3680 /* 3681 * General 32-bit SPUT handler. 3682 * 3683 * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3684 */ 3685 # op vAA, field /* BBBB */ 3686 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 3687 FETCH(a1, 1) # a1 <- field ref BBBB 3688 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 3689 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 3690 bnez a0, .LOP_SPUT_SHORT_finish # is resolved entry null? 3691 /* 3692 * Continuation if the field has not yet been resolved. 3693 * a1: BBBB field ref 3694 * rBIX: dvmDex->pResFields 3695 */ 3696 LOAD_rSELF_method(a2) # a2 <- current method 3697 #if defined(WITH_JIT) 3698 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 3699 #endif 3700 EXPORT_PC() # resolve() may throw, so export now 3701 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 3702 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 3703 move a0, v0 3704 beqz v0, common_exceptionThrown # success? no, handle exception 3705 #if defined(WITH_JIT) 3706 /* 3707 * If the JIT is actively building a trace we need to make sure 3708 * that the field is fully resolved before including this instruction. 3709 */ 3710 JAL(common_verifyField) 3711 #endif 3712 b .LOP_SPUT_SHORT_finish # resume 3713 3714 3715 /* ------------------------------ */ 3716 .balign 128 3717 .L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3718 /* File: mips/OP_INVOKE_VIRTUAL.S */ 3719 /* 3720 * Handle a virtual method call. 3721 * 3722 * for: invoke-virtual, invoke-virtual/range 3723 */ 3724 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3725 # op vAA, {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3726 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 3727 FETCH(a1, 1) # a1 <- BBBB 3728 LOAD_base_offDvmDex_pResMethods(a3, a3) # a3 <- pDvmDex->pResMethods 3729 FETCH(rBIX, 2) # rBIX <- GFED or CCCC 3730 LOAD_eas2(a0, a3, a1) # a0 <- resolved baseMethod 3731 .if (!0) 3732 and rBIX, rBIX, 15 # rBIX <- D (or stays CCCC) 3733 .endif 3734 EXPORT_PC() # must export for invoke 3735 # already resolved? 3736 bnez a0, .LOP_INVOKE_VIRTUAL_continue # yes, continue on 3737 3738 LOAD_rSELF_method(a3) # a3 <- self->method 3739 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 3740 li a2, METHOD_VIRTUAL # resolver method type 3741 JAL(dvmResolveMethod) # v0 <- call(clazz, ref, flags) 3742 move a0, v0 3743 # got null? 3744 bnez v0, .LOP_INVOKE_VIRTUAL_continue # no, continue 3745 b common_exceptionThrown # yes, handle exception 3746 3747 /* ------------------------------ */ 3748 .balign 128 3749 .L_OP_INVOKE_SUPER: /* 0x6f */ 3750 /* File: mips/OP_INVOKE_SUPER.S */ 3751 /* 3752 * Handle a "super" method call. 3753 * 3754 * for: invoke-super, invoke-super/range 3755 */ 3756 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3757 # op vAA, {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3758 FETCH(t0, 2) # t0 <- GFED or CCCC 3759 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 3760 .if (!0) 3761 and t0, t0, 15 # t0 <- D (or stays CCCC) 3762 .endif 3763 FETCH(a1, 1) # a1 <- BBBB 3764 LOAD_base_offDvmDex_pResMethods(a3, a3) # a3 <- pDvmDex->pResMethods 3765 GET_VREG(rOBJ, t0) # rOBJ <- "this" ptr 3766 LOAD_eas2(a0, a3, a1) # a0 <- resolved baseMethod 3767 # null "this"? 3768 LOAD_rSELF_method(t1) # t1 <- current method 3769 beqz rOBJ, common_errNullObject # null "this", throw exception 3770 # cmp a0, 0; already resolved? 3771 LOAD_base_offMethod_clazz(rBIX, t1) # rBIX <- method->clazz 3772 EXPORT_PC() # must export for invoke 3773 bnez a0, .LOP_INVOKE_SUPER_continue # resolved, continue on 3774 3775 move a0, rBIX # a0 <- method->clazz 3776 li a2, METHOD_VIRTUAL # resolver method type 3777 JAL(dvmResolveMethod) # v0 <- call(clazz, ref, flags) 3778 move a0, v0 3779 # got null? 3780 beqz v0, common_exceptionThrown # yes, handle exception 3781 b .LOP_INVOKE_SUPER_continue 3782 3783 /* ------------------------------ */ 3784 .balign 128 3785 .L_OP_INVOKE_DIRECT: /* 0x70 */ 3786 /* File: mips/OP_INVOKE_DIRECT.S */ 3787 /* 3788 * Handle a direct method call. 3789 * 3790 * (We could defer the "is 'this' pointer null" test to the common 3791 * method invocation code, and use a flag to indicate that static 3792 * calls don't count. If we do this as part of copying the arguments 3793 * out we could avoiding loading the first arg twice.) 3794 * 3795 * for: invoke-direct, invoke-direct/range 3796 */ 3797 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3798 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3799 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 3800 FETCH(a1, 1) # a1 <- BBBB 3801 LOAD_base_offDvmDex_pResMethods(a3, a3) # a3 <- pDvmDex->pResMethods 3802 FETCH(rBIX, 2) # rBIX <- GFED or CCCC 3803 LOAD_eas2(a0, a3, a1) # a0 <- resolved methodToCall 3804 .if (!0) 3805 and rBIX, rBIX, 15 # rBIX <- D (or stays CCCC) 3806 .endif 3807 EXPORT_PC() # must export for invoke 3808 GET_VREG(rOBJ, rBIX) # rOBJ <- "this" ptr 3809 # already resolved? 3810 bnez a0, 1f # resolved, call the function 3811 3812 lw a3, offThread_method(rSELF) # a3 <- self->method 3813 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 3814 li a2, METHOD_DIRECT # resolver method type 3815 JAL(dvmResolveMethod) # v0 <- call(clazz, ref, flags) 3816 move a0, v0 3817 # got null? 3818 beqz v0, common_exceptionThrown # yes, handle exception 3819 3820 1: 3821 bnez rOBJ, common_invokeMethodNoRange # a0=method, rOBJ="this" 3822 b common_errNullObject # yes, throw exception 3823 3824 3825 3826 3827 /* ------------------------------ */ 3828 .balign 128 3829 .L_OP_INVOKE_STATIC: /* 0x71 */ 3830 /* File: mips/OP_INVOKE_STATIC.S */ 3831 /* 3832 * Handle a static method call. 3833 * 3834 * for: invoke-static, invoke-static/range 3835 */ 3836 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3837 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3838 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 3839 FETCH(a1, 1) # a1 <- BBBB 3840 LOAD_base_offDvmDex_pResMethods(a3, a3) # a3 <- pDvmDex->pResMethods 3841 li rOBJ, 0 # null "this" in delay slot 3842 LOAD_eas2(a0, a3, a1) # a0 <- resolved methodToCall 3843 #if defined(WITH_JIT) 3844 EAS2(rBIX, a3, a1) # rBIX<- &resolved_metherToCall 3845 #endif 3846 EXPORT_PC() # must export for invoke 3847 # already resolved? 3848 bnez a0, common_invokeMethodNoRange # yes, continue on 3849 b .LOP_INVOKE_STATIC_resolve 3850 3851 /* ------------------------------ */ 3852 .balign 128 3853 .L_OP_INVOKE_INTERFACE: /* 0x72 */ 3854 /* File: mips/OP_INVOKE_INTERFACE.S */ 3855 /* 3856 * Handle an interface method call. 3857 * 3858 * for: invoke-interface, invoke-interface/range 3859 */ 3860 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3861 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3862 FETCH(a2, 2) # a2 <- FEDC or CCCC 3863 FETCH(a1, 1) # a1 <- BBBB 3864 .if (!0) 3865 and a2, 15 # a2 <- C (or stays CCCC) 3866 .endif 3867 EXPORT_PC() # must export for invoke 3868 GET_VREG(rOBJ, a2) # rOBJ <- first arg ("this") 3869 LOAD_rSELF_methodClassDex(a3) # a3 <- methodClassDex 3870 LOAD_rSELF_method(a2) # a2 <- method 3871 # null obj? 3872 beqz rOBJ, common_errNullObject # yes, fail 3873 LOAD_base_offObject_clazz(a0, rOBJ) # a0 <- thisPtr->clazz 3874 JAL(dvmFindInterfaceMethodInCache) # v0 <- call(class, ref, method, dex) 3875 move a0, v0 3876 # failed? 3877 beqz v0, common_exceptionThrown # yes, handle exception 3878 b common_invokeMethodNoRange # (a0=method, rOBJ="this") 3879 3880 /* ------------------------------ */ 3881 .balign 128 3882 .L_OP_UNUSED_73: /* 0x73 */ 3883 /* File: mips/OP_UNUSED_73.S */ 3884 /* File: mips/unused.S */ 3885 BAL(common_abort) 3886 3887 3888 3889 /* ------------------------------ */ 3890 .balign 128 3891 .L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3892 /* File: mips/OP_INVOKE_VIRTUAL_RANGE.S */ 3893 /* File: mips/OP_INVOKE_VIRTUAL.S */ 3894 /* 3895 * Handle a virtual method call. 3896 * 3897 * for: invoke-virtual, invoke-virtual/range 3898 */ 3899 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3900 # op vAA, {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3901 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 3902 FETCH(a1, 1) # a1 <- BBBB 3903 LOAD_base_offDvmDex_pResMethods(a3, a3) # a3 <- pDvmDex->pResMethods 3904 FETCH(rBIX, 2) # rBIX <- GFED or CCCC 3905 LOAD_eas2(a0, a3, a1) # a0 <- resolved baseMethod 3906 .if (!1) 3907 and rBIX, rBIX, 15 # rBIX <- D (or stays CCCC) 3908 .endif 3909 EXPORT_PC() # must export for invoke 3910 # already resolved? 3911 bnez a0, .LOP_INVOKE_VIRTUAL_RANGE_continue # yes, continue on 3912 3913 LOAD_rSELF_method(a3) # a3 <- self->method 3914 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 3915 li a2, METHOD_VIRTUAL # resolver method type 3916 JAL(dvmResolveMethod) # v0 <- call(clazz, ref, flags) 3917 move a0, v0 3918 # got null? 3919 bnez v0, .LOP_INVOKE_VIRTUAL_RANGE_continue # no, continue 3920 b common_exceptionThrown # yes, handle exception 3921 3922 3923 /* ------------------------------ */ 3924 .balign 128 3925 .L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3926 /* File: mips/OP_INVOKE_SUPER_RANGE.S */ 3927 /* File: mips/OP_INVOKE_SUPER.S */ 3928 /* 3929 * Handle a "super" method call. 3930 * 3931 * for: invoke-super, invoke-super/range 3932 */ 3933 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3934 # op vAA, {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3935 FETCH(t0, 2) # t0 <- GFED or CCCC 3936 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 3937 .if (!1) 3938 and t0, t0, 15 # t0 <- D (or stays CCCC) 3939 .endif 3940 FETCH(a1, 1) # a1 <- BBBB 3941 LOAD_base_offDvmDex_pResMethods(a3, a3) # a3 <- pDvmDex->pResMethods 3942 GET_VREG(rOBJ, t0) # rOBJ <- "this" ptr 3943 LOAD_eas2(a0, a3, a1) # a0 <- resolved baseMethod 3944 # null "this"? 3945 LOAD_rSELF_method(t1) # t1 <- current method 3946 beqz rOBJ, common_errNullObject # null "this", throw exception 3947 # cmp a0, 0; already resolved? 3948 LOAD_base_offMethod_clazz(rBIX, t1) # rBIX <- method->clazz 3949 EXPORT_PC() # must export for invoke 3950 bnez a0, .LOP_INVOKE_SUPER_RANGE_continue # resolved, continue on 3951 3952 move a0, rBIX # a0 <- method->clazz 3953 li a2, METHOD_VIRTUAL # resolver method type 3954 JAL(dvmResolveMethod) # v0 <- call(clazz, ref, flags) 3955 move a0, v0 3956 # got null? 3957 beqz v0, common_exceptionThrown # yes, handle exception 3958 b .LOP_INVOKE_SUPER_RANGE_continue 3959 3960 3961 /* ------------------------------ */ 3962 .balign 128 3963 .L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3964 /* File: mips/OP_INVOKE_DIRECT_RANGE.S */ 3965 /* File: mips/OP_INVOKE_DIRECT.S */ 3966 /* 3967 * Handle a direct method call. 3968 * 3969 * (We could defer the "is 'this' pointer null" test to the common 3970 * method invocation code, and use a flag to indicate that static 3971 * calls don't count. If we do this as part of copying the arguments 3972 * out we could avoiding loading the first arg twice.) 3973 * 3974 * for: invoke-direct, invoke-direct/range 3975 */ 3976 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3977 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3978 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 3979 FETCH(a1, 1) # a1 <- BBBB 3980 LOAD_base_offDvmDex_pResMethods(a3, a3) # a3 <- pDvmDex->pResMethods 3981 FETCH(rBIX, 2) # rBIX <- GFED or CCCC 3982 LOAD_eas2(a0, a3, a1) # a0 <- resolved methodToCall 3983 .if (!1) 3984 and rBIX, rBIX, 15 # rBIX <- D (or stays CCCC) 3985 .endif 3986 EXPORT_PC() # must export for invoke 3987 GET_VREG(rOBJ, rBIX) # rOBJ <- "this" ptr 3988 # already resolved? 3989 bnez a0, 1f # resolved, call the function 3990 3991 lw a3, offThread_method(rSELF) # a3 <- self->method 3992 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 3993 li a2, METHOD_DIRECT # resolver method type 3994 JAL(dvmResolveMethod) # v0 <- call(clazz, ref, flags) 3995 move a0, v0 3996 # got null? 3997 beqz v0, common_exceptionThrown # yes, handle exception 3998 3999 1: 4000 bnez rOBJ, common_invokeMethodRange # a0=method, rOBJ="this" 4001 b common_errNullObject # yes, throw exception 4002 4003 4004 4005 4006 4007 /* ------------------------------ */ 4008 .balign 128 4009 .L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 4010 /* File: mips/OP_INVOKE_STATIC_RANGE.S */ 4011 /* File: mips/OP_INVOKE_STATIC.S */ 4012 /* 4013 * Handle a static method call. 4014 * 4015 * for: invoke-static, invoke-static/range 4016 */ 4017 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 4018 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 4019 LOAD_rSELF_methodClassDex(a3) # a3 <- pDvmDex 4020 FETCH(a1, 1) # a1 <- BBBB 4021 LOAD_base_offDvmDex_pResMethods(a3, a3) # a3 <- pDvmDex->pResMethods 4022 li rOBJ, 0 # null "this" in delay slot 4023 LOAD_eas2(a0, a3, a1) # a0 <- resolved methodToCall 4024 #if defined(WITH_JIT) 4025 EAS2(rBIX, a3, a1) # rBIX<- &resolved_metherToCall 4026 #endif 4027 EXPORT_PC() # must export for invoke 4028 # already resolved? 4029 bnez a0, common_invokeMethodRange # yes, continue on 4030 b .LOP_INVOKE_STATIC_RANGE_resolve 4031 4032 4033 /* ------------------------------ */ 4034 .balign 128 4035 .L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 4036 /* File: mips/OP_INVOKE_INTERFACE_RANGE.S */ 4037 /* File: mips/OP_INVOKE_INTERFACE.S */ 4038 /* 4039 * Handle an interface method call. 4040 * 4041 * for: invoke-interface, invoke-interface/range 4042 */ 4043 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 4044 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 4045 FETCH(a2, 2) # a2 <- FEDC or CCCC 4046 FETCH(a1, 1) # a1 <- BBBB 4047 .if (!1) 4048 and a2, 15 # a2 <- C (or stays CCCC) 4049 .endif 4050 EXPORT_PC() # must export for invoke 4051 GET_VREG(rOBJ, a2) # rOBJ <- first arg ("this") 4052 LOAD_rSELF_methodClassDex(a3) # a3 <- methodClassDex 4053 LOAD_rSELF_method(a2) # a2 <- method 4054 # null obj? 4055 beqz rOBJ, common_errNullObject # yes, fail 4056 LOAD_base_offObject_clazz(a0, rOBJ) # a0 <- thisPtr->clazz 4057 JAL(dvmFindInterfaceMethodInCache) # v0 <- call(class, ref, method, dex) 4058 move a0, v0 4059 # failed? 4060 beqz v0, common_exceptionThrown # yes, handle exception 4061 b common_invokeMethodRange # (a0=method, rOBJ="this") 4062 4063 4064 /* ------------------------------ */ 4065 .balign 128 4066 .L_OP_UNUSED_79: /* 0x79 */ 4067 /* File: mips/OP_UNUSED_79.S */ 4068 /* File: mips/unused.S */ 4069 BAL(common_abort) 4070 4071 4072 4073 /* ------------------------------ */ 4074 .balign 128 4075 .L_OP_UNUSED_7A: /* 0x7a */ 4076 /* File: mips/OP_UNUSED_7A.S */ 4077 /* File: mips/unused.S */ 4078 BAL(common_abort) 4079 4080 4081 4082 /* ------------------------------ */ 4083 .balign 128 4084 .L_OP_NEG_INT: /* 0x7b */ 4085 /* File: mips/OP_NEG_INT.S */ 4086 /* File: mips/unop.S */ 4087 /* 4088 * Generic 32-bit unary operation. Provide an "instr" line that 4089 * specifies an instruction that performs "result = op a0". 4090 * This could be a MIPS instruction or a function call. 4091 * 4092 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4093 * int-to-byte, int-to-char, int-to-short 4094 */ 4095 /* unop vA, vB */ 4096 GET_OPB(a3) # a3 <- B 4097 GET_OPA4(t0) # t0 <- A+ 4098 GET_VREG(a0, a3) # a0 <- vB 4099 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4100 # optional op 4101 negu a0, a0 # a0 <- op, a0-a3 changed 4102 GET_INST_OPCODE(t1) # extract opcode from rINST 4103 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 4104 /* 9-10 instructions */ 4105 4106 4107 /* ------------------------------ */ 4108 .balign 128 4109 .L_OP_NOT_INT: /* 0x7c */ 4110 /* File: mips/OP_NOT_INT.S */ 4111 /* File: mips/unop.S */ 4112 /* 4113 * Generic 32-bit unary operation. Provide an "instr" line that 4114 * specifies an instruction that performs "result = op a0". 4115 * This could be a MIPS instruction or a function call. 4116 * 4117 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4118 * int-to-byte, int-to-char, int-to-short 4119 */ 4120 /* unop vA, vB */ 4121 GET_OPB(a3) # a3 <- B 4122 GET_OPA4(t0) # t0 <- A+ 4123 GET_VREG(a0, a3) # a0 <- vB 4124 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4125 # optional op 4126 not a0, a0 # a0 <- op, a0-a3 changed 4127 GET_INST_OPCODE(t1) # extract opcode from rINST 4128 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 4129 /* 9-10 instructions */ 4130 4131 4132 /* ------------------------------ */ 4133 .balign 128 4134 .L_OP_NEG_LONG: /* 0x7d */ 4135 /* File: mips/OP_NEG_LONG.S */ 4136 /* File: mips/unopWide.S */ 4137 /* 4138 * Generic 64-bit unary operation. Provide an "instr" line that 4139 * specifies an instruction that performs "result = op a0/a1". 4140 * This could be MIPS instruction or a function call. 4141 * 4142 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 4143 */ 4144 /* unop vA, vB */ 4145 GET_OPA4(t1) # t1 <- A+ 4146 GET_OPB(a3) # a3 <- B 4147 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4148 EAS2(rOBJ, rFP, t1) # rOBJ <- &fp[A] 4149 LOAD64(a0, a1, a3) # a0/a1 <- vAA 4150 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4151 negu v0, a0 # optional op 4152 negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0 # a0/a1 <- op, a2-a3 changed 4153 GET_INST_OPCODE(t0) # extract opcode from rINST 4154 STORE64(v0, v1, rOBJ) # vAA <- a0/a1 4155 GOTO_OPCODE(t0) # jump to next instruction 4156 /* 12-13 instructions */ 4157 4158 4159 4160 4161 /* ------------------------------ */ 4162 .balign 128 4163 .L_OP_NOT_LONG: /* 0x7e */ 4164 /* File: mips/OP_NOT_LONG.S */ 4165 /* File: mips/unopWide.S */ 4166 /* 4167 * Generic 64-bit unary operation. Provide an "instr" line that 4168 * specifies an instruction that performs "result = op a0/a1". 4169 * This could be MIPS instruction or a function call. 4170 * 4171 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 4172 */ 4173 /* unop vA, vB */ 4174 GET_OPA4(t1) # t1 <- A+ 4175 GET_OPB(a3) # a3 <- B 4176 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4177 EAS2(rOBJ, rFP, t1) # rOBJ <- &fp[A] 4178 LOAD64(a0, a1, a3) # a0/a1 <- vAA 4179 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4180 not a0, a0 # optional op 4181 not a1, a1 # a0/a1 <- op, a2-a3 changed 4182 GET_INST_OPCODE(t0) # extract opcode from rINST 4183 STORE64(a0, a1, rOBJ) # vAA <- a0/a1 4184 GOTO_OPCODE(t0) # jump to next instruction 4185 /* 12-13 instructions */ 4186 4187 4188 4189 /* ------------------------------ */ 4190 .balign 128 4191 .L_OP_NEG_FLOAT: /* 0x7f */ 4192 /* File: mips/OP_NEG_FLOAT.S */ 4193 /* File: mips/unop.S */ 4194 /* 4195 * Generic 32-bit unary operation. Provide an "instr" line that 4196 * specifies an instruction that performs "result = op a0". 4197 * This could be a MIPS instruction or a function call. 4198 * 4199 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4200 * int-to-byte, int-to-char, int-to-short 4201 */ 4202 /* unop vA, vB */ 4203 GET_OPB(a3) # a3 <- B 4204 GET_OPA4(t0) # t0 <- A+ 4205 GET_VREG(a0, a3) # a0 <- vB 4206 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4207 # optional op 4208 addu a0, a0, 0x80000000 # a0 <- op, a0-a3 changed 4209 GET_INST_OPCODE(t1) # extract opcode from rINST 4210 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 4211 /* 9-10 instructions */ 4212 4213 4214 /* ------------------------------ */ 4215 .balign 128 4216 .L_OP_NEG_DOUBLE: /* 0x80 */ 4217 /* File: mips/OP_NEG_DOUBLE.S */ 4218 /* File: mips/unopWide.S */ 4219 /* 4220 * Generic 64-bit unary operation. Provide an "instr" line that 4221 * specifies an instruction that performs "result = op a0/a1". 4222 * This could be MIPS instruction or a function call. 4223 * 4224 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 4225 */ 4226 /* unop vA, vB */ 4227 GET_OPA4(t1) # t1 <- A+ 4228 GET_OPB(a3) # a3 <- B 4229 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4230 EAS2(rOBJ, rFP, t1) # rOBJ <- &fp[A] 4231 LOAD64(a0, a1, a3) # a0/a1 <- vAA 4232 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4233 # optional op 4234 addu a1, a1, 0x80000000 # a0/a1 <- op, a2-a3 changed 4235 GET_INST_OPCODE(t0) # extract opcode from rINST 4236 STORE64(a0, a1, rOBJ) # vAA <- a0/a1 4237 GOTO_OPCODE(t0) # jump to next instruction 4238 /* 12-13 instructions */ 4239 4240 4241 4242 /* ------------------------------ */ 4243 .balign 128 4244 .L_OP_INT_TO_LONG: /* 0x81 */ 4245 /* File: mips/OP_INT_TO_LONG.S */ 4246 /* File: mips/unopWider.S */ 4247 /* 4248 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 4249 * that specifies an instruction that performs "result = op a0", where 4250 * "result" is a 64-bit quantity in a0/a1. 4251 * 4252 * For: int-to-long, int-to-double, float-to-long, float-to-double 4253 */ 4254 /* unop vA, vB */ 4255 GET_OPA4(t1) # t1 <- A+ 4256 GET_OPB(a3) # a3 <- B 4257 GET_VREG(a0, a3) # a0 <- vB 4258 EAS2(rOBJ, rFP, t1) # rOBJ <- &fp[A] 4259 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4260 # optional op 4261 sra a1, a0, 31 # result <- op, a0-a3 changed 4262 GET_INST_OPCODE(t0) # extract opcode from rINST 4263 STORE64(a0, a1, rOBJ) # vA/vA+1 <- a0/a1 4264 GOTO_OPCODE(t0) # jump to next instruction 4265 /* 10-11 instructions */ 4266 4267 4268 /* ------------------------------ */ 4269 .balign 128 4270 .L_OP_INT_TO_FLOAT: /* 0x82 */ 4271 /* File: mips/OP_INT_TO_FLOAT.S */ 4272 /* File: mips/unflop.S */ 4273 /* 4274 * Generic 32-bit unary operation. Provide an "instr" line that 4275 * specifies an instruction that performs "result = op a0". 4276 * This could be a MIPS instruction or a function call. 4277 * 4278 * for: int-to-float, float-to-int 4279 */ 4280 /* unop vA, vB */ 4281 GET_OPB(a3) # a3 <- B 4282 GET_OPA4(rOBJ) # t0 <- A+ 4283 #ifdef SOFT_FLOAT 4284 GET_VREG(a0, a3) # a0 <- vB 4285 #else 4286 GET_VREG_F(fa0, a3) 4287 #endif 4288 # optional op 4289 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4290 #ifdef SOFT_FLOAT 4291 JAL(__floatsisf) # a0 <- op, a0-a3 changed 4292 4293 .LOP_INT_TO_FLOAT_set_vreg: 4294 SET_VREG(v0, rOBJ) # vAA <- result0 4295 #else 4296 cvt.s.w fv0, fa0 4297 4298 .LOP_INT_TO_FLOAT_set_vreg_f: 4299 SET_VREG_F(fv0, rOBJ) 4300 #endif 4301 GET_INST_OPCODE(t1) # extract opcode from rINST 4302 GOTO_OPCODE(t1) # jump to next instruction 4303 /* 9-10 instructions */ 4304 4305 4306 /* ------------------------------ */ 4307 .balign 128 4308 .L_OP_INT_TO_DOUBLE: /* 0x83 */ 4309 /* File: mips/OP_INT_TO_DOUBLE.S */ 4310 /* File: mips/unflopWider.S */ 4311 /* 4312 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 4313 * that specifies an instruction that performs "result = op a0", where 4314 * "result" is a 64-bit quantity in a0/a1. 4315 * 4316 * For: int-to-double, float-to-long, float-to-double 4317 */ 4318 /* unop vA, vB */ 4319 GET_OPA4(rOBJ) # rOBJ <- A+ 4320 GET_OPB(a3) # a3 <- B 4321 #ifdef SOFT_FLOAT 4322 GET_VREG(a0, a3) # a0 <- vB 4323 #else 4324 GET_VREG_F(fa0, a3) 4325 #endif 4326 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 4327 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4328 # optional op 4329 #ifdef SOFT_FLOAT 4330 JAL(__floatsidf) # result <- op, a0-a3 changed 4331 4332 .LOP_INT_TO_DOUBLE_set_vreg: 4333 STORE64(rRESULT0, rRESULT1, rOBJ) # vA/vA+1 <- a0/a1 4334 #else 4335 cvt.d.w fv0, fa0 4336 4337 .LOP_INT_TO_DOUBLE_set_vreg: 4338 STORE64_F(fv0, fv0f, rOBJ) # vA/vA+1 <- a0/a1 4339 #endif 4340 GET_INST_OPCODE(t0) # extract opcode from rINST 4341 GOTO_OPCODE(t0) # jump to next instruction 4342 /* 10-11 instructions */ 4343 4344 4345 /* ------------------------------ */ 4346 .balign 128 4347 .L_OP_LONG_TO_INT: /* 0x84 */ 4348 /* File: mips/OP_LONG_TO_INT.S */ 4349 GET_OPB(a1) # a1 <- B from 15:12 4350 GET_OPA4(a0) # a0 <- A from 11:8 4351 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4352 #ifdef HAVE_BIG_ENDIAN 4353 addu a1, a1, 1 4354 #endif 4355 GET_VREG(a2, a1) # a2 <- fp[B] 4356 GET_INST_OPCODE(t0) # t0 <- opcode from rINST 4357 SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 4358 4359 /* ------------------------------ */ 4360 .balign 128 4361 .L_OP_LONG_TO_FLOAT: /* 0x85 */ 4362 /* File: mips/OP_LONG_TO_FLOAT.S */ 4363 /* File: mips/unopNarrower.S */ 4364 /* 4365 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 4366 * that specifies an instruction that performs "result = op a0/a1", where 4367 * "result" is a 32-bit quantity in a0. 4368 * 4369 * For: long-to-float, double-to-int, double-to-float 4370 * If hard floating point support is available, use fa0 as the parameter, except for 4371 * long-to-float opcode. 4372 * (This would work for long-to-int, but that instruction is actually 4373 * an exact match for OP_MOVE.) 4374 */ 4375 /* unop vA, vB */ 4376 GET_OPB(a3) # a3 <- B 4377 GET_OPA4(rOBJ) # t1 <- A+ 4378 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4379 #ifdef SOFT_FLOAT 4380 LOAD64(rARG0, rARG1, a3) # a0/a1 <- vB/vB+1 4381 #else 4382 LOAD64(rARG0, rARG1, a3) 4383 #endif 4384 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4385 # optional op 4386 #ifdef SOFT_FLOAT 4387 JAL(__floatdisf) # a0 <- op, a0-a3 changed 4388 4389 .LOP_LONG_TO_FLOAT_set_vreg: 4390 SET_VREG(v0, rOBJ) # vA <- result0 4391 #else 4392 JAL(__floatdisf) 4393 4394 .LOP_LONG_TO_FLOAT_set_vreg_f: 4395 SET_VREG_F(fv0, rOBJ) # vA <- result0 4396 #endif 4397 GET_INST_OPCODE(t0) # extract opcode from rINST 4398 GOTO_OPCODE(t0) # jump to next instruction 4399 /* 10-11 instructions */ 4400 4401 4402 /* ------------------------------ */ 4403 .balign 128 4404 .L_OP_LONG_TO_DOUBLE: /* 0x86 */ 4405 /* File: mips/OP_LONG_TO_DOUBLE.S */ 4406 /* File: mips/unflopWide.S */ 4407 /* 4408 * Generic 64-bit unary operation. Provide an "instr" line that 4409 * specifies an instruction that performs "result = op a0/a1". 4410 * This could be a MIPS instruction or a function call. 4411 * 4412 * long-to-double, double-to-long 4413 */ 4414 /* unop vA, vB */ 4415 GET_OPA4(rOBJ) # t1 <- A+ 4416 GET_OPB(a3) # a3 <- B 4417 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4418 EAS2(rOBJ, rFP, rOBJ) # t1 <- &fp[A] 4419 #ifdef SOFT_FLOAT 4420 LOAD64(rARG0, rARG1, a3) # a0/a1 <- vAA 4421 #else 4422 LOAD64(rARG0, rARG1, a3) 4423 #endif 4424 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4425 # optional op 4426 JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed 4427 4428 .LOP_LONG_TO_DOUBLE_set_vreg: 4429 #ifdef SOFT_FLOAT 4430 STORE64(rRESULT0, rRESULT1, rOBJ) # vAA <- a0/a1 4431 #else 4432 STORE64_F(fv0, fv0f, rOBJ) # vAA <- a0/a1 4433 #endif 4434 GET_INST_OPCODE(t0) # extract opcode from rINST 4435 GOTO_OPCODE(t0) # jump to next instruction 4436 /* 12-13 instructions */ 4437 4438 4439 4440 /* ------------------------------ */ 4441 .balign 128 4442 .L_OP_FLOAT_TO_INT: /* 0x87 */ 4443 /* File: mips/OP_FLOAT_TO_INT.S */ 4444 /* File: mips/unflop.S */ 4445 /* 4446 * Generic 32-bit unary operation. Provide an "instr" line that 4447 * specifies an instruction that performs "result = op a0". 4448 * This could be a MIPS instruction or a function call. 4449 * 4450 * for: int-to-float, float-to-int 4451 */ 4452 /* unop vA, vB */ 4453 GET_OPB(a3) # a3 <- B 4454 GET_OPA4(rOBJ) # t0 <- A+ 4455 #ifdef SOFT_FLOAT 4456 GET_VREG(a0, a3) # a0 <- vB 4457 #else 4458 GET_VREG_F(fa0, a3) 4459 #endif 4460 # optional op 4461 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4462 #ifdef SOFT_FLOAT 4463 b f2i_doconv # a0 <- op, a0-a3 changed 4464 4465 .LOP_FLOAT_TO_INT_set_vreg: 4466 SET_VREG(v0, rOBJ) # vAA <- result0 4467 #else 4468 b f2i_doconv 4469 4470 .LOP_FLOAT_TO_INT_set_vreg_f: 4471 SET_VREG_F(fv0, rOBJ) 4472 #endif 4473 GET_INST_OPCODE(t1) # extract opcode from rINST 4474 GOTO_OPCODE(t1) # jump to next instruction 4475 /* 9-10 instructions */ 4476 4477 4478 /* ------------------------------ */ 4479 .balign 128 4480 .L_OP_FLOAT_TO_LONG: /* 0x88 */ 4481 /* File: mips/OP_FLOAT_TO_LONG.S */ 4482 /* File: mips/unflopWider.S */ 4483 /* 4484 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 4485 * that specifies an instruction that performs "result = op a0", where 4486 * "result" is a 64-bit quantity in a0/a1. 4487 * 4488 * For: int-to-double, float-to-long, float-to-double 4489 */ 4490 /* unop vA, vB */ 4491 GET_OPA4(rOBJ) # rOBJ <- A+ 4492 GET_OPB(a3) # a3 <- B 4493 #ifdef SOFT_FLOAT 4494 GET_VREG(a0, a3) # a0 <- vB 4495 #else 4496 GET_VREG_F(fa0, a3) 4497 #endif 4498 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 4499 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4500 # optional op 4501 #ifdef SOFT_FLOAT 4502 b f2l_doconv # result <- op, a0-a3 changed 4503 4504 .LOP_FLOAT_TO_LONG_set_vreg: 4505 STORE64(rRESULT0, rRESULT1, rOBJ) # vA/vA+1 <- a0/a1 4506 #else 4507 b f2l_doconv 4508 4509 .LOP_FLOAT_TO_LONG_set_vreg: 4510 STORE64(rRESULT0, rRESULT1, rOBJ) # vA/vA+1 <- a0/a1 4511 #endif 4512 GET_INST_OPCODE(t0) # extract opcode from rINST 4513 GOTO_OPCODE(t0) # jump to next instruction 4514 /* 10-11 instructions */ 4515 4516 4517 /* ------------------------------ */ 4518 .balign 128 4519 .L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 4520 /* File: mips/OP_FLOAT_TO_DOUBLE.S */ 4521 /* File: mips/unflopWider.S */ 4522 /* 4523 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 4524 * that specifies an instruction that performs "result = op a0", where 4525 * "result" is a 64-bit quantity in a0/a1. 4526 * 4527 * For: int-to-double, float-to-long, float-to-double 4528 */ 4529 /* unop vA, vB */ 4530 GET_OPA4(rOBJ) # rOBJ <- A+ 4531 GET_OPB(a3) # a3 <- B 4532 #ifdef SOFT_FLOAT 4533 GET_VREG(a0, a3) # a0 <- vB 4534 #else 4535 GET_VREG_F(fa0, a3) 4536 #endif 4537 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 4538 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4539 # optional op 4540 #ifdef SOFT_FLOAT 4541 JAL(__extendsfdf2) # result <- op, a0-a3 changed 4542 4543 .LOP_FLOAT_TO_DOUBLE_set_vreg: 4544 STORE64(rRESULT0, rRESULT1, rOBJ) # vA/vA+1 <- a0/a1 4545 #else 4546 cvt.d.s fv0, fa0 4547 4548 .LOP_FLOAT_TO_DOUBLE_set_vreg: 4549 STORE64_F(fv0, fv0f, rOBJ) # vA/vA+1 <- a0/a1 4550 #endif 4551 GET_INST_OPCODE(t0) # extract opcode from rINST 4552 GOTO_OPCODE(t0) # jump to next instruction 4553 /* 10-11 instructions */ 4554 4555 4556 /* ------------------------------ */ 4557 .balign 128 4558 .L_OP_DOUBLE_TO_INT: /* 0x8a */ 4559 /* File: mips/OP_DOUBLE_TO_INT.S */ 4560 /* File: mips/unopNarrower.S */ 4561 /* 4562 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 4563 * that specifies an instruction that performs "result = op a0/a1", where 4564 * "result" is a 32-bit quantity in a0. 4565 * 4566 * For: long-to-float, double-to-int, double-to-float 4567 * If hard floating point support is available, use fa0 as the parameter, except for 4568 * long-to-float opcode. 4569 * (This would work for long-to-int, but that instruction is actually 4570 * an exact match for OP_MOVE.) 4571 */ 4572 /* unop vA, vB */ 4573 GET_OPB(a3) # a3 <- B 4574 GET_OPA4(rOBJ) # t1 <- A+ 4575 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4576 #ifdef SOFT_FLOAT 4577 LOAD64(rARG0, rARG1, a3) # a0/a1 <- vB/vB+1 4578 #else 4579 LOAD64_F(fa0, fa0f, a3) 4580 #endif 4581 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4582 # optional op 4583 #ifdef SOFT_FLOAT 4584 b d2i_doconv # a0 <- op, a0-a3 changed 4585 4586 .LOP_DOUBLE_TO_INT_set_vreg: 4587 SET_VREG(v0, rOBJ) # vA <- result0 4588 #else 4589 b d2i_doconv 4590 4591 .LOP_DOUBLE_TO_INT_set_vreg_f: 4592 SET_VREG_F(fv0, rOBJ) # vA <- result0 4593 #endif 4594 GET_INST_OPCODE(t0) # extract opcode from rINST 4595 GOTO_OPCODE(t0) # jump to next instruction 4596 /* 10-11 instructions */ 4597 4598 /* 4599 * Convert the double in a0/a1 to an int in a0. 4600 * 4601 * We have to clip values to int min/max per the specification. The 4602 * expected common case is a "reasonable" value that converts directly 4603 * to modest integer. The EABI convert function isn't doing this for us. 4604 * Use rBIX / rTEMP as global to hold arguments (they are not bound to a global var) 4605 */ 4606 4607 /* ------------------------------ */ 4608 .balign 128 4609 .L_OP_DOUBLE_TO_LONG: /* 0x8b */ 4610 /* File: mips/OP_DOUBLE_TO_LONG.S */ 4611 /* File: mips/unflopWide.S */ 4612 /* 4613 * Generic 64-bit unary operation. Provide an "instr" line that 4614 * specifies an instruction that performs "result = op a0/a1". 4615 * This could be a MIPS instruction or a function call. 4616 * 4617 * long-to-double, double-to-long 4618 */ 4619 /* unop vA, vB */ 4620 GET_OPA4(rOBJ) # t1 <- A+ 4621 GET_OPB(a3) # a3 <- B 4622 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4623 EAS2(rOBJ, rFP, rOBJ) # t1 <- &fp[A] 4624 #ifdef SOFT_FLOAT 4625 LOAD64(rARG0, rARG1, a3) # a0/a1 <- vAA 4626 #else 4627 LOAD64_F(fa0, fa0f, a3) 4628 #endif 4629 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4630 # optional op 4631 b d2l_doconv # a0/a1 <- op, a2-a3 changed 4632 4633 .LOP_DOUBLE_TO_LONG_set_vreg: 4634 #ifdef SOFT_FLOAT 4635 STORE64(rRESULT0, rRESULT1, rOBJ) # vAA <- a0/a1 4636 #else 4637 STORE64(rRESULT0, rRESULT1, rOBJ) # vAA <- a0/a1 4638 #endif 4639 GET_INST_OPCODE(t0) # extract opcode from rINST 4640 GOTO_OPCODE(t0) # jump to next instruction 4641 /* 12-13 instructions */ 4642 4643 4644 4645 /* ------------------------------ */ 4646 .balign 128 4647 .L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 4648 /* File: mips/OP_DOUBLE_TO_FLOAT.S */ 4649 /* File: mips/unopNarrower.S */ 4650 /* 4651 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 4652 * that specifies an instruction that performs "result = op a0/a1", where 4653 * "result" is a 32-bit quantity in a0. 4654 * 4655 * For: long-to-float, double-to-int, double-to-float 4656 * If hard floating point support is available, use fa0 as the parameter, except for 4657 * long-to-float opcode. 4658 * (This would work for long-to-int, but that instruction is actually 4659 * an exact match for OP_MOVE.) 4660 */ 4661 /* unop vA, vB */ 4662 GET_OPB(a3) # a3 <- B 4663 GET_OPA4(rOBJ) # t1 <- A+ 4664 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4665 #ifdef SOFT_FLOAT 4666 LOAD64(rARG0, rARG1, a3) # a0/a1 <- vB/vB+1 4667 #else 4668 LOAD64_F(fa0, fa0f, a3) 4669 #endif 4670 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4671 # optional op 4672 #ifdef SOFT_FLOAT 4673 JAL(__truncdfsf2) # a0 <- op, a0-a3 changed 4674 4675 .LOP_DOUBLE_TO_FLOAT_set_vreg: 4676 SET_VREG(v0, rOBJ) # vA <- result0 4677 #else 4678 cvt.s.d fv0, fa0 4679 4680 .LOP_DOUBLE_TO_FLOAT_set_vreg_f: 4681 SET_VREG_F(fv0, rOBJ) # vA <- result0 4682 #endif 4683 GET_INST_OPCODE(t0) # extract opcode from rINST 4684 GOTO_OPCODE(t0) # jump to next instruction 4685 /* 10-11 instructions */ 4686 4687 4688 /* ------------------------------ */ 4689 .balign 128 4690 .L_OP_INT_TO_BYTE: /* 0x8d */ 4691 /* File: mips/OP_INT_TO_BYTE.S */ 4692 /* File: mips/unop.S */ 4693 /* 4694 * Generic 32-bit unary operation. Provide an "instr" line that 4695 * specifies an instruction that performs "result = op a0". 4696 * This could be a MIPS instruction or a function call. 4697 * 4698 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4699 * int-to-byte, int-to-char, int-to-short 4700 */ 4701 /* unop vA, vB */ 4702 GET_OPB(a3) # a3 <- B 4703 GET_OPA4(t0) # t0 <- A+ 4704 GET_VREG(a0, a3) # a0 <- vB 4705 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4706 sll a0, a0, 24 # optional op 4707 sra a0, a0, 24 # a0 <- op, a0-a3 changed 4708 GET_INST_OPCODE(t1) # extract opcode from rINST 4709 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 4710 /* 9-10 instructions */ 4711 4712 4713 /* ------------------------------ */ 4714 .balign 128 4715 .L_OP_INT_TO_CHAR: /* 0x8e */ 4716 /* File: mips/OP_INT_TO_CHAR.S */ 4717 /* File: mips/unop.S */ 4718 /* 4719 * Generic 32-bit unary operation. Provide an "instr" line that 4720 * specifies an instruction that performs "result = op a0". 4721 * This could be a MIPS instruction or a function call. 4722 * 4723 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4724 * int-to-byte, int-to-char, int-to-short 4725 */ 4726 /* unop vA, vB */ 4727 GET_OPB(a3) # a3 <- B 4728 GET_OPA4(t0) # t0 <- A+ 4729 GET_VREG(a0, a3) # a0 <- vB 4730 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4731 # optional op 4732 and a0, 0xffff # a0 <- op, a0-a3 changed 4733 GET_INST_OPCODE(t1) # extract opcode from rINST 4734 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 4735 /* 9-10 instructions */ 4736 4737 4738 /* ------------------------------ */ 4739 .balign 128 4740 .L_OP_INT_TO_SHORT: /* 0x8f */ 4741 /* File: mips/OP_INT_TO_SHORT.S */ 4742 /* File: mips/unop.S */ 4743 /* 4744 * Generic 32-bit unary operation. Provide an "instr" line that 4745 * specifies an instruction that performs "result = op a0". 4746 * This could be a MIPS instruction or a function call. 4747 * 4748 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4749 * int-to-byte, int-to-char, int-to-short 4750 */ 4751 /* unop vA, vB */ 4752 GET_OPB(a3) # a3 <- B 4753 GET_OPA4(t0) # t0 <- A+ 4754 GET_VREG(a0, a3) # a0 <- vB 4755 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4756 sll a0, 16 # optional op 4757 sra a0, 16 # a0 <- op, a0-a3 changed 4758 GET_INST_OPCODE(t1) # extract opcode from rINST 4759 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 4760 /* 9-10 instructions */ 4761 4762 4763 /* ------------------------------ */ 4764 .balign 128 4765 .L_OP_ADD_INT: /* 0x90 */ 4766 /* File: mips/OP_ADD_INT.S */ 4767 /* File: mips/binop.S */ 4768 /* 4769 * Generic 32-bit binary operation. Provide an "instr" line that 4770 * specifies an instruction that performs "result = a0 op a1". 4771 * This could be a MIPS instruction or a function call. (If the result 4772 * comes back in a register other than a0, you can override "result".) 4773 * 4774 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4775 * vCC (a1). Useful for integer division and modulus. Note that we 4776 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4777 * handles it correctly. 4778 * 4779 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4780 * xor-int, shl-int, shr-int, ushr-int 4781 */ 4782 /* binop vAA, vBB, vCC */ 4783 FETCH(a0, 1) # a0 <- CCBB 4784 GET_OPA(rOBJ) # rOBJ <- AA 4785 srl a3, a0, 8 # a3 <- CC 4786 and a2, a0, 255 # a2 <- BB 4787 GET_VREG(a1, a3) # a1 <- vCC 4788 GET_VREG(a0, a2) # a0 <- vBB 4789 .if 0 4790 # is second operand zero? 4791 beqz a1, common_errDivideByZero 4792 .endif 4793 4794 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4795 # optional op 4796 addu a0, a0, a1 # a0 <- op, a0-a3 changed 4797 GET_INST_OPCODE(t0) # extract opcode from rINST 4798 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4799 /* 11-14 instructions */ 4800 4801 4802 4803 /* ------------------------------ */ 4804 .balign 128 4805 .L_OP_SUB_INT: /* 0x91 */ 4806 /* File: mips/OP_SUB_INT.S */ 4807 /* File: mips/binop.S */ 4808 /* 4809 * Generic 32-bit binary operation. Provide an "instr" line that 4810 * specifies an instruction that performs "result = a0 op a1". 4811 * This could be a MIPS instruction or a function call. (If the result 4812 * comes back in a register other than a0, you can override "result".) 4813 * 4814 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4815 * vCC (a1). Useful for integer division and modulus. Note that we 4816 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4817 * handles it correctly. 4818 * 4819 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4820 * xor-int, shl-int, shr-int, ushr-int 4821 */ 4822 /* binop vAA, vBB, vCC */ 4823 FETCH(a0, 1) # a0 <- CCBB 4824 GET_OPA(rOBJ) # rOBJ <- AA 4825 srl a3, a0, 8 # a3 <- CC 4826 and a2, a0, 255 # a2 <- BB 4827 GET_VREG(a1, a3) # a1 <- vCC 4828 GET_VREG(a0, a2) # a0 <- vBB 4829 .if 0 4830 # is second operand zero? 4831 beqz a1, common_errDivideByZero 4832 .endif 4833 4834 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4835 # optional op 4836 subu a0, a0, a1 # a0 <- op, a0-a3 changed 4837 GET_INST_OPCODE(t0) # extract opcode from rINST 4838 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4839 /* 11-14 instructions */ 4840 4841 4842 4843 /* ------------------------------ */ 4844 .balign 128 4845 .L_OP_MUL_INT: /* 0x92 */ 4846 /* File: mips/OP_MUL_INT.S */ 4847 /* File: mips/binop.S */ 4848 /* 4849 * Generic 32-bit binary operation. Provide an "instr" line that 4850 * specifies an instruction that performs "result = a0 op a1". 4851 * This could be a MIPS instruction or a function call. (If the result 4852 * comes back in a register other than a0, you can override "result".) 4853 * 4854 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4855 * vCC (a1). Useful for integer division and modulus. Note that we 4856 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4857 * handles it correctly. 4858 * 4859 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4860 * xor-int, shl-int, shr-int, ushr-int 4861 */ 4862 /* binop vAA, vBB, vCC */ 4863 FETCH(a0, 1) # a0 <- CCBB 4864 GET_OPA(rOBJ) # rOBJ <- AA 4865 srl a3, a0, 8 # a3 <- CC 4866 and a2, a0, 255 # a2 <- BB 4867 GET_VREG(a1, a3) # a1 <- vCC 4868 GET_VREG(a0, a2) # a0 <- vBB 4869 .if 0 4870 # is second operand zero? 4871 beqz a1, common_errDivideByZero 4872 .endif 4873 4874 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4875 # optional op 4876 mul a0, a0, a1 # a0 <- op, a0-a3 changed 4877 GET_INST_OPCODE(t0) # extract opcode from rINST 4878 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4879 /* 11-14 instructions */ 4880 4881 4882 4883 /* ------------------------------ */ 4884 .balign 128 4885 .L_OP_DIV_INT: /* 0x93 */ 4886 /* File: mips/OP_DIV_INT.S */ 4887 /* File: mips/binop.S */ 4888 /* 4889 * Generic 32-bit binary operation. Provide an "instr" line that 4890 * specifies an instruction that performs "result = a0 op a1". 4891 * This could be a MIPS instruction or a function call. (If the result 4892 * comes back in a register other than a0, you can override "result".) 4893 * 4894 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4895 * vCC (a1). Useful for integer division and modulus. Note that we 4896 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4897 * handles it correctly. 4898 * 4899 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4900 * xor-int, shl-int, shr-int, ushr-int 4901 */ 4902 /* binop vAA, vBB, vCC */ 4903 FETCH(a0, 1) # a0 <- CCBB 4904 GET_OPA(rOBJ) # rOBJ <- AA 4905 srl a3, a0, 8 # a3 <- CC 4906 and a2, a0, 255 # a2 <- BB 4907 GET_VREG(a1, a3) # a1 <- vCC 4908 GET_VREG(a0, a2) # a0 <- vBB 4909 .if 1 4910 # is second operand zero? 4911 beqz a1, common_errDivideByZero 4912 .endif 4913 4914 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4915 # optional op 4916 div zero, a0, a1; mflo a0 # a0 <- op, a0-a3 changed 4917 GET_INST_OPCODE(t0) # extract opcode from rINST 4918 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4919 /* 11-14 instructions */ 4920 4921 4922 4923 /* ------------------------------ */ 4924 .balign 128 4925 .L_OP_REM_INT: /* 0x94 */ 4926 /* File: mips/OP_REM_INT.S */ 4927 /* File: mips/binop.S */ 4928 /* 4929 * Generic 32-bit binary operation. Provide an "instr" line that 4930 * specifies an instruction that performs "result = a0 op a1". 4931 * This could be a MIPS instruction or a function call. (If the result 4932 * comes back in a register other than a0, you can override "result".) 4933 * 4934 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4935 * vCC (a1). Useful for integer division and modulus. Note that we 4936 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4937 * handles it correctly. 4938 * 4939 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4940 * xor-int, shl-int, shr-int, ushr-int 4941 */ 4942 /* binop vAA, vBB, vCC */ 4943 FETCH(a0, 1) # a0 <- CCBB 4944 GET_OPA(rOBJ) # rOBJ <- AA 4945 srl a3, a0, 8 # a3 <- CC 4946 and a2, a0, 255 # a2 <- BB 4947 GET_VREG(a1, a3) # a1 <- vCC 4948 GET_VREG(a0, a2) # a0 <- vBB 4949 .if 1 4950 # is second operand zero? 4951 beqz a1, common_errDivideByZero 4952 .endif 4953 4954 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4955 # optional op 4956 div zero, a0, a1; mfhi a0 # a0 <- op, a0-a3 changed 4957 GET_INST_OPCODE(t0) # extract opcode from rINST 4958 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4959 /* 11-14 instructions */ 4960 4961 4962 4963 /* ------------------------------ */ 4964 .balign 128 4965 .L_OP_AND_INT: /* 0x95 */ 4966 /* File: mips/OP_AND_INT.S */ 4967 /* File: mips/binop.S */ 4968 /* 4969 * Generic 32-bit binary operation. Provide an "instr" line that 4970 * specifies an instruction that performs "result = a0 op a1". 4971 * This could be a MIPS instruction or a function call. (If the result 4972 * comes back in a register other than a0, you can override "result".) 4973 * 4974 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4975 * vCC (a1). Useful for integer division and modulus. Note that we 4976 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4977 * handles it correctly. 4978 * 4979 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4980 * xor-int, shl-int, shr-int, ushr-int 4981 */ 4982 /* binop vAA, vBB, vCC */ 4983 FETCH(a0, 1) # a0 <- CCBB 4984 GET_OPA(rOBJ) # rOBJ <- AA 4985 srl a3, a0, 8 # a3 <- CC 4986 and a2, a0, 255 # a2 <- BB 4987 GET_VREG(a1, a3) # a1 <- vCC 4988 GET_VREG(a0, a2) # a0 <- vBB 4989 .if 0 4990 # is second operand zero? 4991 beqz a1, common_errDivideByZero 4992 .endif 4993 4994 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4995 # optional op 4996 and a0, a0, a1 # a0 <- op, a0-a3 changed 4997 GET_INST_OPCODE(t0) # extract opcode from rINST 4998 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4999 /* 11-14 instructions */ 5000 5001 5002 5003 /* ------------------------------ */ 5004 .balign 128 5005 .L_OP_OR_INT: /* 0x96 */ 5006 /* File: mips/OP_OR_INT.S */ 5007 /* File: mips/binop.S */ 5008 /* 5009 * Generic 32-bit binary operation. Provide an "instr" line that 5010 * specifies an instruction that performs "result = a0 op a1". 5011 * This could be a MIPS instruction or a function call. (If the result 5012 * comes back in a register other than a0, you can override "result".) 5013 * 5014 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5015 * vCC (a1). Useful for integer division and modulus. Note that we 5016 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5017 * handles it correctly. 5018 * 5019 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5020 * xor-int, shl-int, shr-int, ushr-int 5021 */ 5022 /* binop vAA, vBB, vCC */ 5023 FETCH(a0, 1) # a0 <- CCBB 5024 GET_OPA(rOBJ) # rOBJ <- AA 5025 srl a3, a0, 8 # a3 <- CC 5026 and a2, a0, 255 # a2 <- BB 5027 GET_VREG(a1, a3) # a1 <- vCC 5028 GET_VREG(a0, a2) # a0 <- vBB 5029 .if 0 5030 # is second operand zero? 5031 beqz a1, common_errDivideByZero 5032 .endif 5033 5034 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5035 # optional op 5036 or a0, a0, a1 # a0 <- op, a0-a3 changed 5037 GET_INST_OPCODE(t0) # extract opcode from rINST 5038 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5039 /* 11-14 instructions */ 5040 5041 5042 5043 /* ------------------------------ */ 5044 .balign 128 5045 .L_OP_XOR_INT: /* 0x97 */ 5046 /* File: mips/OP_XOR_INT.S */ 5047 /* File: mips/binop.S */ 5048 /* 5049 * Generic 32-bit binary operation. Provide an "instr" line that 5050 * specifies an instruction that performs "result = a0 op a1". 5051 * This could be a MIPS instruction or a function call. (If the result 5052 * comes back in a register other than a0, you can override "result".) 5053 * 5054 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5055 * vCC (a1). Useful for integer division and modulus. Note that we 5056 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5057 * handles it correctly. 5058 * 5059 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5060 * xor-int, shl-int, shr-int, ushr-int 5061 */ 5062 /* binop vAA, vBB, vCC */ 5063 FETCH(a0, 1) # a0 <- CCBB 5064 GET_OPA(rOBJ) # rOBJ <- AA 5065 srl a3, a0, 8 # a3 <- CC 5066 and a2, a0, 255 # a2 <- BB 5067 GET_VREG(a1, a3) # a1 <- vCC 5068 GET_VREG(a0, a2) # a0 <- vBB 5069 .if 0 5070 # is second operand zero? 5071 beqz a1, common_errDivideByZero 5072 .endif 5073 5074 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5075 # optional op 5076 xor a0, a0, a1 # a0 <- op, a0-a3 changed 5077 GET_INST_OPCODE(t0) # extract opcode from rINST 5078 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5079 /* 11-14 instructions */ 5080 5081 5082 5083 /* ------------------------------ */ 5084 .balign 128 5085 .L_OP_SHL_INT: /* 0x98 */ 5086 /* File: mips/OP_SHL_INT.S */ 5087 /* File: mips/binop.S */ 5088 /* 5089 * Generic 32-bit binary operation. Provide an "instr" line that 5090 * specifies an instruction that performs "result = a0 op a1". 5091 * This could be a MIPS instruction or a function call. (If the result 5092 * comes back in a register other than a0, you can override "result".) 5093 * 5094 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5095 * vCC (a1). Useful for integer division and modulus. Note that we 5096 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5097 * handles it correctly. 5098 * 5099 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5100 * xor-int, shl-int, shr-int, ushr-int 5101 */ 5102 /* binop vAA, vBB, vCC */ 5103 FETCH(a0, 1) # a0 <- CCBB 5104 GET_OPA(rOBJ) # rOBJ <- AA 5105 srl a3, a0, 8 # a3 <- CC 5106 and a2, a0, 255 # a2 <- BB 5107 GET_VREG(a1, a3) # a1 <- vCC 5108 GET_VREG(a0, a2) # a0 <- vBB 5109 .if 0 5110 # is second operand zero? 5111 beqz a1, common_errDivideByZero 5112 .endif 5113 5114 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5115 and a1, a1, 31 # optional op 5116 sll a0, a0, a1 # a0 <- op, a0-a3 changed 5117 GET_INST_OPCODE(t0) # extract opcode from rINST 5118 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5119 /* 11-14 instructions */ 5120 5121 5122 5123 /* ------------------------------ */ 5124 .balign 128 5125 .L_OP_SHR_INT: /* 0x99 */ 5126 /* File: mips/OP_SHR_INT.S */ 5127 /* File: mips/binop.S */ 5128 /* 5129 * Generic 32-bit binary operation. Provide an "instr" line that 5130 * specifies an instruction that performs "result = a0 op a1". 5131 * This could be a MIPS instruction or a function call. (If the result 5132 * comes back in a register other than a0, you can override "result".) 5133 * 5134 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5135 * vCC (a1). Useful for integer division and modulus. Note that we 5136 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5137 * handles it correctly. 5138 * 5139 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5140 * xor-int, shl-int, shr-int, ushr-int 5141 */ 5142 /* binop vAA, vBB, vCC */ 5143 FETCH(a0, 1) # a0 <- CCBB 5144 GET_OPA(rOBJ) # rOBJ <- AA 5145 srl a3, a0, 8 # a3 <- CC 5146 and a2, a0, 255 # a2 <- BB 5147 GET_VREG(a1, a3) # a1 <- vCC 5148 GET_VREG(a0, a2) # a0 <- vBB 5149 .if 0 5150 # is second operand zero? 5151 beqz a1, common_errDivideByZero 5152 .endif 5153 5154 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5155 and a1, a1, 31 # optional op 5156 sra a0, a0, a1 # a0 <- op, a0-a3 changed 5157 GET_INST_OPCODE(t0) # extract opcode from rINST 5158 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5159 /* 11-14 instructions */ 5160 5161 5162 5163 /* ------------------------------ */ 5164 .balign 128 5165 .L_OP_USHR_INT: /* 0x9a */ 5166 /* File: mips/OP_USHR_INT.S */ 5167 /* File: mips/binop.S */ 5168 /* 5169 * Generic 32-bit binary operation. Provide an "instr" line that 5170 * specifies an instruction that performs "result = a0 op a1". 5171 * This could be a MIPS instruction or a function call. (If the result 5172 * comes back in a register other than a0, you can override "result".) 5173 * 5174 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5175 * vCC (a1). Useful for integer division and modulus. Note that we 5176 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5177 * handles it correctly. 5178 * 5179 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5180 * xor-int, shl-int, shr-int, ushr-int 5181 */ 5182 /* binop vAA, vBB, vCC */ 5183 FETCH(a0, 1) # a0 <- CCBB 5184 GET_OPA(rOBJ) # rOBJ <- AA 5185 srl a3, a0, 8 # a3 <- CC 5186 and a2, a0, 255 # a2 <- BB 5187 GET_VREG(a1, a3) # a1 <- vCC 5188 GET_VREG(a0, a2) # a0 <- vBB 5189 .if 0 5190 # is second operand zero? 5191 beqz a1, common_errDivideByZero 5192 .endif 5193 5194 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5195 and a1, a1, 31 # optional op 5196 srl a0, a0, a1 # a0 <- op, a0-a3 changed 5197 GET_INST_OPCODE(t0) # extract opcode from rINST 5198 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5199 /* 11-14 instructions */ 5200 5201 5202 5203 /* ------------------------------ */ 5204 .balign 128 5205 .L_OP_ADD_LONG: /* 0x9b */ 5206 /* File: mips/OP_ADD_LONG.S */ 5207 /* 5208 * The compiler generates the following sequence for 5209 * [v1 v0] = [a1 a0] + [a3 a2]; 5210 * addu v0,a2,a0 5211 * addu a1,a3,a1 5212 * sltu v1,v0,a2 5213 * addu v1,v1,a1 5214 */ 5215 /* File: mips/binopWide.S */ 5216 /* 5217 * Generic 64-bit binary operation. Provide an "instr" line that 5218 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5219 * This could be a MIPS instruction or a function call. (If the result 5220 * comes back in a register other than a0, you can override "result".) 5221 * 5222 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5223 * vCC (a1). Useful for integer division and modulus. 5224 * 5225 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5226 * xor-long 5227 * 5228 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5229 */ 5230 /* binop vAA, vBB, vCC */ 5231 FETCH(a0, 1) # a0 <- CCBB 5232 GET_OPA(rOBJ) # rOBJ <- AA 5233 and a2, a0, 255 # a2 <- BB 5234 srl a3, a0, 8 # a3 <- CC 5235 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[AA] 5236 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5237 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5238 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5239 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5240 .if 0 5241 or t0, a2, a3 # second arg (a2-a3) is zero? 5242 beqz t0, common_errDivideByZero 5243 .endif 5244 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5245 5246 addu v0, a2, a0 # optional op 5247 addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed 5248 GET_INST_OPCODE(t0) # extract opcode from rINST 5249 STORE64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 5250 GOTO_OPCODE(t0) # jump to next instruction 5251 /* 14-17 instructions */ 5252 5253 5254 5255 /* ------------------------------ */ 5256 .balign 128 5257 .L_OP_SUB_LONG: /* 0x9c */ 5258 /* File: mips/OP_SUB_LONG.S */ 5259 /* 5260 * For little endian the code sequence looks as follows: 5261 * subu v0,a0,a2 5262 * subu v1,a1,a3 5263 * sltu a0,a0,v0 5264 * subu v1,v1,a0 5265 */ 5266 /* File: mips/binopWide.S */ 5267 /* 5268 * Generic 64-bit binary operation. Provide an "instr" line that 5269 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5270 * This could be a MIPS instruction or a function call. (If the result 5271 * comes back in a register other than a0, you can override "result".) 5272 * 5273 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5274 * vCC (a1). Useful for integer division and modulus. 5275 * 5276 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5277 * xor-long 5278 * 5279 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5280 */ 5281 /* binop vAA, vBB, vCC */ 5282 FETCH(a0, 1) # a0 <- CCBB 5283 GET_OPA(rOBJ) # rOBJ <- AA 5284 and a2, a0, 255 # a2 <- BB 5285 srl a3, a0, 8 # a3 <- CC 5286 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[AA] 5287 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5288 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5289 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5290 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5291 .if 0 5292 or t0, a2, a3 # second arg (a2-a3) is zero? 5293 beqz t0, common_errDivideByZero 5294 .endif 5295 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5296 5297 subu v0, a0, a2 # optional op 5298 subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed 5299 GET_INST_OPCODE(t0) # extract opcode from rINST 5300 STORE64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 5301 GOTO_OPCODE(t0) # jump to next instruction 5302 /* 14-17 instructions */ 5303 5304 5305 5306 5307 /* ------------------------------ */ 5308 .balign 128 5309 .L_OP_MUL_LONG: /* 0x9d */ 5310 /* File: mips/OP_MUL_LONG.S */ 5311 /* 5312 * Signed 64-bit integer multiply. 5313 * a1 a0 5314 * x a3 a2 5315 * ------------- 5316 * a2a1 a2a0 5317 * a3a0 5318 * a3a1 (<= unused) 5319 * --------------- 5320 * v1 v0 5321 */ 5322 /* mul-long vAA, vBB, vCC */ 5323 FETCH(a0, 1) # a0 <- CCBB 5324 and t0, a0, 255 # a2 <- BB 5325 srl t1, a0, 8 # a3 <- CC 5326 EAS2(t0, rFP, t0) # t0 <- &fp[BB] 5327 LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1 5328 5329 EAS2(t1, rFP, t1) # t0 <- &fp[CC] 5330 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5331 5332 mul v1, a3, a0 # v1= a3a0 5333 multu a2, a0 5334 mfhi t1 5335 mflo v0 # v0= a2a0 5336 mul t0, a2, a1 # t0= a2a1 5337 addu v1, v1, t1 # v1+= hi(a2a0) 5338 addu v1, v1, t0 # v1= a3a0 + a2a1; 5339 5340 GET_OPA(a0) # a0 <- AA 5341 EAS2(a0, rFP, a0) # a0 <- &fp[A] 5342 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5343 b .LOP_MUL_LONG_finish 5344 5345 /* ------------------------------ */ 5346 .balign 128 5347 .L_OP_DIV_LONG: /* 0x9e */ 5348 /* File: mips/OP_DIV_LONG.S */ 5349 #ifdef HAVE_LITTLE_ENDIAN 5350 /* File: mips/binopWide.S */ 5351 /* 5352 * Generic 64-bit binary operation. Provide an "instr" line that 5353 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5354 * This could be a MIPS instruction or a function call. (If the result 5355 * comes back in a register other than a0, you can override "result".) 5356 * 5357 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5358 * vCC (a1). Useful for integer division and modulus. 5359 * 5360 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5361 * xor-long 5362 * 5363 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5364 */ 5365 /* binop vAA, vBB, vCC */ 5366 FETCH(a0, 1) # a0 <- CCBB 5367 GET_OPA(rOBJ) # rOBJ <- AA 5368 and a2, a0, 255 # a2 <- BB 5369 srl a3, a0, 8 # a3 <- CC 5370 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[AA] 5371 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5372 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5373 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5374 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5375 .if 1 5376 or t0, a2, a3 # second arg (a2-a3) is zero? 5377 beqz t0, common_errDivideByZero 5378 .endif 5379 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5380 5381 # optional op 5382 JAL(__divdi3) # result <- op, a0-a3 changed 5383 GET_INST_OPCODE(t0) # extract opcode from rINST 5384 STORE64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 5385 GOTO_OPCODE(t0) # jump to next instruction 5386 /* 14-17 instructions */ 5387 5388 5389 #else 5390 /* File: mips/binopWide.S */ 5391 /* 5392 * Generic 64-bit binary operation. Provide an "instr" line that 5393 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5394 * This could be a MIPS instruction or a function call. (If the result 5395 * comes back in a register other than a0, you can override "result".) 5396 * 5397 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5398 * vCC (a1). Useful for integer division and modulus. 5399 * 5400 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5401 * xor-long 5402 * 5403 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5404 */ 5405 /* binop vAA, vBB, vCC */ 5406 FETCH(a0, 1) # a0 <- CCBB 5407 GET_OPA(rOBJ) # rOBJ <- AA 5408 and a2, a0, 255 # a2 <- BB 5409 srl a3, a0, 8 # a3 <- CC 5410 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[AA] 5411 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5412 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5413 LOAD64(a1, a0, a2) # a0/a1 <- vBB/vBB+1 5414 LOAD64(a3, a2, t1) # a2/a3 <- vCC/vCC+1 5415 .if 1 5416 or t0, a3, a2 # second arg (a2-a3) is zero? 5417 beqz t0, common_errDivideByZero 5418 .endif 5419 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5420 5421 # optional op 5422 JAL(__divdi3) # result <- op, a0-a3 changed 5423 GET_INST_OPCODE(t0) # extract opcode from rINST 5424 STORE64(v1, v0, rOBJ) # vAA/vAA+1 <- v1/v0 5425 GOTO_OPCODE(t0) # jump to next instruction 5426 /* 14-17 instructions */ 5427 5428 5429 #endif 5430 5431 /* ------------------------------ */ 5432 .balign 128 5433 .L_OP_REM_LONG: /* 0x9f */ 5434 /* File: mips/OP_REM_LONG.S */ 5435 /* ldivmod returns quotient in a0/a1 and remainder in a2/a3 */ 5436 #ifdef HAVE_LITTLE_ENDIAN 5437 /* File: mips/binopWide.S */ 5438 /* 5439 * Generic 64-bit binary operation. Provide an "instr" line that 5440 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5441 * This could be a MIPS instruction or a function call. (If the result 5442 * comes back in a register other than a0, you can override "result".) 5443 * 5444 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5445 * vCC (a1). Useful for integer division and modulus. 5446 * 5447 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5448 * xor-long 5449 * 5450 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5451 */ 5452 /* binop vAA, vBB, vCC */ 5453 FETCH(a0, 1) # a0 <- CCBB 5454 GET_OPA(rOBJ) # rOBJ <- AA 5455 and a2, a0, 255 # a2 <- BB 5456 srl a3, a0, 8 # a3 <- CC 5457 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[AA] 5458 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5459 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5460 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5461 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5462 .if 1 5463 or t0, a2, a3 # second arg (a2-a3) is zero? 5464 beqz t0, common_errDivideByZero 5465 .endif 5466 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5467 5468 # optional op 5469 JAL(__moddi3) # result <- op, a0-a3 changed 5470 GET_INST_OPCODE(t0) # extract opcode from rINST 5471 STORE64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 5472 GOTO_OPCODE(t0) # jump to next instruction 5473 /* 14-17 instructions */ 5474 5475 5476 #else 5477 /* File: mips/binopWide.S */ 5478 /* 5479 * Generic 64-bit binary operation. Provide an "instr" line that 5480 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5481 * This could be a MIPS instruction or a function call. (If the result 5482 * comes back in a register other than a0, you can override "result".) 5483 * 5484 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5485 * vCC (a1). Useful for integer division and modulus. 5486 * 5487 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5488 * xor-long 5489 * 5490 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5491 */ 5492 /* binop vAA, vBB, vCC */ 5493 FETCH(a0, 1) # a0 <- CCBB 5494 GET_OPA(rOBJ) # rOBJ <- AA 5495 and a2, a0, 255 # a2 <- BB 5496 srl a3, a0, 8 # a3 <- CC 5497 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[AA] 5498 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5499 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5500 LOAD64(a1, a0, a2) # a0/a1 <- vBB/vBB+1 5501 LOAD64(a3, a2, t1) # a2/a3 <- vCC/vCC+1 5502 .if 1 5503 or t0, a3, a2 # second arg (a2-a3) is zero? 5504 beqz t0, common_errDivideByZero 5505 .endif 5506 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5507 5508 # optional op 5509 JAL(__moddi3) # result <- op, a0-a3 changed 5510 GET_INST_OPCODE(t0) # extract opcode from rINST 5511 STORE64(v1, v0, rOBJ) # vAA/vAA+1 <- v1/v0 5512 GOTO_OPCODE(t0) # jump to next instruction 5513 /* 14-17 instructions */ 5514 5515 5516 #endif 5517 5518 /* ------------------------------ */ 5519 .balign 128 5520 .L_OP_AND_LONG: /* 0xa0 */ 5521 /* File: mips/OP_AND_LONG.S */ 5522 /* File: mips/binopWide.S */ 5523 /* 5524 * Generic 64-bit binary operation. Provide an "instr" line that 5525 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5526 * This could be a MIPS instruction or a function call. (If the result 5527 * comes back in a register other than a0, you can override "result".) 5528 * 5529 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5530 * vCC (a1). Useful for integer division and modulus. 5531 * 5532 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5533 * xor-long 5534 * 5535 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5536 */ 5537 /* binop vAA, vBB, vCC */ 5538 FETCH(a0, 1) # a0 <- CCBB 5539 GET_OPA(rOBJ) # rOBJ <- AA 5540 and a2, a0, 255 # a2 <- BB 5541 srl a3, a0, 8 # a3 <- CC 5542 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[AA] 5543 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5544 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5545 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5546 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5547 .if 0 5548 or t0, a2, a3 # second arg (a2-a3) is zero? 5549 beqz t0, common_errDivideByZero 5550 .endif 5551 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5552 5553 and a0, a0, a2 # optional op 5554 and a1, a1, a3 # result <- op, a0-a3 changed 5555 GET_INST_OPCODE(t0) # extract opcode from rINST 5556 STORE64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1 5557 GOTO_OPCODE(t0) # jump to next instruction 5558 /* 14-17 instructions */ 5559 5560 5561 5562 /* ------------------------------ */ 5563 .balign 128 5564 .L_OP_OR_LONG: /* 0xa1 */ 5565 /* File: mips/OP_OR_LONG.S */ 5566 /* File: mips/binopWide.S */ 5567 /* 5568 * Generic 64-bit binary operation. Provide an "instr" line that 5569 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5570 * This could be a MIPS instruction or a function call. (If the result 5571 * comes back in a register other than a0, you can override "result".) 5572 * 5573 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5574 * vCC (a1). Useful for integer division and modulus. 5575 * 5576 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5577 * xor-long 5578 * 5579 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5580 */ 5581 /* binop vAA, vBB, vCC */ 5582 FETCH(a0, 1) # a0 <- CCBB 5583 GET_OPA(rOBJ) # rOBJ <- AA 5584 and a2, a0, 255 # a2 <- BB 5585 srl a3, a0, 8 # a3 <- CC 5586 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[AA] 5587 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5588 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5589 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5590 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5591 .if 0 5592 or t0, a2, a3 # second arg (a2-a3) is zero? 5593 beqz t0, common_errDivideByZero 5594 .endif 5595 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5596 5597 or a0, a0, a2 # optional op 5598 or a1, a1, a3 # result <- op, a0-a3 changed 5599 GET_INST_OPCODE(t0) # extract opcode from rINST 5600 STORE64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1 5601 GOTO_OPCODE(t0) # jump to next instruction 5602 /* 14-17 instructions */ 5603 5604 5605 5606 /* ------------------------------ */ 5607 .balign 128 5608 .L_OP_XOR_LONG: /* 0xa2 */ 5609 /* File: mips/OP_XOR_LONG.S */ 5610 /* File: mips/binopWide.S */ 5611 /* 5612 * Generic 64-bit binary operation. Provide an "instr" line that 5613 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5614 * This could be a MIPS instruction or a function call. (If the result 5615 * comes back in a register other than a0, you can override "result".) 5616 * 5617 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5618 * vCC (a1). Useful for integer division and modulus. 5619 * 5620 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5621 * xor-long 5622 * 5623 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5624 */ 5625 /* binop vAA, vBB, vCC */ 5626 FETCH(a0, 1) # a0 <- CCBB 5627 GET_OPA(rOBJ) # rOBJ <- AA 5628 and a2, a0, 255 # a2 <- BB 5629 srl a3, a0, 8 # a3 <- CC 5630 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[AA] 5631 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5632 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5633 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5634 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5635 .if 0 5636 or t0, a2, a3 # second arg (a2-a3) is zero? 5637 beqz t0, common_errDivideByZero 5638 .endif 5639 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5640 5641 xor a0, a0, a2 # optional op 5642 xor a1, a1, a3 # result <- op, a0-a3 changed 5643 GET_INST_OPCODE(t0) # extract opcode from rINST 5644 STORE64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1 5645 GOTO_OPCODE(t0) # jump to next instruction 5646 /* 14-17 instructions */ 5647 5648 5649 5650 /* ------------------------------ */ 5651 .balign 128 5652 .L_OP_SHL_LONG: /* 0xa3 */ 5653 /* File: mips/OP_SHL_LONG.S */ 5654 /* 5655 * Long integer shift. This is different from the generic 32/64-bit 5656 * binary operations because vAA/vBB are 64-bit but vCC (the shift 5657 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 5658 * 6 bits of the shift distance. 5659 */ 5660 /* shl-long vAA, vBB, vCC */ 5661 FETCH(a0, 1) # a0 <- CCBB 5662 GET_OPA(t2) # t2 <- AA 5663 and a3, a0, 255 # a3 <- BB 5664 srl a0, a0, 8 # a0 <- CC 5665 EAS2(a3, rFP, a3) # a3 <- &fp[BB] 5666 GET_VREG(a2, a0) # a2 <- vCC 5667 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 5668 5669 EAS2(t2, rFP, t2) # t2 <- &fp[AA] 5670 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5671 5672 sll v0, a0, a2 # rlo<- alo << (shift&31) 5673 not v1, a2 # rhi<- 31-shift (shift is 5b) 5674 srl a0, 1 5675 srl a0, v1 # alo<- alo >> (32-(shift&31)) 5676 sll v1, a1, a2 # rhi<- ahi << (shift&31) 5677 or v1, a0 # rhi<- rhi | alo 5678 andi a2, 0x20 # shift< shift & 0x20 5679 movn v1, v0, a2 # rhi<- rlo (if shift&0x20) 5680 movn v0, zero, a2 # rlo<- 0 (if shift&0x20) 5681 5682 GET_INST_OPCODE(t0) # extract opcode from rINST 5683 STORE64(v0, v1, t2) # vAA/vAA+1 <- a0/a1 5684 GOTO_OPCODE(t0) # jump to next instruction 5685 5686 5687 /* ------------------------------ */ 5688 .balign 128 5689 .L_OP_SHR_LONG: /* 0xa4 */ 5690 /* File: mips/OP_SHR_LONG.S */ 5691 /* 5692 * Long integer shift. This is different from the generic 32/64-bit 5693 * binary operations because vAA/vBB are 64-bit but vCC (the shift 5694 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 5695 * 6 bits of the shift distance. 5696 */ 5697 /* shr-long vAA, vBB, vCC */ 5698 FETCH(a0, 1) # a0 <- CCBB 5699 GET_OPA(t3) # t3 <- AA 5700 and a3, a0, 255 # a3 <- BB 5701 srl a0, a0, 8 # a0 <- CC 5702 EAS2(a3, rFP, a3) # a3 <- &fp[BB] 5703 GET_VREG(a2, a0) # a2 <- vCC 5704 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 5705 EAS2(t3, rFP, t3) # t3 <- &fp[AA] 5706 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5707 5708 sra v1, a1, a2 # rhi<- ahi >> (shift&31) 5709 srl v0, a0, a2 # rlo<- alo >> (shift&31) 5710 sra a3, a1, 31 # a3<- sign(ah) 5711 not a0, a2 # alo<- 31-shift (shift is 5b) 5712 sll a1, 1 5713 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 5714 or v0, a1 # rlo<- rlo | ahi 5715 andi a2, 0x20 # shift & 0x20 5716 movn v0, v1, a2 # rlo<- rhi (if shift&0x20) 5717 movn v1, a3, a2 # rhi<- sign(ahi) (if shift&0x20) 5718 5719 STORE64(v0, v1, t3) # vAA/VAA+1 <- v0/v0 5720 GET_INST_OPCODE(t0) # extract opcode from rINST 5721 GOTO_OPCODE(t0) # jump to next instruction 5722 5723 5724 /* ------------------------------ */ 5725 .balign 128 5726 .L_OP_USHR_LONG: /* 0xa5 */ 5727 /* File: mips/OP_USHR_LONG.S */ 5728 /* 5729 * Long integer shift. This is different from the generic 32/64-bit 5730 * binary operations because vAA/vBB are 64-bit but vCC (the shift 5731 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 5732 * 6 bits of the shift distance. 5733 */ 5734 /* ushr-long vAA, vBB, vCC */ 5735 FETCH(a0, 1) # a0 <- CCBB 5736 GET_OPA(t0) # t3 <- AA 5737 and a3, a0, 255 # a3 <- BB 5738 srl a0, a0, 8 # a0 <- CC 5739 EAS2(a3, rFP, a3) # a3 <- &fp[BB] 5740 GET_VREG(a2, a0) # a2 <- vCC 5741 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 5742 EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA] 5743 5744 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5745 srl v1, a1, a2 # rhi<- ahi >> (shift&31) 5746 srl v0, a0, a2 # rlo<- alo >> (shift&31) 5747 not a0, a2 # alo<- 31-n (shift is 5b) 5748 sll a1, 1 5749 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 5750 or v0, a1 # rlo<- rlo | ahi 5751 andi a2, 0x20 # shift & 0x20 5752 movn v0, v1, a2 # rlo<- rhi (if shift&0x20) 5753 movn v1, zero, a2 # rhi<- 0 (if shift&0x20) 5754 5755 STORE64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 5756 GET_INST_OPCODE(t0) # extract opcode from rINST 5757 GOTO_OPCODE(t0) # jump to next instruction 5758 5759 5760 /* ------------------------------ */ 5761 .balign 128 5762 .L_OP_ADD_FLOAT: /* 0xa6 */ 5763 /* File: mips/OP_ADD_FLOAT.S */ 5764 /* File: mips/binflop.S */ 5765 /* 5766 * Generic 32-bit binary float operation. 5767 * 5768 * For: add-fp, sub-fp, mul-fp, div-fp 5769 */ 5770 5771 /* binop vAA, vBB, vCC */ 5772 FETCH(a0, 1) # a0 <- CCBB 5773 GET_OPA(rOBJ) # s5 <- AA 5774 srl a3, a0, 8 # a3 <- CC 5775 and a2, a0, 255 # a2 <- BB 5776 #ifdef SOFT_FLOAT 5777 GET_VREG(a1, a3) # a1 <- vCC 5778 GET_VREG(a0, a2) # a0 <- vBB 5779 .if 0 5780 # is second operand zero? 5781 beqz a1, common_errDivideByZero 5782 .endif 5783 #else 5784 GET_VREG_F(fa1, a3) # a1 <- vCC 5785 GET_VREG_F(fa0, a2) # a0 <- vBB 5786 5787 .if 0 5788 # is second operand zero? 5789 li.s ft0, 0 5790 c.eq.s fcc0, ft0, fa1 # condition bit and comparision with 0 5791 bc1t fcc0, common_errDivideByZero 5792 .endif 5793 #endif 5794 5795 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5796 # optional op 5797 #ifdef SOFT_FLOAT 5798 JAL(__addsf3) # v0 = result 5799 SET_VREG(v0, rOBJ) # vAA <- v0 5800 #else 5801 add.s fv0, fa0, fa1 # f0 = result 5802 SET_VREG_F(fv0, rOBJ) # vAA <- fv0 5803 #endif 5804 GET_INST_OPCODE(t0) # extract opcode from rINST 5805 GOTO_OPCODE(t0) # jump to next instruction 5806 /* 11-14 instructions */ 5807 5808 5809 5810 /* ------------------------------ */ 5811 .balign 128 5812 .L_OP_SUB_FLOAT: /* 0xa7 */ 5813 /* File: mips/OP_SUB_FLOAT.S */ 5814 /* File: mips/binflop.S */ 5815 /* 5816 * Generic 32-bit binary float operation. 5817 * 5818 * For: add-fp, sub-fp, mul-fp, div-fp 5819 */ 5820 5821 /* binop vAA, vBB, vCC */ 5822 FETCH(a0, 1) # a0 <- CCBB 5823 GET_OPA(rOBJ) # s5 <- AA 5824 srl a3, a0, 8 # a3 <- CC 5825 and a2, a0, 255 # a2 <- BB 5826 #ifdef SOFT_FLOAT 5827 GET_VREG(a1, a3) # a1 <- vCC 5828 GET_VREG(a0, a2) # a0 <- vBB 5829 .if 0 5830 # is second operand zero? 5831 beqz a1, common_errDivideByZero 5832 .endif 5833 #else 5834 GET_VREG_F(fa1, a3) # a1 <- vCC 5835 GET_VREG_F(fa0, a2) # a0 <- vBB 5836 5837 .if 0 5838 # is second operand zero? 5839 li.s ft0, 0 5840 c.eq.s fcc0, ft0, fa1 # condition bit and comparision with 0 5841 bc1t fcc0, common_errDivideByZero 5842 .endif 5843 #endif 5844 5845 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5846 # optional op 5847 #ifdef SOFT_FLOAT 5848 JAL(__subsf3) # v0 = result 5849 SET_VREG(v0, rOBJ) # vAA <- v0 5850 #else 5851 sub.s fv0, fa0, fa1 # f0 = result 5852 SET_VREG_F(fv0, rOBJ) # vAA <- fv0 5853 #endif 5854 GET_INST_OPCODE(t0) # extract opcode from rINST 5855 GOTO_OPCODE(t0) # jump to next instruction 5856 /* 11-14 instructions */ 5857 5858 5859 5860 /* ------------------------------ */ 5861 .balign 128 5862 .L_OP_MUL_FLOAT: /* 0xa8 */ 5863 /* File: mips/OP_MUL_FLOAT.S */ 5864 /* File: mips/binflop.S */ 5865 /* 5866 * Generic 32-bit binary float operation. 5867 * 5868 * For: add-fp, sub-fp, mul-fp, div-fp 5869 */ 5870 5871 /* binop vAA, vBB, vCC */ 5872 FETCH(a0, 1) # a0 <- CCBB 5873 GET_OPA(rOBJ) # s5 <- AA 5874 srl a3, a0, 8 # a3 <- CC 5875 and a2, a0, 255 # a2 <- BB 5876 #ifdef SOFT_FLOAT 5877 GET_VREG(a1, a3) # a1 <- vCC 5878 GET_VREG(a0, a2) # a0 <- vBB 5879 .if 0 5880 # is second operand zero? 5881 beqz a1, common_errDivideByZero 5882 .endif 5883 #else 5884 GET_VREG_F(fa1, a3) # a1 <- vCC 5885 GET_VREG_F(fa0, a2) # a0 <- vBB 5886 5887 .if 0 5888 # is second operand zero? 5889 li.s ft0, 0 5890 c.eq.s fcc0, ft0, fa1 # condition bit and comparision with 0 5891 bc1t fcc0, common_errDivideByZero 5892 .endif 5893 #endif 5894 5895 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5896 # optional op 5897 #ifdef SOFT_FLOAT 5898 JAL(__mulsf3) # v0 = result 5899 SET_VREG(v0, rOBJ) # vAA <- v0 5900 #else 5901 mul.s fv0, fa0, fa1 # f0 = result 5902 SET_VREG_F(fv0, rOBJ) # vAA <- fv0 5903 #endif 5904 GET_INST_OPCODE(t0) # extract opcode from rINST 5905 GOTO_OPCODE(t0) # jump to next instruction 5906 /* 11-14 instructions */ 5907 5908 5909 5910 /* ------------------------------ */ 5911 .balign 128 5912 .L_OP_DIV_FLOAT: /* 0xa9 */ 5913 /* File: mips/OP_DIV_FLOAT.S */ 5914 /* File: mips/binflop.S */ 5915 /* 5916 * Generic 32-bit binary float operation. 5917 * 5918 * For: add-fp, sub-fp, mul-fp, div-fp 5919 */ 5920 5921 /* binop vAA, vBB, vCC */ 5922 FETCH(a0, 1) # a0 <- CCBB 5923 GET_OPA(rOBJ) # s5 <- AA 5924 srl a3, a0, 8 # a3 <- CC 5925 and a2, a0, 255 # a2 <- BB 5926 #ifdef SOFT_FLOAT 5927 GET_VREG(a1, a3) # a1 <- vCC 5928 GET_VREG(a0, a2) # a0 <- vBB 5929 .if 0 5930 # is second operand zero? 5931 beqz a1, common_errDivideByZero 5932 .endif 5933 #else 5934 GET_VREG_F(fa1, a3) # a1 <- vCC 5935 GET_VREG_F(fa0, a2) # a0 <- vBB 5936 5937 .if 0 5938 # is second operand zero? 5939 li.s ft0, 0 5940 c.eq.s fcc0, ft0, fa1 # condition bit and comparision with 0 5941 bc1t fcc0, common_errDivideByZero 5942 .endif 5943 #endif 5944 5945 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5946 # optional op 5947 #ifdef SOFT_FLOAT 5948 JAL(__divsf3) # v0 = result 5949 SET_VREG(v0, rOBJ) # vAA <- v0 5950 #else 5951 div.s fv0, fa0, fa1 # f0 = result 5952 SET_VREG_F(fv0, rOBJ) # vAA <- fv0 5953 #endif 5954 GET_INST_OPCODE(t0) # extract opcode from rINST 5955 GOTO_OPCODE(t0) # jump to next instruction 5956 /* 11-14 instructions */ 5957 5958 5959 5960 /* ------------------------------ */ 5961 .balign 128 5962 .L_OP_REM_FLOAT: /* 0xaa */ 5963 /* File: mips/OP_REM_FLOAT.S */ 5964 /* File: mips/binflop.S */ 5965 /* 5966 * Generic 32-bit binary float operation. 5967 * 5968 * For: add-fp, sub-fp, mul-fp, div-fp 5969 */ 5970 5971 /* binop vAA, vBB, vCC */ 5972 FETCH(a0, 1) # a0 <- CCBB 5973 GET_OPA(rOBJ) # s5 <- AA 5974 srl a3, a0, 8 # a3 <- CC 5975 and a2, a0, 255 # a2 <- BB 5976 #ifdef SOFT_FLOAT 5977 GET_VREG(a1, a3) # a1 <- vCC 5978 GET_VREG(a0, a2) # a0 <- vBB 5979 .if 0 5980 # is second operand zero? 5981 beqz a1, common_errDivideByZero 5982 .endif 5983 #else 5984 GET_VREG_F(fa1, a3) # a1 <- vCC 5985 GET_VREG_F(fa0, a2) # a0 <- vBB 5986 5987 .if 0 5988 # is second operand zero? 5989 li.s ft0, 0 5990 c.eq.s fcc0, ft0, fa1 # condition bit and comparision with 0 5991 bc1t fcc0, common_errDivideByZero 5992 .endif 5993 #endif 5994 5995 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5996 # optional op 5997 #ifdef SOFT_FLOAT 5998 JAL(fmodf) # v0 = result 5999 SET_VREG(v0, rOBJ) # vAA <- v0 6000 #else 6001 JAL(fmodf) # f0 = result 6002 SET_VREG_F(fv0, rOBJ) # vAA <- fv0 6003 #endif 6004 GET_INST_OPCODE(t0) # extract opcode from rINST 6005 GOTO_OPCODE(t0) # jump to next instruction 6006 /* 11-14 instructions */ 6007 6008 6009 6010 /* ------------------------------ */ 6011 .balign 128 6012 .L_OP_ADD_DOUBLE: /* 0xab */ 6013 /* File: mips/OP_ADD_DOUBLE.S */ 6014 /* File: mips/binflopWide.S */ 6015 /* 6016 * Generic 64-bit binary operation. Provide an "instr" line that 6017 * specifies an instruction that performs "result = a0-a1 op a2-a3". 6018 * This could be an MIPS instruction or a function call. 6019 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6020 * vCC (a1). Useful for integer division and modulus. 6021 * 6022 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 6023 * xor-long, add-double, sub-double, mul-double, div-double, 6024 * rem-double 6025 * 6026 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 6027 */ 6028 /* binop vAA, vBB, vCC */ 6029 FETCH(a0, 1) # a0 <- CCBB 6030 GET_OPA(rOBJ) # s5 <- AA 6031 and a2, a0, 255 # a2 <- BB 6032 srl a3, a0, 8 # a3 <- CC 6033 EAS2(rOBJ, rFP, rOBJ) # s5 <- &fp[AA] 6034 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 6035 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 6036 #ifdef SOFT_FLOAT 6037 LOAD64(rARG0, rARG1, a2) # a0/a1 <- vBB/vBB+1 6038 LOAD64(rARG2, rARG3, t1) # a2/a3 <- vCC/vCC+1 6039 .if 0 6040 or t0, rARG2, rARG3 # second arg (a2-a3) is zero? 6041 beqz t0, common_errDivideByZero 6042 .endif 6043 #else 6044 LOAD64_F(fa0, fa0f, a2) 6045 LOAD64_F(fa1, fa1f, t1) 6046 .if 0 6047 li.d ft0, 0 6048 c.eq.d fcc0, fa1, ft0 6049 bc1t fcc0, common_errDivideByZero 6050 .endif 6051 #endif 6052 1: 6053 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6054 # optional op 6055 #ifdef SOFT_FLOAT 6056 JAL(__adddf3) # result <- op, a0-a3 changed 6057 STORE64(rRESULT0, rRESULT1, rOBJ) 6058 #else 6059 add.d fv0, fa0, fa1 6060 STORE64_F(fv0, fv0f, rOBJ) 6061 #endif 6062 GET_INST_OPCODE(t0) # extract opcode from rINST 6063 GOTO_OPCODE(t0) # jump to next instruction 6064 /* 14-17 instructions */ 6065 6066 6067 6068 /* ------------------------------ */ 6069 .balign 128 6070 .L_OP_SUB_DOUBLE: /* 0xac */ 6071 /* File: mips/OP_SUB_DOUBLE.S */ 6072 /* File: mips/binflopWide.S */ 6073 /* 6074 * Generic 64-bit binary operation. Provide an "instr" line that 6075 * specifies an instruction that performs "result = a0-a1 op a2-a3". 6076 * This could be an MIPS instruction or a function call. 6077 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6078 * vCC (a1). Useful for integer division and modulus. 6079 * 6080 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 6081 * xor-long, add-double, sub-double, mul-double, div-double, 6082 * rem-double 6083 * 6084 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 6085 */ 6086 /* binop vAA, vBB, vCC */ 6087 FETCH(a0, 1) # a0 <- CCBB 6088 GET_OPA(rOBJ) # s5 <- AA 6089 and a2, a0, 255 # a2 <- BB 6090 srl a3, a0, 8 # a3 <- CC 6091 EAS2(rOBJ, rFP, rOBJ) # s5 <- &fp[AA] 6092 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 6093 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 6094 #ifdef SOFT_FLOAT 6095 LOAD64(rARG0, rARG1, a2) # a0/a1 <- vBB/vBB+1 6096 LOAD64(rARG2, rARG3, t1) # a2/a3 <- vCC/vCC+1 6097 .if 0 6098 or t0, rARG2, rARG3 # second arg (a2-a3) is zero? 6099 beqz t0, common_errDivideByZero 6100 .endif 6101 #else 6102 LOAD64_F(fa0, fa0f, a2) 6103 LOAD64_F(fa1, fa1f, t1) 6104 .if 0 6105 li.d ft0, 0 6106 c.eq.d fcc0, fa1, ft0 6107 bc1t fcc0, common_errDivideByZero 6108 .endif 6109 #endif 6110 1: 6111 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6112 # optional op 6113 #ifdef SOFT_FLOAT 6114 JAL(__subdf3) # result <- op, a0-a3 changed 6115 STORE64(rRESULT0, rRESULT1, rOBJ) 6116 #else 6117 sub.d fv0, fa0, fa1 6118 STORE64_F(fv0, fv0f, rOBJ) 6119 #endif 6120 GET_INST_OPCODE(t0) # extract opcode from rINST 6121 GOTO_OPCODE(t0) # jump to next instruction 6122 /* 14-17 instructions */ 6123 6124 6125 6126 /* ------------------------------ */ 6127 .balign 128 6128 .L_OP_MUL_DOUBLE: /* 0xad */ 6129 /* File: mips/OP_MUL_DOUBLE.S */ 6130 /* File: mips/binflopWide.S */ 6131 /* 6132 * Generic 64-bit binary operation. Provide an "instr" line that 6133 * specifies an instruction that performs "result = a0-a1 op a2-a3". 6134 * This could be an MIPS instruction or a function call. 6135 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6136 * vCC (a1). Useful for integer division and modulus. 6137 * 6138 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 6139 * xor-long, add-double, sub-double, mul-double, div-double, 6140 * rem-double 6141 * 6142 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 6143 */ 6144 /* binop vAA, vBB, vCC */ 6145 FETCH(a0, 1) # a0 <- CCBB 6146 GET_OPA(rOBJ) # s5 <- AA 6147 and a2, a0, 255 # a2 <- BB 6148 srl a3, a0, 8 # a3 <- CC 6149 EAS2(rOBJ, rFP, rOBJ) # s5 <- &fp[AA] 6150 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 6151 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 6152 #ifdef SOFT_FLOAT 6153 LOAD64(rARG0, rARG1, a2) # a0/a1 <- vBB/vBB+1 6154 LOAD64(rARG2, rARG3, t1) # a2/a3 <- vCC/vCC+1 6155 .if 0 6156 or t0, rARG2, rARG3 # second arg (a2-a3) is zero? 6157 beqz t0, common_errDivideByZero 6158 .endif 6159 #else 6160 LOAD64_F(fa0, fa0f, a2) 6161 LOAD64_F(fa1, fa1f, t1) 6162 .if 0 6163 li.d ft0, 0 6164 c.eq.d fcc0, fa1, ft0 6165 bc1t fcc0, common_errDivideByZero 6166 .endif 6167 #endif 6168 1: 6169 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6170 # optional op 6171 #ifdef SOFT_FLOAT 6172 JAL(__muldf3) # result <- op, a0-a3 changed 6173 STORE64(rRESULT0, rRESULT1, rOBJ) 6174 #else 6175 mul.d fv0, fa0, fa1 6176 STORE64_F(fv0, fv0f, rOBJ) 6177 #endif 6178 GET_INST_OPCODE(t0) # extract opcode from rINST 6179 GOTO_OPCODE(t0) # jump to next instruction 6180 /* 14-17 instructions */ 6181 6182 6183 6184 /* ------------------------------ */ 6185 .balign 128 6186 .L_OP_DIV_DOUBLE: /* 0xae */ 6187 /* File: mips/OP_DIV_DOUBLE.S */ 6188 /* File: mips/binflopWide.S */ 6189 /* 6190 * Generic 64-bit binary operation. Provide an "instr" line that 6191 * specifies an instruction that performs "result = a0-a1 op a2-a3". 6192 * This could be an MIPS instruction or a function call. 6193 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6194 * vCC (a1). Useful for integer division and modulus. 6195 * 6196 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 6197 * xor-long, add-double, sub-double, mul-double, div-double, 6198 * rem-double 6199 * 6200 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 6201 */ 6202 /* binop vAA, vBB, vCC */ 6203 FETCH(a0, 1) # a0 <- CCBB 6204 GET_OPA(rOBJ) # s5 <- AA 6205 and a2, a0, 255 # a2 <- BB 6206 srl a3, a0, 8 # a3 <- CC 6207 EAS2(rOBJ, rFP, rOBJ) # s5 <- &fp[AA] 6208 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 6209 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 6210 #ifdef SOFT_FLOAT 6211 LOAD64(rARG0, rARG1, a2) # a0/a1 <- vBB/vBB+1 6212 LOAD64(rARG2, rARG3, t1) # a2/a3 <- vCC/vCC+1 6213 .if 0 6214 or t0, rARG2, rARG3 # second arg (a2-a3) is zero? 6215 beqz t0, common_errDivideByZero 6216 .endif 6217 #else 6218 LOAD64_F(fa0, fa0f, a2) 6219 LOAD64_F(fa1, fa1f, t1) 6220 .if 0 6221 li.d ft0, 0 6222 c.eq.d fcc0, fa1, ft0 6223 bc1t fcc0, common_errDivideByZero 6224 .endif 6225 #endif 6226 1: 6227 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6228 # optional op 6229 #ifdef SOFT_FLOAT 6230 JAL(__divdf3) # result <- op, a0-a3 changed 6231 STORE64(rRESULT0, rRESULT1, rOBJ) 6232 #else 6233 div.d fv0, fa0, fa1 6234 STORE64_F(fv0, fv0f, rOBJ) 6235 #endif 6236 GET_INST_OPCODE(t0) # extract opcode from rINST 6237 GOTO_OPCODE(t0) # jump to next instruction 6238 /* 14-17 instructions */ 6239 6240 6241 6242 /* ------------------------------ */ 6243 .balign 128 6244 .L_OP_REM_DOUBLE: /* 0xaf */ 6245 /* File: mips/OP_REM_DOUBLE.S */ 6246 /* File: mips/binflopWide.S */ 6247 /* 6248 * Generic 64-bit binary operation. Provide an "instr" line that 6249 * specifies an instruction that performs "result = a0-a1 op a2-a3". 6250 * This could be an MIPS instruction or a function call. 6251 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6252 * vCC (a1). Useful for integer division and modulus. 6253 * 6254 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 6255 * xor-long, add-double, sub-double, mul-double, div-double, 6256 * rem-double 6257 * 6258 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 6259 */ 6260 /* binop vAA, vBB, vCC */ 6261 FETCH(a0, 1) # a0 <- CCBB 6262 GET_OPA(rOBJ) # s5 <- AA 6263 and a2, a0, 255 # a2 <- BB 6264 srl a3, a0, 8 # a3 <- CC 6265 EAS2(rOBJ, rFP, rOBJ) # s5 <- &fp[AA] 6266 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 6267 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 6268 #ifdef SOFT_FLOAT 6269 LOAD64(rARG0, rARG1, a2) # a0/a1 <- vBB/vBB+1 6270 LOAD64(rARG2, rARG3, t1) # a2/a3 <- vCC/vCC+1 6271 .if 0 6272 or t0, rARG2, rARG3 # second arg (a2-a3) is zero? 6273 beqz t0, common_errDivideByZero 6274 .endif 6275 #else 6276 LOAD64_F(fa0, fa0f, a2) 6277 LOAD64_F(fa1, fa1f, t1) 6278 .if 0 6279 li.d ft0, 0 6280 c.eq.d fcc0, fa1, ft0 6281 bc1t fcc0, common_errDivideByZero 6282 .endif 6283 #endif 6284 1: 6285 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6286 # optional op 6287 #ifdef SOFT_FLOAT 6288 JAL(fmod) # result <- op, a0-a3 changed 6289 STORE64(rRESULT0, rRESULT1, rOBJ) 6290 #else 6291 JAL(fmod) 6292 STORE64_F(fv0, fv0f, rOBJ) 6293 #endif 6294 GET_INST_OPCODE(t0) # extract opcode from rINST 6295 GOTO_OPCODE(t0) # jump to next instruction 6296 /* 14-17 instructions */ 6297 6298 6299 6300 /* ------------------------------ */ 6301 .balign 128 6302 .L_OP_ADD_INT_2ADDR: /* 0xb0 */ 6303 /* File: mips/OP_ADD_INT_2ADDR.S */ 6304 /* File: mips/binop2addr.S */ 6305 /* 6306 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6307 * that specifies an instruction that performs "result = a0 op a1". 6308 * This could be an MIPS instruction or a function call. 6309 * 6310 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6311 * vCC (a1). Useful for integer division and modulus. 6312 * 6313 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6314 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6315 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6316 */ 6317 /* binop/2addr vA, vB */ 6318 GET_OPA4(rOBJ) # rOBJ <- A+ 6319 GET_OPB(a3) # a3 <- B 6320 GET_VREG(a0, rOBJ) # a0 <- vA 6321 GET_VREG(a1, a3) # a1 <- vB 6322 .if 0 6323 # is second operand zero? 6324 beqz a1, common_errDivideByZero 6325 .endif 6326 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6327 6328 # optional op 6329 addu a0, a0, a1 # a0 <- op, a0-a3 changed 6330 GET_INST_OPCODE(t0) # extract opcode from rINST 6331 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6332 /* 10-13 instructions */ 6333 6334 6335 6336 /* ------------------------------ */ 6337 .balign 128 6338 .L_OP_SUB_INT_2ADDR: /* 0xb1 */ 6339 /* File: mips/OP_SUB_INT_2ADDR.S */ 6340 /* File: mips/binop2addr.S */ 6341 /* 6342 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6343 * that specifies an instruction that performs "result = a0 op a1". 6344 * This could be an MIPS instruction or a function call. 6345 * 6346 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6347 * vCC (a1). Useful for integer division and modulus. 6348 * 6349 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6350 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6351 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6352 */ 6353 /* binop/2addr vA, vB */ 6354 GET_OPA4(rOBJ) # rOBJ <- A+ 6355 GET_OPB(a3) # a3 <- B 6356 GET_VREG(a0, rOBJ) # a0 <- vA 6357 GET_VREG(a1, a3) # a1 <- vB 6358 .if 0 6359 # is second operand zero? 6360 beqz a1, common_errDivideByZero 6361 .endif 6362 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6363 6364 # optional op 6365 subu a0, a0, a1 # a0 <- op, a0-a3 changed 6366 GET_INST_OPCODE(t0) # extract opcode from rINST 6367 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6368 /* 10-13 instructions */ 6369 6370 6371 6372 /* ------------------------------ */ 6373 .balign 128 6374 .L_OP_MUL_INT_2ADDR: /* 0xb2 */ 6375 /* File: mips/OP_MUL_INT_2ADDR.S */ 6376 /* File: mips/binop2addr.S */ 6377 /* 6378 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6379 * that specifies an instruction that performs "result = a0 op a1". 6380 * This could be an MIPS instruction or a function call. 6381 * 6382 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6383 * vCC (a1). Useful for integer division and modulus. 6384 * 6385 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6386 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6387 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6388 */ 6389 /* binop/2addr vA, vB */ 6390 GET_OPA4(rOBJ) # rOBJ <- A+ 6391 GET_OPB(a3) # a3 <- B 6392 GET_VREG(a0, rOBJ) # a0 <- vA 6393 GET_VREG(a1, a3) # a1 <- vB 6394 .if 0 6395 # is second operand zero? 6396 beqz a1, common_errDivideByZero 6397 .endif 6398 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6399 6400 # optional op 6401 mul a0, a0, a1 # a0 <- op, a0-a3 changed 6402 GET_INST_OPCODE(t0) # extract opcode from rINST 6403 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6404 /* 10-13 instructions */ 6405 6406 6407 6408 /* ------------------------------ */ 6409 .balign 128 6410 .L_OP_DIV_INT_2ADDR: /* 0xb3 */ 6411 /* File: mips/OP_DIV_INT_2ADDR.S */ 6412 /* File: mips/binop2addr.S */ 6413 /* 6414 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6415 * that specifies an instruction that performs "result = a0 op a1". 6416 * This could be an MIPS instruction or a function call. 6417 * 6418 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6419 * vCC (a1). Useful for integer division and modulus. 6420 * 6421 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6422 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6423 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6424 */ 6425 /* binop/2addr vA, vB */ 6426 GET_OPA4(rOBJ) # rOBJ <- A+ 6427 GET_OPB(a3) # a3 <- B 6428 GET_VREG(a0, rOBJ) # a0 <- vA 6429 GET_VREG(a1, a3) # a1 <- vB 6430 .if 1 6431 # is second operand zero? 6432 beqz a1, common_errDivideByZero 6433 .endif 6434 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6435 6436 # optional op 6437 div zero, a0, a1; mflo a0 # a0 <- op, a0-a3 changed 6438 GET_INST_OPCODE(t0) # extract opcode from rINST 6439 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6440 /* 10-13 instructions */ 6441 6442 6443 6444 /* ------------------------------ */ 6445 .balign 128 6446 .L_OP_REM_INT_2ADDR: /* 0xb4 */ 6447 /* File: mips/OP_REM_INT_2ADDR.S */ 6448 /* File: mips/binop2addr.S */ 6449 /* 6450 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6451 * that specifies an instruction that performs "result = a0 op a1". 6452 * This could be an MIPS instruction or a function call. 6453 * 6454 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6455 * vCC (a1). Useful for integer division and modulus. 6456 * 6457 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6458 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6459 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6460 */ 6461 /* binop/2addr vA, vB */ 6462 GET_OPA4(rOBJ) # rOBJ <- A+ 6463 GET_OPB(a3) # a3 <- B 6464 GET_VREG(a0, rOBJ) # a0 <- vA 6465 GET_VREG(a1, a3) # a1 <- vB 6466 .if 1 6467 # is second operand zero? 6468 beqz a1, common_errDivideByZero 6469 .endif 6470 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6471 6472 # optional op 6473 div zero, a0, a1; mfhi a0 # a0 <- op, a0-a3 changed 6474 GET_INST_OPCODE(t0) # extract opcode from rINST 6475 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6476 /* 10-13 instructions */ 6477 6478 6479 6480 /* ------------------------------ */ 6481 .balign 128 6482 .L_OP_AND_INT_2ADDR: /* 0xb5 */ 6483 /* File: mips/OP_AND_INT_2ADDR.S */ 6484 /* File: mips/binop2addr.S */ 6485 /* 6486 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6487 * that specifies an instruction that performs "result = a0 op a1". 6488 * This could be an MIPS instruction or a function call. 6489 * 6490 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6491 * vCC (a1). Useful for integer division and modulus. 6492 * 6493 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6494 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6495 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6496 */ 6497 /* binop/2addr vA, vB */ 6498 GET_OPA4(rOBJ) # rOBJ <- A+ 6499 GET_OPB(a3) # a3 <- B 6500 GET_VREG(a0, rOBJ) # a0 <- vA 6501 GET_VREG(a1, a3) # a1 <- vB 6502 .if 0 6503 # is second operand zero? 6504 beqz a1, common_errDivideByZero 6505 .endif 6506 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6507 6508 # optional op 6509 and a0, a0, a1 # a0 <- op, a0-a3 changed 6510 GET_INST_OPCODE(t0) # extract opcode from rINST 6511 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6512 /* 10-13 instructions */ 6513 6514 6515 6516 /* ------------------------------ */ 6517 .balign 128 6518 .L_OP_OR_INT_2ADDR: /* 0xb6 */ 6519 /* File: mips/OP_OR_INT_2ADDR.S */ 6520 /* File: mips/binop2addr.S */ 6521 /* 6522 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6523 * that specifies an instruction that performs "result = a0 op a1". 6524 * This could be an MIPS instruction or a function call. 6525 * 6526 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6527 * vCC (a1). Useful for integer division and modulus. 6528 * 6529 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6530 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6531 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6532 */ 6533 /* binop/2addr vA, vB */ 6534 GET_OPA4(rOBJ) # rOBJ <- A+ 6535 GET_OPB(a3) # a3 <- B 6536 GET_VREG(a0, rOBJ) # a0 <- vA 6537 GET_VREG(a1, a3) # a1 <- vB 6538 .if 0 6539 # is second operand zero? 6540 beqz a1, common_errDivideByZero 6541 .endif 6542 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6543 6544 # optional op 6545 or a0, a0, a1 # a0 <- op, a0-a3 changed 6546 GET_INST_OPCODE(t0) # extract opcode from rINST 6547 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6548 /* 10-13 instructions */ 6549 6550 6551 6552 /* ------------------------------ */ 6553 .balign 128 6554 .L_OP_XOR_INT_2ADDR: /* 0xb7 */ 6555 /* File: mips/OP_XOR_INT_2ADDR.S */ 6556 /* File: mips/binop2addr.S */ 6557 /* 6558 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6559 * that specifies an instruction that performs "result = a0 op a1". 6560 * This could be an MIPS instruction or a function call. 6561 * 6562 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6563 * vCC (a1). Useful for integer division and modulus. 6564 * 6565 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6566 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6567 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6568 */ 6569 /* binop/2addr vA, vB */ 6570 GET_OPA4(rOBJ) # rOBJ <- A+ 6571 GET_OPB(a3) # a3 <- B 6572 GET_VREG(a0, rOBJ) # a0 <- vA 6573 GET_VREG(a1, a3) # a1 <- vB 6574 .if 0 6575 # is second operand zero? 6576 beqz a1, common_errDivideByZero 6577 .endif 6578 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6579 6580 # optional op 6581 xor a0, a0, a1 # a0 <- op, a0-a3 changed 6582 GET_INST_OPCODE(t0) # extract opcode from rINST 6583 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6584 /* 10-13 instructions */ 6585 6586 6587 6588 /* ------------------------------ */ 6589 .balign 128 6590 .L_OP_SHL_INT_2ADDR: /* 0xb8 */ 6591 /* File: mips/OP_SHL_INT_2ADDR.S */ 6592 /* File: mips/binop2addr.S */ 6593 /* 6594 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6595 * that specifies an instruction that performs "result = a0 op a1". 6596 * This could be an MIPS instruction or a function call. 6597 * 6598 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6599 * vCC (a1). Useful for integer division and modulus. 6600 * 6601 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6602 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6603 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6604 */ 6605 /* binop/2addr vA, vB */ 6606 GET_OPA4(rOBJ) # rOBJ <- A+ 6607 GET_OPB(a3) # a3 <- B 6608 GET_VREG(a0, rOBJ) # a0 <- vA 6609 GET_VREG(a1, a3) # a1 <- vB 6610 .if 0 6611 # is second operand zero? 6612 beqz a1, common_errDivideByZero 6613 .endif 6614 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6615 6616 and a1, a1, 31 # optional op 6617 sll a0, a0, a1 # a0 <- op, a0-a3 changed 6618 GET_INST_OPCODE(t0) # extract opcode from rINST 6619 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6620 /* 10-13 instructions */ 6621 6622 6623 6624 /* ------------------------------ */ 6625 .balign 128 6626 .L_OP_SHR_INT_2ADDR: /* 0xb9 */ 6627 /* File: mips/OP_SHR_INT_2ADDR.S */ 6628 /* File: mips/binop2addr.S */ 6629 /* 6630 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6631 * that specifies an instruction that performs "result = a0 op a1". 6632 * This could be an MIPS instruction or a function call. 6633 * 6634 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6635 * vCC (a1). Useful for integer division and modulus. 6636 * 6637 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6638 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6639 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6640 */ 6641 /* binop/2addr vA, vB */ 6642 GET_OPA4(rOBJ) # rOBJ <- A+ 6643 GET_OPB(a3) # a3 <- B 6644 GET_VREG(a0, rOBJ) # a0 <- vA 6645 GET_VREG(a1, a3) # a1 <- vB 6646 .if 0 6647 # is second operand zero? 6648 beqz a1, common_errDivideByZero 6649 .endif 6650 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6651 6652 and a1, a1, 31 # optional op 6653 sra a0, a0, a1 # a0 <- op, a0-a3 changed 6654 GET_INST_OPCODE(t0) # extract opcode from rINST 6655 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6656 /* 10-13 instructions */ 6657 6658 6659 6660 /* ------------------------------ */ 6661 .balign 128 6662 .L_OP_USHR_INT_2ADDR: /* 0xba */ 6663 /* File: mips/OP_USHR_INT_2ADDR.S */ 6664 /* File: mips/binop2addr.S */ 6665 /* 6666 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6667 * that specifies an instruction that performs "result = a0 op a1". 6668 * This could be an MIPS instruction or a function call. 6669 * 6670 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6671 * vCC (a1). Useful for integer division and modulus. 6672 * 6673 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6674 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6675 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6676 */ 6677 /* binop/2addr vA, vB */ 6678 GET_OPA4(rOBJ) # rOBJ <- A+ 6679 GET_OPB(a3) # a3 <- B 6680 GET_VREG(a0, rOBJ) # a0 <- vA 6681 GET_VREG(a1, a3) # a1 <- vB 6682 .if 0 6683 # is second operand zero? 6684 beqz a1, common_errDivideByZero 6685 .endif 6686 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6687 6688 and a1, a1, 31 # optional op 6689 srl a0, a0, a1 # a0 <- op, a0-a3 changed 6690 GET_INST_OPCODE(t0) # extract opcode from rINST 6691 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6692 /* 10-13 instructions */ 6693 6694 6695 6696 /* ------------------------------ */ 6697 .balign 128 6698 .L_OP_ADD_LONG_2ADDR: /* 0xbb */ 6699 /* File: mips/OP_ADD_LONG_2ADDR.S */ 6700 /* 6701 *See OP_ADD_LONG.S for details 6702 */ 6703 /* File: mips/binopWide2addr.S */ 6704 /* 6705 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6706 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6707 * This could be a MIPS instruction or a function call. (If the result 6708 * comes back in a register other than a0, you can override "result".) 6709 * 6710 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6711 * vCC (a1). Useful for integer division and modulus. 6712 * 6713 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6714 * and-long/2addr, or-long/2addr, xor-long/2addr 6715 * rem-double/2addr 6716 */ 6717 /* binop/2addr vA, vB */ 6718 GET_OPA4(rOBJ) # rOBJ <- A+ 6719 GET_OPB(a1) # a1 <- B 6720 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6721 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 6722 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6723 LOAD64(a0, a1, rOBJ) # a0/a1 <- vAA/vAA+1 6724 .if 0 6725 or t0, a2, a3 # second arg (a2-a3) is zero? 6726 beqz t0, common_errDivideByZero 6727 .endif 6728 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6729 6730 addu v0, a2, a0 # optional op 6731 addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed 6732 GET_INST_OPCODE(t0) # extract opcode from rINST 6733 STORE64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 6734 GOTO_OPCODE(t0) # jump to next instruction 6735 /* 12-15 instructions */ 6736 6737 6738 6739 /* ------------------------------ */ 6740 .balign 128 6741 .L_OP_SUB_LONG_2ADDR: /* 0xbc */ 6742 /* File: mips/OP_SUB_LONG_2ADDR.S */ 6743 /* 6744 * See comments in OP_SUB_LONG.S 6745 */ 6746 /* File: mips/binopWide2addr.S */ 6747 /* 6748 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6749 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6750 * This could be a MIPS instruction or a function call. (If the result 6751 * comes back in a register other than a0, you can override "result".) 6752 * 6753 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6754 * vCC (a1). Useful for integer division and modulus. 6755 * 6756 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6757 * and-long/2addr, or-long/2addr, xor-long/2addr 6758 * rem-double/2addr 6759 */ 6760 /* binop/2addr vA, vB */ 6761 GET_OPA4(rOBJ) # rOBJ <- A+ 6762 GET_OPB(a1) # a1 <- B 6763 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6764 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 6765 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6766 LOAD64(a0, a1, rOBJ) # a0/a1 <- vAA/vAA+1 6767 .if 0 6768 or t0, a2, a3 # second arg (a2-a3) is zero? 6769 beqz t0, common_errDivideByZero 6770 .endif 6771 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6772 6773 subu v0, a0, a2 # optional op 6774 subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed 6775 GET_INST_OPCODE(t0) # extract opcode from rINST 6776 STORE64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 6777 GOTO_OPCODE(t0) # jump to next instruction 6778 /* 12-15 instructions */ 6779 6780 6781 6782 /* ------------------------------ */ 6783 .balign 128 6784 .L_OP_MUL_LONG_2ADDR: /* 0xbd */ 6785 /* File: mips/OP_MUL_LONG_2ADDR.S */ 6786 /* 6787 * See comments in OP_MUL_LONG.S 6788 */ 6789 /* mul-long/2addr vA, vB */ 6790 GET_OPA4(t0) # t0 <- A+ 6791 6792 EAS2(t0, rFP, t0) # t0 <- &fp[A] 6793 LOAD64(a0, a1, t0) # vAA.low / high 6794 6795 GET_OPB(t1) # t1 <- B 6796 EAS2(t1, rFP, t1) # t1 <- &fp[B] 6797 LOAD64(a2, a3, t1) # vBB.low / high 6798 6799 mul v1, a3, a0 # v1= a3a0 6800 multu a2, a0 6801 mfhi t1 6802 mflo v0 # v0= a2a0 6803 mul t2, a2, a1 # t2= a2a1 6804 addu v1, v1, t1 # v1= a3a0 + hi(a2a0) 6805 addu v1, v1, t2 # v1= v1 + a2a1; 6806 6807 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6808 GET_INST_OPCODE(t1) # extract opcode from rINST 6809 # vAA <- v0 (low) 6810 STORE64(v0, v1, t0) # vAA+1 <- v1 (high) 6811 GOTO_OPCODE(t1) # jump to next instruction 6812 6813 6814 /* ------------------------------ */ 6815 .balign 128 6816 .L_OP_DIV_LONG_2ADDR: /* 0xbe */ 6817 /* File: mips/OP_DIV_LONG_2ADDR.S */ 6818 #ifdef HAVE_LITTLE_ENDIAN 6819 /* File: mips/binopWide2addr.S */ 6820 /* 6821 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6822 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6823 * This could be a MIPS instruction or a function call. (If the result 6824 * comes back in a register other than a0, you can override "result".) 6825 * 6826 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6827 * vCC (a1). Useful for integer division and modulus. 6828 * 6829 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6830 * and-long/2addr, or-long/2addr, xor-long/2addr 6831 * rem-double/2addr 6832 */ 6833 /* binop/2addr vA, vB */ 6834 GET_OPA4(rOBJ) # rOBJ <- A+ 6835 GET_OPB(a1) # a1 <- B 6836 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6837 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 6838 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6839 LOAD64(a0, a1, rOBJ) # a0/a1 <- vAA/vAA+1 6840 .if 1 6841 or t0, a2, a3 # second arg (a2-a3) is zero? 6842 beqz t0, common_errDivideByZero 6843 .endif 6844 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6845 6846 # optional op 6847 JAL(__divdi3) # result <- op, a0-a3 changed 6848 GET_INST_OPCODE(t0) # extract opcode from rINST 6849 STORE64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 6850 GOTO_OPCODE(t0) # jump to next instruction 6851 /* 12-15 instructions */ 6852 6853 6854 #else 6855 /* File: mips/binopWide2addr.S */ 6856 /* 6857 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6858 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6859 * This could be a MIPS instruction or a function call. (If the result 6860 * comes back in a register other than a0, you can override "result".) 6861 * 6862 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6863 * vCC (a1). Useful for integer division and modulus. 6864 * 6865 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6866 * and-long/2addr, or-long/2addr, xor-long/2addr 6867 * rem-double/2addr 6868 */ 6869 /* binop/2addr vA, vB */ 6870 GET_OPA4(rOBJ) # rOBJ <- A+ 6871 GET_OPB(a1) # a1 <- B 6872 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6873 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 6874 LOAD64(a3, a2, a1) # a2/a3 <- vBB/vBB+1 6875 LOAD64(a1, a0, rOBJ) # a0/a1 <- vAA/vAA+1 6876 .if 1 6877 or t0, a3, a2 # second arg (a2-a3) is zero? 6878 beqz t0, common_errDivideByZero 6879 .endif 6880 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6881 6882 # optional op 6883 JAL(__divdi3) # result <- op, a0-a3 changed 6884 GET_INST_OPCODE(t0) # extract opcode from rINST 6885 STORE64(v1, v0, rOBJ) # vAA/vAA+1 <- v1/v0 6886 GOTO_OPCODE(t0) # jump to next instruction 6887 /* 12-15 instructions */ 6888 6889 6890 #endif 6891 6892 /* ------------------------------ */ 6893 .balign 128 6894 .L_OP_REM_LONG_2ADDR: /* 0xbf */ 6895 /* File: mips/OP_REM_LONG_2ADDR.S */ 6896 #ifdef HAVE_LITTLE_ENDIAN 6897 /* File: mips/binopWide2addr.S */ 6898 /* 6899 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6900 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6901 * This could be a MIPS instruction or a function call. (If the result 6902 * comes back in a register other than a0, you can override "result".) 6903 * 6904 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6905 * vCC (a1). Useful for integer division and modulus. 6906 * 6907 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6908 * and-long/2addr, or-long/2addr, xor-long/2addr 6909 * rem-double/2addr 6910 */ 6911 /* binop/2addr vA, vB */ 6912 GET_OPA4(rOBJ) # rOBJ <- A+ 6913 GET_OPB(a1) # a1 <- B 6914 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6915 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 6916 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6917 LOAD64(a0, a1, rOBJ) # a0/a1 <- vAA/vAA+1 6918 .if 1 6919 or t0, a2, a3 # second arg (a2-a3) is zero? 6920 beqz t0, common_errDivideByZero 6921 .endif 6922 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6923 6924 # optional op 6925 JAL(__moddi3) # result <- op, a0-a3 changed 6926 GET_INST_OPCODE(t0) # extract opcode from rINST 6927 STORE64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 6928 GOTO_OPCODE(t0) # jump to next instruction 6929 /* 12-15 instructions */ 6930 6931 6932 #else 6933 /* File: mips/binopWide2addr.S */ 6934 /* 6935 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6936 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6937 * This could be a MIPS instruction or a function call. (If the result 6938 * comes back in a register other than a0, you can override "result".) 6939 * 6940 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6941 * vCC (a1). Useful for integer division and modulus. 6942 * 6943 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6944 * and-long/2addr, or-long/2addr, xor-long/2addr 6945 * rem-double/2addr 6946 */ 6947 /* binop/2addr vA, vB */ 6948 GET_OPA4(rOBJ) # rOBJ <- A+ 6949 GET_OPB(a1) # a1 <- B 6950 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6951 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 6952 LOAD64(a3, a2, a1) # a2/a3 <- vBB/vBB+1 6953 LOAD64(a1, a0, rOBJ) # a0/a1 <- vAA/vAA+1 6954 .if 1 6955 or t0, a3, a2 # second arg (a2-a3) is zero? 6956 beqz t0, common_errDivideByZero 6957 .endif 6958 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6959 6960 # optional op 6961 JAL(__moddi3) # result <- op, a0-a3 changed 6962 GET_INST_OPCODE(t0) # extract opcode from rINST 6963 STORE64(v1, v0, rOBJ) # vAA/vAA+1 <- v1/v0 6964 GOTO_OPCODE(t0) # jump to next instruction 6965 /* 12-15 instructions */ 6966 6967 6968 #endif 6969 6970 /* ------------------------------ */ 6971 .balign 128 6972 .L_OP_AND_LONG_2ADDR: /* 0xc0 */ 6973 /* File: mips/OP_AND_LONG_2ADDR.S */ 6974 /* File: mips/binopWide2addr.S */ 6975 /* 6976 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6977 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6978 * This could be a MIPS instruction or a function call. (If the result 6979 * comes back in a register other than a0, you can override "result".) 6980 * 6981 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6982 * vCC (a1). Useful for integer division and modulus. 6983 * 6984 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6985 * and-long/2addr, or-long/2addr, xor-long/2addr 6986 * rem-double/2addr 6987 */ 6988 /* binop/2addr vA, vB */ 6989 GET_OPA4(rOBJ) # rOBJ <- A+ 6990 GET_OPB(a1) # a1 <- B 6991 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6992 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 6993 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6994 LOAD64(a0, a1, rOBJ) # a0/a1 <- vAA/vAA+1 6995 .if 0 6996 or t0, a2, a3 # second arg (a2-a3) is zero? 6997 beqz t0, common_errDivideByZero 6998 .endif 6999 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7000 7001 and a0, a0, a2 # optional op 7002 and a1, a1, a3 # result <- op, a0-a3 changed 7003 GET_INST_OPCODE(t0) # extract opcode from rINST 7004 STORE64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1 7005 GOTO_OPCODE(t0) # jump to next instruction 7006 /* 12-15 instructions */ 7007 7008 7009 7010 /* ------------------------------ */ 7011 .balign 128 7012 .L_OP_OR_LONG_2ADDR: /* 0xc1 */ 7013 /* File: mips/OP_OR_LONG_2ADDR.S */ 7014 /* File: mips/binopWide2addr.S */ 7015 /* 7016 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 7017 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 7018 * This could be a MIPS instruction or a function call. (If the result 7019 * comes back in a register other than a0, you can override "result".) 7020 * 7021 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7022 * vCC (a1). Useful for integer division and modulus. 7023 * 7024 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 7025 * and-long/2addr, or-long/2addr, xor-long/2addr 7026 * rem-double/2addr 7027 */ 7028 /* binop/2addr vA, vB */ 7029 GET_OPA4(rOBJ) # rOBJ <- A+ 7030 GET_OPB(a1) # a1 <- B 7031 EAS2(a1, rFP, a1) # a1 <- &fp[B] 7032 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 7033 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 7034 LOAD64(a0, a1, rOBJ) # a0/a1 <- vAA/vAA+1 7035 .if 0 7036 or t0, a2, a3 # second arg (a2-a3) is zero? 7037 beqz t0, common_errDivideByZero 7038 .endif 7039 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7040 7041 or a0, a0, a2 # optional op 7042 or a1, a1, a3 # result <- op, a0-a3 changed 7043 GET_INST_OPCODE(t0) # extract opcode from rINST 7044 STORE64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1 7045 GOTO_OPCODE(t0) # jump to next instruction 7046 /* 12-15 instructions */ 7047 7048 7049 7050 /* ------------------------------ */ 7051 .balign 128 7052 .L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 7053 /* File: mips/OP_XOR_LONG_2ADDR.S */ 7054 /* File: mips/binopWide2addr.S */ 7055 /* 7056 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 7057 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 7058 * This could be a MIPS instruction or a function call. (If the result 7059 * comes back in a register other than a0, you can override "result".) 7060 * 7061 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7062 * vCC (a1). Useful for integer division and modulus. 7063 * 7064 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 7065 * and-long/2addr, or-long/2addr, xor-long/2addr 7066 * rem-double/2addr 7067 */ 7068 /* binop/2addr vA, vB */ 7069 GET_OPA4(rOBJ) # rOBJ <- A+ 7070 GET_OPB(a1) # a1 <- B 7071 EAS2(a1, rFP, a1) # a1 <- &fp[B] 7072 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 7073 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 7074 LOAD64(a0, a1, rOBJ) # a0/a1 <- vAA/vAA+1 7075 .if 0 7076 or t0, a2, a3 # second arg (a2-a3) is zero? 7077 beqz t0, common_errDivideByZero 7078 .endif 7079 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7080 7081 xor a0, a0, a2 # optional op 7082 xor a1, a1, a3 # result <- op, a0-a3 changed 7083 GET_INST_OPCODE(t0) # extract opcode from rINST 7084 STORE64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1 7085 GOTO_OPCODE(t0) # jump to next instruction 7086 /* 12-15 instructions */ 7087 7088 7089 7090 /* ------------------------------ */ 7091 .balign 128 7092 .L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 7093 /* File: mips/OP_SHL_LONG_2ADDR.S */ 7094 /* 7095 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 7096 * 32-bit shift distance. 7097 */ 7098 /* shl-long/2addr vA, vB */ 7099 GET_OPA4(t2) # t2 <- A+ 7100 GET_OPB(a3) # a3 <- B 7101 GET_VREG(a2, a3) # a2 <- vB 7102 EAS2(rOBJ, rFP, t2) # rOBJ <- &fp[A] 7103 LOAD64(a0, a1, rOBJ) # a0/a1 <- vAA/vAA+1 7104 7105 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7106 7107 sll v0, a0, a2 # rlo<- alo << (shift&31) 7108 not v1, a2 # rhi<- 31-shift (shift is 5b) 7109 srl a0, 1 7110 srl a0, v1 # alo<- alo >> (32-(shift&31)) 7111 sll v1, a1, a2 # rhi<- ahi << (shift&31) 7112 or v1, a0 # rhi<- rhi | alo 7113 andi a2, 0x20 # shift< shift & 0x20 7114 movn v1, v0, a2 # rhi<- rlo (if shift&0x20) 7115 movn v0, zero, a2 # rlo<- 0 (if shift&0x20) 7116 7117 GET_INST_OPCODE(t0) # extract opcode from rINST 7118 STORE64(v0, v1, rOBJ) # vAA/vAA+1 <- a0/a1 7119 GOTO_OPCODE(t0) # jump to next instruction 7120 7121 7122 /* ------------------------------ */ 7123 .balign 128 7124 .L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 7125 /* File: mips/OP_SHR_LONG_2ADDR.S */ 7126 /* 7127 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 7128 * 32-bit shift distance. 7129 */ 7130 /* shr-long/2addr vA, vB */ 7131 GET_OPA4(t2) # t2 <- A+ 7132 GET_OPB(a3) # a3 <- B 7133 GET_VREG(a2, a3) # a2 <- vB 7134 EAS2(t2, rFP, t2) # t2 <- &fp[A] 7135 LOAD64(a0, a1, t2) # a0/a1 <- vAA/vAA+1 7136 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7137 7138 sra v1, a1, a2 # rhi<- ahi >> (shift&31) 7139 srl v0, a0, a2 # rlo<- alo >> (shift&31) 7140 sra a3, a1, 31 # a3<- sign(ah) 7141 not a0, a2 # alo<- 31-shift (shift is 5b) 7142 sll a1, 1 7143 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 7144 or v0, a1 # rlo<- rlo | ahi 7145 andi a2, 0x20 # shift & 0x20 7146 movn v0, v1, a2 # rlo<- rhi (if shift&0x20) 7147 movn v1, a3, a2 # rhi<- sign(ahi) (if shift&0x20) 7148 7149 GET_INST_OPCODE(t0) # extract opcode from rINST 7150 STORE64(v0, v1, t2) # vAA/vAA+1 <- a0/a1 7151 GOTO_OPCODE(t0) # jump to next instruction 7152 7153 7154 /* ------------------------------ */ 7155 .balign 128 7156 .L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 7157 /* File: mips/OP_USHR_LONG_2ADDR.S */ 7158 /* 7159 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 7160 * 32-bit shift distance. 7161 */ 7162 /* ushr-long/2addr vA, vB */ 7163 GET_OPA4(t3) # t3 <- A+ 7164 GET_OPB(a3) # a3 <- B 7165 GET_VREG(a2, a3) # a2 <- vB 7166 EAS2(t3, rFP, t3) # t3 <- &fp[A] 7167 LOAD64(a0, a1, t3) # a0/a1 <- vAA/vAA+1 7168 7169 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7170 srl v1, a1, a2 # rhi<- ahi >> (shift&31) 7171 srl v0, a0, a2 # rlo<- alo >> (shift&31) 7172 not a0, a2 # alo<- 31-n (shift is 5b) 7173 sll a1, 1 7174 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 7175 or v0, a1 # rlo<- rlo | ahi 7176 andi a2, 0x20 # shift & 0x20 7177 movn v0, v1, a2 # rlo<- rhi (if shift&0x20) 7178 movn v1, zero, a2 # rhi<- 0 (if shift&0x20) 7179 7180 GET_INST_OPCODE(t0) # extract opcode from rINST 7181 STORE64(v0, v1, t3) # vAA/vAA+1 <- a0/a1 7182 GOTO_OPCODE(t0) # jump to next instruction 7183 7184 7185 /* ------------------------------ */ 7186 .balign 128 7187 .L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 7188 /* File: mips/OP_ADD_FLOAT_2ADDR.S */ 7189 /* File: mips/binflop2addr.S */ 7190 /* 7191 * Generic 32-bit "/2addr" binary operation. Provide an "instr" and 7192 * "instr_f" line 7193 * that specifies an instruction that performs "result = a0 op a1". 7194 * This could be an MIPS instruction or a function call. 7195 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7196 * vCC (a1). Useful for integer division and modulus. 7197 * 7198 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 7199 * div-float/2addr, rem-float/2addr 7200 */ 7201 /* binop/2addr vA, vB */ 7202 GET_OPA4(rOBJ) # t1 <- A+ 7203 GET_OPB(a3) # a3 <- B 7204 #ifdef SOFT_FLOAT 7205 GET_VREG(a0, rOBJ) # a0 <- vA 7206 GET_VREG(a1, a3) # a1 <- vB 7207 .if 0 7208 # is second operand zero? 7209 beqz a1, common_errDivideByZero 7210 .endif 7211 #else 7212 GET_VREG_F(fa0, rOBJ) 7213 GET_VREG_F(fa1, a3) 7214 .if 0 7215 # is second operand zero? 7216 li.s ft0, 0 7217 c.eq.s fcc0, ft0, fa1 7218 bc1t fcc0, common_errDivideByZero 7219 .endif 7220 #endif 7221 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7222 # optional op 7223 #ifdef SOFT_FLOAT 7224 JAL(__addsf3) # result <- op, a0-a3 changed 7225 SET_VREG(v0, rOBJ) # vAA <- result 7226 #else 7227 add.s fv0, fa0, fa1 7228 SET_VREG_F(fv0, rOBJ) # vAA <- result 7229 #endif 7230 GET_INST_OPCODE(t0) # extract opcode from rINST 7231 GOTO_OPCODE(t0) # jump to next instruction 7232 /* 10-13 instructions */ 7233 7234 7235 7236 /* ------------------------------ */ 7237 .balign 128 7238 .L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 7239 /* File: mips/OP_SUB_FLOAT_2ADDR.S */ 7240 /* File: mips/binflop2addr.S */ 7241 /* 7242 * Generic 32-bit "/2addr" binary operation. Provide an "instr" and 7243 * "instr_f" line 7244 * that specifies an instruction that performs "result = a0 op a1". 7245 * This could be an MIPS instruction or a function call. 7246 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7247 * vCC (a1). Useful for integer division and modulus. 7248 * 7249 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 7250 * div-float/2addr, rem-float/2addr 7251 */ 7252 /* binop/2addr vA, vB */ 7253 GET_OPA4(rOBJ) # t1 <- A+ 7254 GET_OPB(a3) # a3 <- B 7255 #ifdef SOFT_FLOAT 7256 GET_VREG(a0, rOBJ) # a0 <- vA 7257 GET_VREG(a1, a3) # a1 <- vB 7258 .if 0 7259 # is second operand zero? 7260 beqz a1, common_errDivideByZero 7261 .endif 7262 #else 7263 GET_VREG_F(fa0, rOBJ) 7264 GET_VREG_F(fa1, a3) 7265 .if 0 7266 # is second operand zero? 7267 li.s ft0, 0 7268 c.eq.s fcc0, ft0, fa1 7269 bc1t fcc0, common_errDivideByZero 7270 .endif 7271 #endif 7272 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7273 # optional op 7274 #ifdef SOFT_FLOAT 7275 JAL(__subsf3) # result <- op, a0-a3 changed 7276 SET_VREG(v0, rOBJ) # vAA <- result 7277 #else 7278 sub.s fv0, fa0, fa1 7279 SET_VREG_F(fv0, rOBJ) # vAA <- result 7280 #endif 7281 GET_INST_OPCODE(t0) # extract opcode from rINST 7282 GOTO_OPCODE(t0) # jump to next instruction 7283 /* 10-13 instructions */ 7284 7285 7286 7287 /* ------------------------------ */ 7288 .balign 128 7289 .L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 7290 /* File: mips/OP_MUL_FLOAT_2ADDR.S */ 7291 /* File: mips/binflop2addr.S */ 7292 /* 7293 * Generic 32-bit "/2addr" binary operation. Provide an "instr" and 7294 * "instr_f" line 7295 * that specifies an instruction that performs "result = a0 op a1". 7296 * This could be an MIPS instruction or a function call. 7297 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7298 * vCC (a1). Useful for integer division and modulus. 7299 * 7300 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 7301 * div-float/2addr, rem-float/2addr 7302 */ 7303 /* binop/2addr vA, vB */ 7304 GET_OPA4(rOBJ) # t1 <- A+ 7305 GET_OPB(a3) # a3 <- B 7306 #ifdef SOFT_FLOAT 7307 GET_VREG(a0, rOBJ) # a0 <- vA 7308 GET_VREG(a1, a3) # a1 <- vB 7309 .if 0 7310 # is second operand zero? 7311 beqz a1, common_errDivideByZero 7312 .endif 7313 #else 7314 GET_VREG_F(fa0, rOBJ) 7315 GET_VREG_F(fa1, a3) 7316 .if 0 7317 # is second operand zero? 7318 li.s ft0, 0 7319 c.eq.s fcc0, ft0, fa1 7320 bc1t fcc0, common_errDivideByZero 7321 .endif 7322 #endif 7323 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7324 # optional op 7325 #ifdef SOFT_FLOAT 7326 JAL(__mulsf3) # result <- op, a0-a3 changed 7327 SET_VREG(v0, rOBJ) # vAA <- result 7328 #else 7329 mul.s fv0, fa0, fa1 7330 SET_VREG_F(fv0, rOBJ) # vAA <- result 7331 #endif 7332 GET_INST_OPCODE(t0) # extract opcode from rINST 7333 GOTO_OPCODE(t0) # jump to next instruction 7334 /* 10-13 instructions */ 7335 7336 7337 7338 /* ------------------------------ */ 7339 .balign 128 7340 .L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 7341 /* File: mips/OP_DIV_FLOAT_2ADDR.S */ 7342 /* File: mips/binflop2addr.S */ 7343 /* 7344 * Generic 32-bit "/2addr" binary operation. Provide an "instr" and 7345 * "instr_f" line 7346 * that specifies an instruction that performs "result = a0 op a1". 7347 * This could be an MIPS instruction or a function call. 7348 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7349 * vCC (a1). Useful for integer division and modulus. 7350 * 7351 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 7352 * div-float/2addr, rem-float/2addr 7353 */ 7354 /* binop/2addr vA, vB */ 7355 GET_OPA4(rOBJ) # t1 <- A+ 7356 GET_OPB(a3) # a3 <- B 7357 #ifdef SOFT_FLOAT 7358 GET_VREG(a0, rOBJ) # a0 <- vA 7359 GET_VREG(a1, a3) # a1 <- vB 7360 .if 0 7361 # is second operand zero? 7362 beqz a1, common_errDivideByZero 7363 .endif 7364 #else 7365 GET_VREG_F(fa0, rOBJ) 7366 GET_VREG_F(fa1, a3) 7367 .if 0 7368 # is second operand zero? 7369 li.s ft0, 0 7370 c.eq.s fcc0, ft0, fa1 7371 bc1t fcc0, common_errDivideByZero 7372 .endif 7373 #endif 7374 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7375 # optional op 7376 #ifdef SOFT_FLOAT 7377 JAL(__divsf3) # result <- op, a0-a3 changed 7378 SET_VREG(v0, rOBJ) # vAA <- result 7379 #else 7380 div.s fv0, fa0, fa1 7381 SET_VREG_F(fv0, rOBJ) # vAA <- result 7382 #endif 7383 GET_INST_OPCODE(t0) # extract opcode from rINST 7384 GOTO_OPCODE(t0) # jump to next instruction 7385 /* 10-13 instructions */ 7386 7387 7388 7389 /* ------------------------------ */ 7390 .balign 128 7391 .L_OP_REM_FLOAT_2ADDR: /* 0xca */ 7392 /* File: mips/OP_REM_FLOAT_2ADDR.S */ 7393 /* File: mips/binflop2addr.S */ 7394 /* 7395 * Generic 32-bit "/2addr" binary operation. Provide an "instr" and 7396 * "instr_f" line 7397 * that specifies an instruction that performs "result = a0 op a1". 7398 * This could be an MIPS instruction or a function call. 7399 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7400 * vCC (a1). Useful for integer division and modulus. 7401 * 7402 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 7403 * div-float/2addr, rem-float/2addr 7404 */ 7405 /* binop/2addr vA, vB */ 7406 GET_OPA4(rOBJ) # t1 <- A+ 7407 GET_OPB(a3) # a3 <- B 7408 #ifdef SOFT_FLOAT 7409 GET_VREG(a0, rOBJ) # a0 <- vA 7410 GET_VREG(a1, a3) # a1 <- vB 7411 .if 0 7412 # is second operand zero? 7413 beqz a1, common_errDivideByZero 7414 .endif 7415 #else 7416 GET_VREG_F(fa0, rOBJ) 7417 GET_VREG_F(fa1, a3) 7418 .if 0 7419 # is second operand zero? 7420 li.s ft0, 0 7421 c.eq.s fcc0, ft0, fa1 7422 bc1t fcc0, common_errDivideByZero 7423 .endif 7424 #endif 7425 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7426 # optional op 7427 #ifdef SOFT_FLOAT 7428 JAL(fmodf) # result <- op, a0-a3 changed 7429 SET_VREG(v0, rOBJ) # vAA <- result 7430 #else 7431 JAL(fmodf) 7432 SET_VREG_F(fv0, rOBJ) # vAA <- result 7433 #endif 7434 GET_INST_OPCODE(t0) # extract opcode from rINST 7435 GOTO_OPCODE(t0) # jump to next instruction 7436 /* 10-13 instructions */ 7437 7438 7439 7440 /* ------------------------------ */ 7441 .balign 128 7442 .L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 7443 /* File: mips/OP_ADD_DOUBLE_2ADDR.S */ 7444 /* File: mips/binflopWide2addr.S */ 7445 /* 7446 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 7447 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 7448 * This could be an MIPS instruction or a function call. 7449 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7450 * vCC (a1). Useful for integer division and modulus. 7451 * 7452 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 7453 * div-double/2addr, rem-double/2addr 7454 */ 7455 /* binop/2addr vA, vB */ 7456 GET_OPA4(rOBJ) # rOBJ <- A+ 7457 GET_OPB(a1) # a1 <- B 7458 EAS2(a1, rFP, a1) # a1 <- &fp[B] 7459 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 7460 #ifdef SOFT_FLOAT 7461 LOAD64(rARG2, rARG3, a1) # a2/a3 <- vBB/vBB+1 7462 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vAA/vAA+1 7463 .if 0 7464 or t0, rARG2, rARG3 # second arg (a2-a3) is zero? 7465 beqz t0, common_errDivideByZero 7466 .endif 7467 #else 7468 LOAD64_F(fa0, fa0f, rOBJ) 7469 LOAD64_F(fa1, fa1f, a1) 7470 .if 0 7471 li.d ft0, 0 7472 c.eq.d fcc0, fa1, ft0 7473 bc1t fcc0, common_errDivideByZero 7474 .endif 7475 #endif 7476 1: 7477 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7478 # optional op 7479 #ifdef SOFT_FLOAT 7480 JAL(__adddf3) # result <- op, a0-a3 changed 7481 STORE64(rRESULT0, rRESULT1, rOBJ) 7482 #else 7483 add.d fv0, fa0, fa1 7484 STORE64_F(fv0, fv0f, rOBJ) 7485 #endif 7486 GET_INST_OPCODE(t0) # extract opcode from rINST 7487 GOTO_OPCODE(t0) # jump to next instruction 7488 /* 12-15 instructions */ 7489 7490 7491 7492 /* ------------------------------ */ 7493 .balign 128 7494 .L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 7495 /* File: mips/OP_SUB_DOUBLE_2ADDR.S */ 7496 /* File: mips/binflopWide2addr.S */ 7497 /* 7498 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 7499 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 7500 * This could be an MIPS instruction or a function call. 7501 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7502 * vCC (a1). Useful for integer division and modulus. 7503 * 7504 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 7505 * div-double/2addr, rem-double/2addr 7506 */ 7507 /* binop/2addr vA, vB */ 7508 GET_OPA4(rOBJ) # rOBJ <- A+ 7509 GET_OPB(a1) # a1 <- B 7510 EAS2(a1, rFP, a1) # a1 <- &fp[B] 7511 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 7512 #ifdef SOFT_FLOAT 7513 LOAD64(rARG2, rARG3, a1) # a2/a3 <- vBB/vBB+1 7514 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vAA/vAA+1 7515 .if 0 7516 or t0, rARG2, rARG3 # second arg (a2-a3) is zero? 7517 beqz t0, common_errDivideByZero 7518 .endif 7519 #else 7520 LOAD64_F(fa0, fa0f, rOBJ) 7521 LOAD64_F(fa1, fa1f, a1) 7522 .if 0 7523 li.d ft0, 0 7524 c.eq.d fcc0, fa1, ft0 7525 bc1t fcc0, common_errDivideByZero 7526 .endif 7527 #endif 7528 1: 7529 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7530 # optional op 7531 #ifdef SOFT_FLOAT 7532 JAL(__subdf3) # result <- op, a0-a3 changed 7533 STORE64(rRESULT0, rRESULT1, rOBJ) 7534 #else 7535 sub.d fv0, fa0, fa1 7536 STORE64_F(fv0, fv0f, rOBJ) 7537 #endif 7538 GET_INST_OPCODE(t0) # extract opcode from rINST 7539 GOTO_OPCODE(t0) # jump to next instruction 7540 /* 12-15 instructions */ 7541 7542 7543 7544 /* ------------------------------ */ 7545 .balign 128 7546 .L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 7547 /* File: mips/OP_MUL_DOUBLE_2ADDR.S */ 7548 /* File: mips/binflopWide2addr.S */ 7549 /* 7550 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 7551 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 7552 * This could be an MIPS instruction or a function call. 7553 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7554 * vCC (a1). Useful for integer division and modulus. 7555 * 7556 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 7557 * div-double/2addr, rem-double/2addr 7558 */ 7559 /* binop/2addr vA, vB */ 7560 GET_OPA4(rOBJ) # rOBJ <- A+ 7561 GET_OPB(a1) # a1 <- B 7562 EAS2(a1, rFP, a1) # a1 <- &fp[B] 7563 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 7564 #ifdef SOFT_FLOAT 7565 LOAD64(rARG2, rARG3, a1) # a2/a3 <- vBB/vBB+1 7566 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vAA/vAA+1 7567 .if 0 7568 or t0, rARG2, rARG3 # second arg (a2-a3) is zero? 7569 beqz t0, common_errDivideByZero 7570 .endif 7571 #else 7572 LOAD64_F(fa0, fa0f, rOBJ) 7573 LOAD64_F(fa1, fa1f, a1) 7574 .if 0 7575 li.d ft0, 0 7576 c.eq.d fcc0, fa1, ft0 7577 bc1t fcc0, common_errDivideByZero 7578 .endif 7579 #endif 7580 1: 7581 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7582 # optional op 7583 #ifdef SOFT_FLOAT 7584 JAL(__muldf3) # result <- op, a0-a3 changed 7585 STORE64(rRESULT0, rRESULT1, rOBJ) 7586 #else 7587 mul.d fv0, fa0, fa1 7588 STORE64_F(fv0, fv0f, rOBJ) 7589 #endif 7590 GET_INST_OPCODE(t0) # extract opcode from rINST 7591 GOTO_OPCODE(t0) # jump to next instruction 7592 /* 12-15 instructions */ 7593 7594 7595 7596 /* ------------------------------ */ 7597 .balign 128 7598 .L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 7599 /* File: mips/OP_DIV_DOUBLE_2ADDR.S */ 7600 /* File: mips/binflopWide2addr.S */ 7601 /* 7602 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 7603 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 7604 * This could be an MIPS instruction or a function call. 7605 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7606 * vCC (a1). Useful for integer division and modulus. 7607 * 7608 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 7609 * div-double/2addr, rem-double/2addr 7610 */ 7611 /* binop/2addr vA, vB */ 7612 GET_OPA4(rOBJ) # rOBJ <- A+ 7613 GET_OPB(a1) # a1 <- B 7614 EAS2(a1, rFP, a1) # a1 <- &fp[B] 7615 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 7616 #ifdef SOFT_FLOAT 7617 LOAD64(rARG2, rARG3, a1) # a2/a3 <- vBB/vBB+1 7618 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vAA/vAA+1 7619 .if 0 7620 or t0, rARG2, rARG3 # second arg (a2-a3) is zero? 7621 beqz t0, common_errDivideByZero 7622 .endif 7623 #else 7624 LOAD64_F(fa0, fa0f, rOBJ) 7625 LOAD64_F(fa1, fa1f, a1) 7626 .if 0 7627 li.d ft0, 0 7628 c.eq.d fcc0, fa1, ft0 7629 bc1t fcc0, common_errDivideByZero 7630 .endif 7631 #endif 7632 1: 7633 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7634 # optional op 7635 #ifdef SOFT_FLOAT 7636 JAL(__divdf3) # result <- op, a0-a3 changed 7637 STORE64(rRESULT0, rRESULT1, rOBJ) 7638 #else 7639 div.d fv0, fa0, fa1 7640 STORE64_F(fv0, fv0f, rOBJ) 7641 #endif 7642 GET_INST_OPCODE(t0) # extract opcode from rINST 7643 GOTO_OPCODE(t0) # jump to next instruction 7644 /* 12-15 instructions */ 7645 7646 7647 7648 /* ------------------------------ */ 7649 .balign 128 7650 .L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 7651 /* File: mips/OP_REM_DOUBLE_2ADDR.S */ 7652 /* File: mips/binflopWide2addr.S */ 7653 /* 7654 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 7655 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 7656 * This could be an MIPS instruction or a function call. 7657 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7658 * vCC (a1). Useful for integer division and modulus. 7659 * 7660 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 7661 * div-double/2addr, rem-double/2addr 7662 */ 7663 /* binop/2addr vA, vB */ 7664 GET_OPA4(rOBJ) # rOBJ <- A+ 7665 GET_OPB(a1) # a1 <- B 7666 EAS2(a1, rFP, a1) # a1 <- &fp[B] 7667 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[A] 7668 #ifdef SOFT_FLOAT 7669 LOAD64(rARG2, rARG3, a1) # a2/a3 <- vBB/vBB+1 7670 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vAA/vAA+1 7671 .if 0 7672 or t0, rARG2, rARG3 # second arg (a2-a3) is zero? 7673 beqz t0, common_errDivideByZero 7674 .endif 7675 #else 7676 LOAD64_F(fa0, fa0f, rOBJ) 7677 LOAD64_F(fa1, fa1f, a1) 7678 .if 0 7679 li.d ft0, 0 7680 c.eq.d fcc0, fa1, ft0 7681 bc1t fcc0, common_errDivideByZero 7682 .endif 7683 #endif 7684 1: 7685 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 7686 # optional op 7687 #ifdef SOFT_FLOAT 7688 JAL(fmod) # result <- op, a0-a3 changed 7689 STORE64(rRESULT0, rRESULT1, rOBJ) 7690 #else 7691 JAL(fmod) 7692 STORE64_F(fv0, fv0f, rOBJ) 7693 #endif 7694 GET_INST_OPCODE(t0) # extract opcode from rINST 7695 GOTO_OPCODE(t0) # jump to next instruction 7696 /* 12-15 instructions */ 7697 7698 7699 7700 /* ------------------------------ */ 7701 .balign 128 7702 .L_OP_ADD_INT_LIT16: /* 0xd0 */ 7703 /* File: mips/OP_ADD_INT_LIT16.S */ 7704 /* File: mips/binopLit16.S */ 7705 /* 7706 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 7707 * that specifies an instruction that performs "result = a0 op a1". 7708 * This could be an MIPS instruction or a function call. (If the result 7709 * comes back in a register other than a0, you can override "result".) 7710 * 7711 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7712 * vCC (a1). Useful for integer division and modulus. 7713 * 7714 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 7715 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 7716 */ 7717 # binop/lit16 vA, vB, /* +CCCC */ 7718 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 7719 GET_OPB(a2) # a2 <- B 7720 GET_OPA(rOBJ) # rOBJ <- A+ 7721 GET_VREG(a0, a2) # a0 <- vB 7722 and rOBJ, rOBJ, 15 7723 .if 0 7724 # cmp a1, 0; is second operand zero? 7725 beqz a1, common_errDivideByZero 7726 .endif 7727 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7728 7729 addu a0, a0, a1 # a0 <- op, a0-a3 changed 7730 GET_INST_OPCODE(t0) # extract opcode from rINST 7731 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7732 /* 10-13 instructions */ 7733 7734 7735 7736 /* ------------------------------ */ 7737 .balign 128 7738 .L_OP_RSUB_INT: /* 0xd1 */ 7739 /* File: mips/OP_RSUB_INT.S */ 7740 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 7741 /* File: mips/binopLit16.S */ 7742 /* 7743 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 7744 * that specifies an instruction that performs "result = a0 op a1". 7745 * This could be an MIPS instruction or a function call. (If the result 7746 * comes back in a register other than a0, you can override "result".) 7747 * 7748 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7749 * vCC (a1). Useful for integer division and modulus. 7750 * 7751 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 7752 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 7753 */ 7754 # binop/lit16 vA, vB, /* +CCCC */ 7755 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 7756 GET_OPB(a2) # a2 <- B 7757 GET_OPA(rOBJ) # rOBJ <- A+ 7758 GET_VREG(a0, a2) # a0 <- vB 7759 and rOBJ, rOBJ, 15 7760 .if 0 7761 # cmp a1, 0; is second operand zero? 7762 beqz a1, common_errDivideByZero 7763 .endif 7764 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7765 7766 subu a0, a1, a0 # a0 <- op, a0-a3 changed 7767 GET_INST_OPCODE(t0) # extract opcode from rINST 7768 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7769 /* 10-13 instructions */ 7770 7771 7772 7773 /* ------------------------------ */ 7774 .balign 128 7775 .L_OP_MUL_INT_LIT16: /* 0xd2 */ 7776 /* File: mips/OP_MUL_INT_LIT16.S */ 7777 /* File: mips/binopLit16.S */ 7778 /* 7779 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 7780 * that specifies an instruction that performs "result = a0 op a1". 7781 * This could be an MIPS instruction or a function call. (If the result 7782 * comes back in a register other than a0, you can override "result".) 7783 * 7784 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7785 * vCC (a1). Useful for integer division and modulus. 7786 * 7787 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 7788 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 7789 */ 7790 # binop/lit16 vA, vB, /* +CCCC */ 7791 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 7792 GET_OPB(a2) # a2 <- B 7793 GET_OPA(rOBJ) # rOBJ <- A+ 7794 GET_VREG(a0, a2) # a0 <- vB 7795 and rOBJ, rOBJ, 15 7796 .if 0 7797 # cmp a1, 0; is second operand zero? 7798 beqz a1, common_errDivideByZero 7799 .endif 7800 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7801 7802 mul a0, a0, a1 # a0 <- op, a0-a3 changed 7803 GET_INST_OPCODE(t0) # extract opcode from rINST 7804 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7805 /* 10-13 instructions */ 7806 7807 7808 7809 /* ------------------------------ */ 7810 .balign 128 7811 .L_OP_DIV_INT_LIT16: /* 0xd3 */ 7812 /* File: mips/OP_DIV_INT_LIT16.S */ 7813 /* File: mips/binopLit16.S */ 7814 /* 7815 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 7816 * that specifies an instruction that performs "result = a0 op a1". 7817 * This could be an MIPS instruction or a function call. (If the result 7818 * comes back in a register other than a0, you can override "result".) 7819 * 7820 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7821 * vCC (a1). Useful for integer division and modulus. 7822 * 7823 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 7824 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 7825 */ 7826 # binop/lit16 vA, vB, /* +CCCC */ 7827 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 7828 GET_OPB(a2) # a2 <- B 7829 GET_OPA(rOBJ) # rOBJ <- A+ 7830 GET_VREG(a0, a2) # a0 <- vB 7831 and rOBJ, rOBJ, 15 7832 .if 1 7833 # cmp a1, 0; is second operand zero? 7834 beqz a1, common_errDivideByZero 7835 .endif 7836 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7837 7838 div zero, a0, a1; mflo a0 # a0 <- op, a0-a3 changed 7839 GET_INST_OPCODE(t0) # extract opcode from rINST 7840 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7841 /* 10-13 instructions */ 7842 7843 7844 7845 /* ------------------------------ */ 7846 .balign 128 7847 .L_OP_REM_INT_LIT16: /* 0xd4 */ 7848 /* File: mips/OP_REM_INT_LIT16.S */ 7849 /* File: mips/binopLit16.S */ 7850 /* 7851 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 7852 * that specifies an instruction that performs "result = a0 op a1". 7853 * This could be an MIPS instruction or a function call. (If the result 7854 * comes back in a register other than a0, you can override "result".) 7855 * 7856 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7857 * vCC (a1). Useful for integer division and modulus. 7858 * 7859 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 7860 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 7861 */ 7862 # binop/lit16 vA, vB, /* +CCCC */ 7863 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 7864 GET_OPB(a2) # a2 <- B 7865 GET_OPA(rOBJ) # rOBJ <- A+ 7866 GET_VREG(a0, a2) # a0 <- vB 7867 and rOBJ, rOBJ, 15 7868 .if 1 7869 # cmp a1, 0; is second operand zero? 7870 beqz a1, common_errDivideByZero 7871 .endif 7872 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7873 7874 div zero, a0, a1; mfhi a0 # a0 <- op, a0-a3 changed 7875 GET_INST_OPCODE(t0) # extract opcode from rINST 7876 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7877 /* 10-13 instructions */ 7878 7879 7880 7881 /* ------------------------------ */ 7882 .balign 128 7883 .L_OP_AND_INT_LIT16: /* 0xd5 */ 7884 /* File: mips/OP_AND_INT_LIT16.S */ 7885 /* File: mips/binopLit16.S */ 7886 /* 7887 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 7888 * that specifies an instruction that performs "result = a0 op a1". 7889 * This could be an MIPS instruction or a function call. (If the result 7890 * comes back in a register other than a0, you can override "result".) 7891 * 7892 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7893 * vCC (a1). Useful for integer division and modulus. 7894 * 7895 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 7896 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 7897 */ 7898 # binop/lit16 vA, vB, /* +CCCC */ 7899 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 7900 GET_OPB(a2) # a2 <- B 7901 GET_OPA(rOBJ) # rOBJ <- A+ 7902 GET_VREG(a0, a2) # a0 <- vB 7903 and rOBJ, rOBJ, 15 7904 .if 0 7905 # cmp a1, 0; is second operand zero? 7906 beqz a1, common_errDivideByZero 7907 .endif 7908 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7909 7910 and a0, a0, a1 # a0 <- op, a0-a3 changed 7911 GET_INST_OPCODE(t0) # extract opcode from rINST 7912 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7913 /* 10-13 instructions */ 7914 7915 7916 7917 /* ------------------------------ */ 7918 .balign 128 7919 .L_OP_OR_INT_LIT16: /* 0xd6 */ 7920 /* File: mips/OP_OR_INT_LIT16.S */ 7921 /* File: mips/binopLit16.S */ 7922 /* 7923 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 7924 * that specifies an instruction that performs "result = a0 op a1". 7925 * This could be an MIPS instruction or a function call. (If the result 7926 * comes back in a register other than a0, you can override "result".) 7927 * 7928 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7929 * vCC (a1). Useful for integer division and modulus. 7930 * 7931 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 7932 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 7933 */ 7934 # binop/lit16 vA, vB, /* +CCCC */ 7935 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 7936 GET_OPB(a2) # a2 <- B 7937 GET_OPA(rOBJ) # rOBJ <- A+ 7938 GET_VREG(a0, a2) # a0 <- vB 7939 and rOBJ, rOBJ, 15 7940 .if 0 7941 # cmp a1, 0; is second operand zero? 7942 beqz a1, common_errDivideByZero 7943 .endif 7944 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7945 7946 or a0, a0, a1 # a0 <- op, a0-a3 changed 7947 GET_INST_OPCODE(t0) # extract opcode from rINST 7948 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7949 /* 10-13 instructions */ 7950 7951 7952 7953 /* ------------------------------ */ 7954 .balign 128 7955 .L_OP_XOR_INT_LIT16: /* 0xd7 */ 7956 /* File: mips/OP_XOR_INT_LIT16.S */ 7957 /* File: mips/binopLit16.S */ 7958 /* 7959 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 7960 * that specifies an instruction that performs "result = a0 op a1". 7961 * This could be an MIPS instruction or a function call. (If the result 7962 * comes back in a register other than a0, you can override "result".) 7963 * 7964 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7965 * vCC (a1). Useful for integer division and modulus. 7966 * 7967 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 7968 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 7969 */ 7970 # binop/lit16 vA, vB, /* +CCCC */ 7971 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 7972 GET_OPB(a2) # a2 <- B 7973 GET_OPA(rOBJ) # rOBJ <- A+ 7974 GET_VREG(a0, a2) # a0 <- vB 7975 and rOBJ, rOBJ, 15 7976 .if 0 7977 # cmp a1, 0; is second operand zero? 7978 beqz a1, common_errDivideByZero 7979 .endif 7980 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7981 7982 xor a0, a0, a1 # a0 <- op, a0-a3 changed 7983 GET_INST_OPCODE(t0) # extract opcode from rINST 7984 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7985 /* 10-13 instructions */ 7986 7987 7988 7989 /* ------------------------------ */ 7990 .balign 128 7991 .L_OP_ADD_INT_LIT8: /* 0xd8 */ 7992 /* File: mips/OP_ADD_INT_LIT8.S */ 7993 /* File: mips/binopLit8.S */ 7994 /* 7995 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7996 * that specifies an instruction that performs "result = a0 op a1". 7997 * This could be an MIPS instruction or a function call. (If the result 7998 * comes back in a register other than a0, you can override "result".) 7999 * 8000 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8001 * vCC (a1). Useful for integer division and modulus. 8002 * 8003 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8004 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8005 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8006 */ 8007 # binop/lit8 vAA, vBB, /* +CC */ 8008 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8009 GET_OPA(rOBJ) # rOBJ <- AA 8010 and a2, a3, 255 # a2 <- BB 8011 GET_VREG(a0, a2) # a0 <- vBB 8012 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8013 .if 0 8014 # is second operand zero? 8015 beqz a1, common_errDivideByZero 8016 .endif 8017 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8018 8019 # optional op 8020 addu a0, a0, a1 # a0 <- op, a0-a3 changed 8021 GET_INST_OPCODE(t0) # extract opcode from rINST 8022 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8023 /* 10-12 instructions */ 8024 8025 8026 8027 /* ------------------------------ */ 8028 .balign 128 8029 .L_OP_RSUB_INT_LIT8: /* 0xd9 */ 8030 /* File: mips/OP_RSUB_INT_LIT8.S */ 8031 /* File: mips/binopLit8.S */ 8032 /* 8033 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 8034 * that specifies an instruction that performs "result = a0 op a1". 8035 * This could be an MIPS instruction or a function call. (If the result 8036 * comes back in a register other than a0, you can override "result".) 8037 * 8038 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8039 * vCC (a1). Useful for integer division and modulus. 8040 * 8041 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8042 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8043 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8044 */ 8045 # binop/lit8 vAA, vBB, /* +CC */ 8046 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8047 GET_OPA(rOBJ) # rOBJ <- AA 8048 and a2, a3, 255 # a2 <- BB 8049 GET_VREG(a0, a2) # a0 <- vBB 8050 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8051 .if 0 8052 # is second operand zero? 8053 beqz a1, common_errDivideByZero 8054 .endif 8055 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8056 8057 # optional op 8058 subu a0, a1, a0 # a0 <- op, a0-a3 changed 8059 GET_INST_OPCODE(t0) # extract opcode from rINST 8060 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8061 /* 10-12 instructions */ 8062 8063 8064 8065 /* ------------------------------ */ 8066 .balign 128 8067 .L_OP_MUL_INT_LIT8: /* 0xda */ 8068 /* File: mips/OP_MUL_INT_LIT8.S */ 8069 /* File: mips/binopLit8.S */ 8070 /* 8071 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 8072 * that specifies an instruction that performs "result = a0 op a1". 8073 * This could be an MIPS instruction or a function call. (If the result 8074 * comes back in a register other than a0, you can override "result".) 8075 * 8076 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8077 * vCC (a1). Useful for integer division and modulus. 8078 * 8079 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8080 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8081 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8082 */ 8083 # binop/lit8 vAA, vBB, /* +CC */ 8084 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8085 GET_OPA(rOBJ) # rOBJ <- AA 8086 and a2, a3, 255 # a2 <- BB 8087 GET_VREG(a0, a2) # a0 <- vBB 8088 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8089 .if 0 8090 # is second operand zero? 8091 beqz a1, common_errDivideByZero 8092 .endif 8093 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8094 8095 # optional op 8096 mul a0, a0, a1 # a0 <- op, a0-a3 changed 8097 GET_INST_OPCODE(t0) # extract opcode from rINST 8098 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8099 /* 10-12 instructions */ 8100 8101 8102 8103 /* ------------------------------ */ 8104 .balign 128 8105 .L_OP_DIV_INT_LIT8: /* 0xdb */ 8106 /* File: mips/OP_DIV_INT_LIT8.S */ 8107 /* File: mips/binopLit8.S */ 8108 /* 8109 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 8110 * that specifies an instruction that performs "result = a0 op a1". 8111 * This could be an MIPS instruction or a function call. (If the result 8112 * comes back in a register other than a0, you can override "result".) 8113 * 8114 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8115 * vCC (a1). Useful for integer division and modulus. 8116 * 8117 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8118 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8119 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8120 */ 8121 # binop/lit8 vAA, vBB, /* +CC */ 8122 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8123 GET_OPA(rOBJ) # rOBJ <- AA 8124 and a2, a3, 255 # a2 <- BB 8125 GET_VREG(a0, a2) # a0 <- vBB 8126 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8127 .if 1 8128 # is second operand zero? 8129 beqz a1, common_errDivideByZero 8130 .endif 8131 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8132 8133 # optional op 8134 div zero, a0, a1; mflo a0 # a0 <- op, a0-a3 changed 8135 GET_INST_OPCODE(t0) # extract opcode from rINST 8136 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8137 /* 10-12 instructions */ 8138 8139 8140 8141 /* ------------------------------ */ 8142 .balign 128 8143 .L_OP_REM_INT_LIT8: /* 0xdc */ 8144 /* File: mips/OP_REM_INT_LIT8.S */ 8145 /* File: mips/binopLit8.S */ 8146 /* 8147 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 8148 * that specifies an instruction that performs "result = a0 op a1". 8149 * This could be an MIPS instruction or a function call. (If the result 8150 * comes back in a register other than a0, you can override "result".) 8151 * 8152 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8153 * vCC (a1). Useful for integer division and modulus. 8154 * 8155 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8156 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8157 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8158 */ 8159 # binop/lit8 vAA, vBB, /* +CC */ 8160 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8161 GET_OPA(rOBJ) # rOBJ <- AA 8162 and a2, a3, 255 # a2 <- BB 8163 GET_VREG(a0, a2) # a0 <- vBB 8164 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8165 .if 1 8166 # is second operand zero? 8167 beqz a1, common_errDivideByZero 8168 .endif 8169 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8170 8171 # optional op 8172 div zero, a0, a1; mfhi a0 # a0 <- op, a0-a3 changed 8173 GET_INST_OPCODE(t0) # extract opcode from rINST 8174 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8175 /* 10-12 instructions */ 8176 8177 8178 8179 /* ------------------------------ */ 8180 .balign 128 8181 .L_OP_AND_INT_LIT8: /* 0xdd */ 8182 /* File: mips/OP_AND_INT_LIT8.S */ 8183 /* File: mips/binopLit8.S */ 8184 /* 8185 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 8186 * that specifies an instruction that performs "result = a0 op a1". 8187 * This could be an MIPS instruction or a function call. (If the result 8188 * comes back in a register other than a0, you can override "result".) 8189 * 8190 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8191 * vCC (a1). Useful for integer division and modulus. 8192 * 8193 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8194 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8195 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8196 */ 8197 # binop/lit8 vAA, vBB, /* +CC */ 8198 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8199 GET_OPA(rOBJ) # rOBJ <- AA 8200 and a2, a3, 255 # a2 <- BB 8201 GET_VREG(a0, a2) # a0 <- vBB 8202 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8203 .if 0 8204 # is second operand zero? 8205 beqz a1, common_errDivideByZero 8206 .endif 8207 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8208 8209 # optional op 8210 and a0, a0, a1 # a0 <- op, a0-a3 changed 8211 GET_INST_OPCODE(t0) # extract opcode from rINST 8212 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8213 /* 10-12 instructions */ 8214 8215 8216 8217 /* ------------------------------ */ 8218 .balign 128 8219 .L_OP_OR_INT_LIT8: /* 0xde */ 8220 /* File: mips/OP_OR_INT_LIT8.S */ 8221 /* File: mips/binopLit8.S */ 8222 /* 8223 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 8224 * that specifies an instruction that performs "result = a0 op a1". 8225 * This could be an MIPS instruction or a function call. (If the result 8226 * comes back in a register other than a0, you can override "result".) 8227 * 8228 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8229 * vCC (a1). Useful for integer division and modulus. 8230 * 8231 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8232 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8233 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8234 */ 8235 # binop/lit8 vAA, vBB, /* +CC */ 8236 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8237 GET_OPA(rOBJ) # rOBJ <- AA 8238 and a2, a3, 255 # a2 <- BB 8239 GET_VREG(a0, a2) # a0 <- vBB 8240 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8241 .if 0 8242 # is second operand zero? 8243 beqz a1, common_errDivideByZero 8244 .endif 8245 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8246 8247 # optional op 8248 or a0, a0, a1 # a0 <- op, a0-a3 changed 8249 GET_INST_OPCODE(t0) # extract opcode from rINST 8250 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8251 /* 10-12 instructions */ 8252 8253 8254 8255 /* ------------------------------ */ 8256 .balign 128 8257 .L_OP_XOR_INT_LIT8: /* 0xdf */ 8258 /* File: mips/OP_XOR_INT_LIT8.S */ 8259 /* File: mips/binopLit8.S */ 8260 /* 8261 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 8262 * that specifies an instruction that performs "result = a0 op a1". 8263 * This could be an MIPS instruction or a function call. (If the result 8264 * comes back in a register other than a0, you can override "result".) 8265 * 8266 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8267 * vCC (a1). Useful for integer division and modulus. 8268 * 8269 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8270 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8271 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8272 */ 8273 # binop/lit8 vAA, vBB, /* +CC */ 8274 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8275 GET_OPA(rOBJ) # rOBJ <- AA 8276 and a2, a3, 255 # a2 <- BB 8277 GET_VREG(a0, a2) # a0 <- vBB 8278 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8279 .if 0 8280 # is second operand zero? 8281 beqz a1, common_errDivideByZero 8282 .endif 8283 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8284 8285 # optional op 8286 xor a0, a0, a1 # a0 <- op, a0-a3 changed 8287 GET_INST_OPCODE(t0) # extract opcode from rINST 8288 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8289 /* 10-12 instructions */ 8290 8291 8292 8293 /* ------------------------------ */ 8294 .balign 128 8295 .L_OP_SHL_INT_LIT8: /* 0xe0 */ 8296 /* File: mips/OP_SHL_INT_LIT8.S */ 8297 /* File: mips/binopLit8.S */ 8298 /* 8299 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 8300 * that specifies an instruction that performs "result = a0 op a1". 8301 * This could be an MIPS instruction or a function call. (If the result 8302 * comes back in a register other than a0, you can override "result".) 8303 * 8304 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8305 * vCC (a1). Useful for integer division and modulus. 8306 * 8307 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8308 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8309 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8310 */ 8311 # binop/lit8 vAA, vBB, /* +CC */ 8312 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8313 GET_OPA(rOBJ) # rOBJ <- AA 8314 and a2, a3, 255 # a2 <- BB 8315 GET_VREG(a0, a2) # a0 <- vBB 8316 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8317 .if 0 8318 # is second operand zero? 8319 beqz a1, common_errDivideByZero 8320 .endif 8321 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8322 8323 and a1, a1, 31 # optional op 8324 sll a0, a0, a1 # a0 <- op, a0-a3 changed 8325 GET_INST_OPCODE(t0) # extract opcode from rINST 8326 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8327 /* 10-12 instructions */ 8328 8329 8330 8331 /* ------------------------------ */ 8332 .balign 128 8333 .L_OP_SHR_INT_LIT8: /* 0xe1 */ 8334 /* File: mips/OP_SHR_INT_LIT8.S */ 8335 /* File: mips/binopLit8.S */ 8336 /* 8337 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 8338 * that specifies an instruction that performs "result = a0 op a1". 8339 * This could be an MIPS instruction or a function call. (If the result 8340 * comes back in a register other than a0, you can override "result".) 8341 * 8342 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8343 * vCC (a1). Useful for integer division and modulus. 8344 * 8345 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8346 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8347 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8348 */ 8349 # binop/lit8 vAA, vBB, /* +CC */ 8350 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8351 GET_OPA(rOBJ) # rOBJ <- AA 8352 and a2, a3, 255 # a2 <- BB 8353 GET_VREG(a0, a2) # a0 <- vBB 8354 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8355 .if 0 8356 # is second operand zero? 8357 beqz a1, common_errDivideByZero 8358 .endif 8359 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8360 8361 and a1, a1, 31 # optional op 8362 sra a0, a0, a1 # a0 <- op, a0-a3 changed 8363 GET_INST_OPCODE(t0) # extract opcode from rINST 8364 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8365 /* 10-12 instructions */ 8366 8367 8368 8369 /* ------------------------------ */ 8370 .balign 128 8371 .L_OP_USHR_INT_LIT8: /* 0xe2 */ 8372 /* File: mips/OP_USHR_INT_LIT8.S */ 8373 /* File: mips/binopLit8.S */ 8374 /* 8375 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 8376 * that specifies an instruction that performs "result = a0 op a1". 8377 * This could be an MIPS instruction or a function call. (If the result 8378 * comes back in a register other than a0, you can override "result".) 8379 * 8380 * If "chkzero" is set to 1, we perform a divide-by-zero check on 8381 * vCC (a1). Useful for integer division and modulus. 8382 * 8383 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 8384 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 8385 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 8386 */ 8387 # binop/lit8 vAA, vBB, /* +CC */ 8388 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 8389 GET_OPA(rOBJ) # rOBJ <- AA 8390 and a2, a3, 255 # a2 <- BB 8391 GET_VREG(a0, a2) # a0 <- vBB 8392 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 8393 .if 0 8394 # is second operand zero? 8395 beqz a1, common_errDivideByZero 8396 .endif 8397 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8398 8399 and a1, a1, 31 # optional op 8400 srl a0, a0, a1 # a0 <- op, a0-a3 changed 8401 GET_INST_OPCODE(t0) # extract opcode from rINST 8402 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 8403 /* 10-12 instructions */ 8404 8405 8406 8407 /* ------------------------------ */ 8408 .balign 128 8409 .L_OP_IGET_VOLATILE: /* 0xe3 */ 8410 /* File: mips/OP_IGET_VOLATILE.S */ 8411 /* File: mips/OP_IGET.S */ 8412 /* 8413 * General 32-bit instance field get. 8414 * 8415 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 8416 */ 8417 # op vA, vB, field /* CCCC */ 8418 GET_OPB(a0) # a0 <- B 8419 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 8420 FETCH(a1, 1) # a1 <- field ref CCCC 8421 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 8422 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 8423 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 8424 # is resolved entry null? 8425 bnez a0, .LOP_IGET_VOLATILE_finish # no, already resolved 8426 LOAD_rSELF_method(a2) # a2 <- current method 8427 EXPORT_PC() # resolve() could throw 8428 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 8429 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 8430 # test results 8431 move a0, v0 8432 bnez v0, .LOP_IGET_VOLATILE_finish 8433 b common_exceptionThrown 8434 8435 8436 /* ------------------------------ */ 8437 .balign 128 8438 .L_OP_IPUT_VOLATILE: /* 0xe4 */ 8439 /* File: mips/OP_IPUT_VOLATILE.S */ 8440 /* File: mips/OP_IPUT.S */ 8441 /* 8442 * General 32-bit instance field put. 8443 * 8444 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 8445 */ 8446 # op vA, vB, field /* CCCC */ 8447 GET_OPB(a0) # a0 <- B 8448 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 8449 FETCH(a1, 1) # a1 <- field ref CCCC 8450 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 8451 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 8452 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 8453 # is resolved entry null? 8454 bnez a0, .LOP_IPUT_VOLATILE_finish # no, already resolved 8455 LOAD_rSELF_method(a2) # a2 <- current method 8456 EXPORT_PC() # resolve() could throw 8457 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 8458 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 8459 # success? 8460 move a0, v0 8461 bnez v0, .LOP_IPUT_VOLATILE_finish # yes, finish up 8462 b common_exceptionThrown 8463 8464 8465 /* ------------------------------ */ 8466 .balign 128 8467 .L_OP_SGET_VOLATILE: /* 0xe5 */ 8468 /* File: mips/OP_SGET_VOLATILE.S */ 8469 /* File: mips/OP_SGET.S */ 8470 /* 8471 * General 32-bit SGET handler. 8472 * 8473 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 8474 */ 8475 # op vAA, field /* BBBB */ 8476 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 8477 FETCH(a1, 1) # a1 <- field ref BBBB 8478 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 8479 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 8480 # is resolved entry !null? 8481 bnez a0, .LOP_SGET_VOLATILE_finish 8482 8483 /* 8484 * Continuation if the field has not yet been resolved. 8485 * a1: BBBB field ref 8486 * rBIX: dvmDex->pResFields 8487 */ 8488 LOAD_rSELF_method(a2) # a2 <- current method 8489 #if defined(WITH_JIT) 8490 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 8491 #endif 8492 EXPORT_PC() # resolve() could throw, so export now 8493 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 8494 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 8495 move a0, v0 8496 # success? 8497 beqz v0, common_exceptionThrown # no, handle exception 8498 #if defined(WITH_JIT) 8499 /* 8500 * If the JIT is actively building a trace we need to make sure 8501 * that the field is fully resolved before including this instruction. 8502 */ 8503 JAL(common_verifyField) 8504 #endif 8505 b .LOP_SGET_VOLATILE_finish # resume 8506 8507 8508 /* ------------------------------ */ 8509 .balign 128 8510 .L_OP_SPUT_VOLATILE: /* 0xe6 */ 8511 /* File: mips/OP_SPUT_VOLATILE.S */ 8512 /* File: mips/OP_SPUT.S */ 8513 /* 8514 * General 32-bit SPUT handler. 8515 * 8516 * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 8517 */ 8518 # op vAA, field /* BBBB */ 8519 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 8520 FETCH(a1, 1) # a1 <- field ref BBBB 8521 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 8522 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 8523 bnez a0, .LOP_SPUT_VOLATILE_finish # is resolved entry null? 8524 /* 8525 * Continuation if the field has not yet been resolved. 8526 * a1: BBBB field ref 8527 * rBIX: dvmDex->pResFields 8528 */ 8529 LOAD_rSELF_method(a2) # a2 <- current method 8530 #if defined(WITH_JIT) 8531 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 8532 #endif 8533 EXPORT_PC() # resolve() may throw, so export now 8534 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 8535 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 8536 move a0, v0 8537 beqz v0, common_exceptionThrown # success? no, handle exception 8538 #if defined(WITH_JIT) 8539 /* 8540 * If the JIT is actively building a trace we need to make sure 8541 * that the field is fully resolved before including this instruction. 8542 */ 8543 JAL(common_verifyField) 8544 #endif 8545 b .LOP_SPUT_VOLATILE_finish # resume 8546 8547 8548 /* ------------------------------ */ 8549 .balign 128 8550 .L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 8551 /* File: mips/OP_IGET_OBJECT_VOLATILE.S */ 8552 /* File: mips/OP_IGET.S */ 8553 /* 8554 * General 32-bit instance field get. 8555 * 8556 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 8557 */ 8558 # op vA, vB, field /* CCCC */ 8559 GET_OPB(a0) # a0 <- B 8560 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 8561 FETCH(a1, 1) # a1 <- field ref CCCC 8562 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 8563 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 8564 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 8565 # is resolved entry null? 8566 bnez a0, .LOP_IGET_OBJECT_VOLATILE_finish # no, already resolved 8567 LOAD_rSELF_method(a2) # a2 <- current method 8568 EXPORT_PC() # resolve() could throw 8569 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 8570 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 8571 # test results 8572 move a0, v0 8573 bnez v0, .LOP_IGET_OBJECT_VOLATILE_finish 8574 b common_exceptionThrown 8575 8576 8577 /* ------------------------------ */ 8578 .balign 128 8579 .L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 8580 /* File: mips/OP_IGET_WIDE_VOLATILE.S */ 8581 /* File: mips/OP_IGET_WIDE.S */ 8582 /* 8583 * Wide 32-bit instance field get. 8584 */ 8585 # iget-wide vA, vB, field /* CCCC */ 8586 GET_OPB(a0) # a0 <- B 8587 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 8588 FETCH(a1, 1) # a1 <- field ref CCCC 8589 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pResFields 8590 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 8591 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 8592 # is resolved entry null? 8593 bnez a0, .LOP_IGET_WIDE_VOLATILE_finish # no, already resolved 8594 LOAD_rSELF_method(a2) # a2 <- current method 8595 EXPORT_PC() # resolve() could throw 8596 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 8597 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 8598 # test return code 8599 move a0, v0 8600 bnez v0, .LOP_IGET_WIDE_VOLATILE_finish 8601 b common_exceptionThrown 8602 8603 8604 /* ------------------------------ */ 8605 .balign 128 8606 .L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 8607 /* File: mips/OP_IPUT_WIDE_VOLATILE.S */ 8608 /* File: mips/OP_IPUT_WIDE.S */ 8609 # iput-wide vA, vB, field /* CCCC */ 8610 GET_OPB(a0) # a0 <- B 8611 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 8612 FETCH(a1, 1) # a1 <- field ref CCCC 8613 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pResFields 8614 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 8615 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 8616 # is resolved entry null? 8617 bnez a0, .LOP_IPUT_WIDE_VOLATILE_finish # no, already resolved 8618 LOAD_rSELF_method(a2) # a2 <- current method 8619 EXPORT_PC() # resolve() could throw 8620 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 8621 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 8622 # success? 8623 move a0, v0 8624 bnez v0, .LOP_IPUT_WIDE_VOLATILE_finish # yes, finish up 8625 b common_exceptionThrown 8626 8627 8628 /* ------------------------------ */ 8629 .balign 128 8630 .L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 8631 /* File: mips/OP_SGET_WIDE_VOLATILE.S */ 8632 /* File: mips/OP_SGET_WIDE.S */ 8633 /* 8634 * 64-bit SGET handler. 8635 */ 8636 # sget-wide vAA, field /* BBBB */ 8637 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 8638 FETCH(a1, 1) # a1 <- field ref BBBB 8639 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 8640 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 8641 # is resolved entry null? 8642 bnez a0, .LOP_SGET_WIDE_VOLATILE_finish 8643 8644 /* 8645 * Continuation if the field has not yet been resolved. 8646 * a1: BBBB field ref 8647 * rBIX: dvmDex->pResFields 8648 * 8649 * Returns StaticField pointer in v0. 8650 */ 8651 LOAD_rSELF_method(a2) # a2 <- current method 8652 #if defined(WITH_JIT) 8653 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 8654 #endif 8655 EXPORT_PC() # resolve() could throw, so export now 8656 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 8657 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 8658 move a0, v0 8659 # success? 8660 beqz v0, common_exceptionThrown # no, handle exception 8661 #if defined(WITH_JIT) 8662 /* 8663 * If the JIT is actively building a trace we need to make sure 8664 * that the field is fully resolved before including this instruction. 8665 */ 8666 JAL(common_verifyField) 8667 #endif 8668 8669 b .LOP_SGET_WIDE_VOLATILE_finish # resume 8670 8671 8672 /* ------------------------------ */ 8673 .balign 128 8674 .L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 8675 /* File: mips/OP_SPUT_WIDE_VOLATILE.S */ 8676 /* File: mips/OP_SPUT_WIDE.S */ 8677 /* 8678 * 64-bit SPUT handler. 8679 */ 8680 # sput-wide vAA, field /* BBBB */ 8681 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 8682 FETCH(a1, 1) # a1 <- field ref BBBB 8683 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 8684 GET_OPA(t0) # t0 <- AA 8685 LOAD_eas2(a2, rBIX, a1) # a2 <- resolved StaticField ptr 8686 EAS2(rOBJ, rFP, t0) # rOBJ<- &fp[AA] 8687 # is resolved entry null? 8688 beqz a2, .LOP_SPUT_WIDE_VOLATILE_resolve # yes, do resolve 8689 .LOP_SPUT_WIDE_VOLATILE_finish: # field ptr in a2, AA in rOBJ 8690 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8691 LOAD64(a0, a1, rOBJ) # a0/a1 <- vAA/vAA+1 8692 GET_INST_OPCODE(rBIX) # extract opcode from rINST 8693 .if 1 8694 addu a2, offStaticField_value # a2<- pointer to data 8695 JAL(dvmQuasiAtomicSwap64Sync) # stores a0/a1 into addr a2 8696 .else 8697 STORE64_off(a0, a1, a2, offStaticField_value) # field <- vAA/vAA+1 8698 .endif 8699 GOTO_OPCODE(rBIX) # jump to next instruction 8700 8701 8702 /* ------------------------------ */ 8703 .balign 128 8704 .L_OP_BREAKPOINT: /* 0xec */ 8705 /* (stub) */ 8706 SAVE_PC_TO_SELF() # only need to export PC and FP 8707 SAVE_FP_TO_SELF() 8708 move a0, rSELF # self is first arg to function 8709 JAL(dvmMterp_OP_BREAKPOINT) # call 8710 LOAD_PC_FROM_SELF() # retrieve updated values 8711 LOAD_FP_FROM_SELF() 8712 FETCH_INST() # load next instruction from rPC 8713 GET_INST_OPCODE(t0) # ...trim down to just the opcode 8714 GOTO_OPCODE(t0) # ...and jump to the handler 8715 /* ------------------------------ */ 8716 .balign 128 8717 .L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 8718 /* File: mips/OP_THROW_VERIFICATION_ERROR.S */ 8719 /* 8720 * Handle a throw-verification-error instruction. This throws an 8721 * exception for an error discovered during verification. The 8722 * exception is indicated by AA, with some detail provided by BBBB. 8723 */ 8724 /* op AA, ref@BBBB */ 8725 8726 LOAD_rSELF_method(a0) # a0 <- self->method 8727 FETCH(a2, 1) # a2 <- BBBB 8728 EXPORT_PC() # export the PC 8729 GET_OPA(a1) # a1 <- AA 8730 JAL(dvmThrowVerificationError) # always throws 8731 b common_exceptionThrown # handle exception 8732 8733 8734 /* ------------------------------ */ 8735 .balign 128 8736 .L_OP_EXECUTE_INLINE: /* 0xee */ 8737 /* File: mips/OP_EXECUTE_INLINE.S */ 8738 /* 8739 * Execute a "native inline" instruction. 8740 * 8741 * We need to call an InlineOp4Func: 8742 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 8743 * 8744 * The first four args are in a0-a3, pointer to return value storage 8745 * is on the stack. The function's return value is a flag that tells 8746 * us if an exception was thrown. 8747 * 8748 * TUNING: could maintain two tables, pointer in Thread and 8749 * swap if profiler/debuggger active. 8750 */ 8751 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 8752 lhu a2, offThread_subMode(rSELF) 8753 FETCH(rBIX, 1) # rBIX <- BBBB 8754 EXPORT_PC() # can throw 8755 and a2, kSubModeDebugProfile # Any going on? 8756 bnez a2, .LOP_EXECUTE_INLINE_debugmode # yes - take slow path 8757 .LOP_EXECUTE_INLINE_resume: 8758 addu a1, rSELF, offThread_retval # a1 <- &self->retval 8759 GET_OPB(a0) # a0 <- B 8760 # Stack should have 16/20 available 8761 sw a1, STACK_OFFSET_ARG04(sp) # push &self->retval 8762 BAL(.LOP_EXECUTE_INLINE_continue) # make call; will return after 8763 lw gp, STACK_OFFSET_GP(sp) # restore gp 8764 # test boolean result of inline 8765 beqz v0, common_exceptionThrown # returned false, handle exception 8766 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 8767 GET_INST_OPCODE(t0) # extract opcode from rINST 8768 GOTO_OPCODE(t0) # jump to next instruction 8769 8770 /* ------------------------------ */ 8771 .balign 128 8772 .L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 8773 /* File: mips/OP_EXECUTE_INLINE_RANGE.S */ 8774 /* 8775 * Execute a "native inline" instruction, using "/range" semantics. 8776 * Same idea as execute-inline, but we get the args differently. 8777 * 8778 * We need to call an InlineOp4Func: 8779 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 8780 * 8781 * The first four args are in a0-a3, pointer to return value storage 8782 * is on the stack. The function's return value is a flag that tells 8783 * us if an exception was thrown. 8784 */ 8785 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 8786 lhu a2, offThread_subMode(rSELF) 8787 FETCH(rBIX, 1) # rBIX<- BBBB 8788 EXPORT_PC() # can throw 8789 and a2, kSubModeDebugProfile # Any going on? 8790 bnez a2, .LOP_EXECUTE_INLINE_RANGE_debugmode # yes - take slow path 8791 .LOP_EXECUTE_INLINE_RANGE_resume: 8792 addu a1, rSELF, offThread_retval # a1<- &self->retval 8793 GET_OPA(a0) 8794 sw a1, STACK_OFFSET_ARG04(sp) # push &self->retval 8795 BAL(.LOP_EXECUTE_INLINE_RANGE_continue) # make call; will return after 8796 lw gp, STACK_OFFSET_GP(sp) # restore gp 8797 beqz v0, common_exceptionThrown # returned false, handle exception 8798 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 8799 GET_INST_OPCODE(t0) # extract opcode from rINST 8800 GOTO_OPCODE(t0) # jump to next instruction 8801 8802 8803 /* ------------------------------ */ 8804 .balign 128 8805 .L_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */ 8806 /* File: mips/OP_INVOKE_OBJECT_INIT_RANGE.S */ 8807 /* 8808 * Invoke Object.<init> on an object. In practice we know that 8809 * Object's nullary constructor doesn't do anything, so we just 8810 * skip it unless a debugger is active. 8811 */ 8812 FETCH(a1, 2) # a1<- CCCC 8813 GET_VREG(a0, a1) # a0<- "this" ptr 8814 # check for NULL 8815 beqz a0, common_errNullObject # export PC and throw NPE 8816 LOAD_base_offObject_clazz(a1, a0) # a1<- obj->clazz 8817 LOAD_base_offClassObject_accessFlags(a2, a1) # a2<- clazz->accessFlags 8818 and a2, CLASS_ISFINALIZABLE # is this class finalizable? 8819 beqz a2, .LOP_INVOKE_OBJECT_INIT_RANGE_finish # no, go 8820 8821 .LOP_INVOKE_OBJECT_INIT_RANGE_setFinal: 8822 EXPORT_PC() # can throw 8823 JAL(dvmSetFinalizable) # call dvmSetFinalizable(obj) 8824 LOAD_offThread_exception(a0, rSELF) # a0<- self->exception 8825 # exception pending? 8826 bnez a0, common_exceptionThrown # yes, handle it 8827 8828 .LOP_INVOKE_OBJECT_INIT_RANGE_finish: 8829 lhu a1, offThread_subMode(rSELF) 8830 and a1, kSubModeDebuggerActive # debugger active? 8831 bnez a1, .LOP_INVOKE_OBJECT_INIT_RANGE_debugger # Yes - skip optimization 8832 FETCH_ADVANCE_INST(2+1) # advance to next instr, load rINST 8833 GET_INST_OPCODE(t0) # t0<- opcode from rINST 8834 GOTO_OPCODE(t0) # execute it 8835 8836 8837 /* ------------------------------ */ 8838 .balign 128 8839 .L_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 8840 /* File: mips/OP_RETURN_VOID_BARRIER.S */ 8841 SMP_DMB 8842 b common_returnFromMethod 8843 8844 /* ------------------------------ */ 8845 .balign 128 8846 .L_OP_IGET_QUICK: /* 0xf2 */ 8847 /* File: mips/OP_IGET_QUICK.S */ 8848 /* For: iget-quick, iget-object-quick */ 8849 # op vA, vB, offset /* CCCC */ 8850 GET_OPB(a2) # a2 <- B 8851 GET_VREG(a3, a2) # a3 <- object we're operating on 8852 FETCH(a1, 1) # a1 <- field byte offset 8853 GET_OPA4(a2) # a2 <- A(+) 8854 # check object for null 8855 beqz a3, common_errNullObject # object was null 8856 addu t0, a3, a1 # 8857 lw a0, 0(t0) # a0 <- obj.field (always 32 bits) 8858 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8859 GET_INST_OPCODE(t0) # extract opcode from rINST 8860 SET_VREG(a0, a2) # fp[A] <- a0 8861 GOTO_OPCODE(t0) # jump to next instruction 8862 8863 8864 /* ------------------------------ */ 8865 .balign 128 8866 .L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 8867 /* File: mips/OP_IGET_WIDE_QUICK.S */ 8868 # iget-wide-quick vA, vB, offset /* CCCC */ 8869 GET_OPB(a2) # a2 <- B 8870 GET_VREG(a3, a2) # a3 <- object we're operating on 8871 FETCH(a1, 1) # a1 <- field byte offset 8872 GET_OPA4(a2) # a2 <- A(+) 8873 # check object for null 8874 beqz a3, common_errNullObject # object was null 8875 addu t0, a3, a1 # t0 <- a3 + a1 8876 LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned) 8877 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8878 EAS2(a3, rFP, a2) 8879 GET_INST_OPCODE(t0) # extract opcode from rINST 8880 STORE64(a0, a1, a3) # fp[A] <- a0/a1 8881 GOTO_OPCODE(t0) # jump to next instruction 8882 8883 8884 /* ------------------------------ */ 8885 .balign 128 8886 .L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 8887 /* File: mips/OP_IGET_OBJECT_QUICK.S */ 8888 /* File: mips/OP_IGET_QUICK.S */ 8889 /* For: iget-quick, iget-object-quick */ 8890 # op vA, vB, offset /* CCCC */ 8891 GET_OPB(a2) # a2 <- B 8892 GET_VREG(a3, a2) # a3 <- object we're operating on 8893 FETCH(a1, 1) # a1 <- field byte offset 8894 GET_OPA4(a2) # a2 <- A(+) 8895 # check object for null 8896 beqz a3, common_errNullObject # object was null 8897 addu t0, a3, a1 # 8898 lw a0, 0(t0) # a0 <- obj.field (always 32 bits) 8899 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8900 GET_INST_OPCODE(t0) # extract opcode from rINST 8901 SET_VREG(a0, a2) # fp[A] <- a0 8902 GOTO_OPCODE(t0) # jump to next instruction 8903 8904 8905 8906 /* ------------------------------ */ 8907 .balign 128 8908 .L_OP_IPUT_QUICK: /* 0xf5 */ 8909 /* File: mips/OP_IPUT_QUICK.S */ 8910 /* For: iput-quick, iput-object-quick */ 8911 # op vA, vB, offset /* CCCC */ 8912 GET_OPB(a2) # a2 <- B 8913 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 8914 FETCH(a1, 1) # a1 <- field byte offset 8915 GET_OPA4(a2) # a2 <- A(+) 8916 beqz a3, common_errNullObject # object was null 8917 GET_VREG(a0, a2) # a0 <- fp[A] 8918 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8919 addu t0, a3, a1 8920 sw a0, 0(t0) # obj.field (always 32 bits) <- a0 8921 GET_INST_OPCODE(t0) # extract opcode from rINST 8922 GOTO_OPCODE(t0) # jump to next instruction 8923 8924 8925 /* ------------------------------ */ 8926 .balign 128 8927 .L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 8928 /* File: mips/OP_IPUT_WIDE_QUICK.S */ 8929 # iput-wide-quick vA, vB, offset /* CCCC */ 8930 GET_OPA4(a0) # a0 <- A(+) 8931 GET_OPB(a1) # a1 <- B 8932 GET_VREG(a2, a1) # a2 <- fp[B], the object pointer 8933 EAS2(a3, rFP, a0) # a3 <- &fp[A] 8934 LOAD64(a0, a1, a3) # a0/a1 <- fp[A] 8935 # check object for null 8936 beqz a2, common_errNullObject # object was null 8937 FETCH(a3, 1) # a3 <- field byte offset 8938 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8939 addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1 8940 STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1 8941 GET_INST_OPCODE(t0) # extract opcode from rINST 8942 GOTO_OPCODE(t0) # jump to next instruction 8943 8944 8945 /* ------------------------------ */ 8946 .balign 128 8947 .L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 8948 /* File: mips/OP_IPUT_OBJECT_QUICK.S */ 8949 /* For: iput-object-quick */ 8950 # op vA, vB, offset /* CCCC */ 8951 GET_OPB(a2) # a2 <- B 8952 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 8953 FETCH(a1, 1) # a1 <- field byte offset 8954 GET_OPA4(a2) # a2 <- A(+) 8955 beqz a3, common_errNullObject # object was null 8956 GET_VREG(a0, a2) # a0 <- fp[A] 8957 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8958 addu t0, a3, a1 8959 sw a0, 0(t0) # obj.field (always 32 bits) <- a0 8960 beqz a0, 1f 8961 lw a2, offThread_cardTable(rSELF) # a2 <- card table base 8962 srl t1, a3, GC_CARD_SHIFT 8963 addu t2, a2, t1 8964 sb a2, 0(t2) 8965 1: 8966 GET_INST_OPCODE(t0) # extract opcode from rINST 8967 GOTO_OPCODE(t0) # jump to next instruction 8968 8969 /* ------------------------------ */ 8970 .balign 128 8971 .L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 8972 /* File: mips/OP_INVOKE_VIRTUAL_QUICK.S */ 8973 /* 8974 * Handle an optimized virtual method call. 8975 * 8976 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 8977 */ 8978 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 8979 # op vAA, {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 8980 FETCH(a3, 2) # a3 <- FEDC or CCCC 8981 FETCH(a1, 1) # a1 <- BBBB 8982 .if (!0) 8983 and a3, a3, 15 # a3 <- C (or stays CCCC) 8984 .endif 8985 GET_VREG(rOBJ, a3) # rOBJ <- vC ("this" ptr) 8986 # is "this" null? 8987 beqz rOBJ, common_errNullObject # null "this", throw exception 8988 LOAD_base_offObject_clazz(a2, rOBJ) # a2 <- thisPtr->clazz 8989 LOAD_base_offClassObject_vtable(a2, a2) # a2 <- thisPtr->clazz->vtable 8990 EXPORT_PC() # invoke must export 8991 LOAD_eas2(a0, a2, a1) # a0 <- vtable[BBBB] 8992 b common_invokeMethodNoRange # (a0=method, r9="this") 8993 8994 /* ------------------------------ */ 8995 .balign 128 8996 .L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 8997 /* File: mips/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 8998 /* File: mips/OP_INVOKE_VIRTUAL_QUICK.S */ 8999 /* 9000 * Handle an optimized virtual method call. 9001 * 9002 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 9003 */ 9004 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 9005 # op vAA, {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 9006 FETCH(a3, 2) # a3 <- FEDC or CCCC 9007 FETCH(a1, 1) # a1 <- BBBB 9008 .if (!1) 9009 and a3, a3, 15 # a3 <- C (or stays CCCC) 9010 .endif 9011 GET_VREG(rOBJ, a3) # rOBJ <- vC ("this" ptr) 9012 # is "this" null? 9013 beqz rOBJ, common_errNullObject # null "this", throw exception 9014 LOAD_base_offObject_clazz(a2, rOBJ) # a2 <- thisPtr->clazz 9015 LOAD_base_offClassObject_vtable(a2, a2) # a2 <- thisPtr->clazz->vtable 9016 EXPORT_PC() # invoke must export 9017 LOAD_eas2(a0, a2, a1) # a0 <- vtable[BBBB] 9018 b common_invokeMethodRange # (a0=method, r9="this") 9019 9020 9021 /* ------------------------------ */ 9022 .balign 128 9023 .L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 9024 /* File: mips/OP_INVOKE_SUPER_QUICK.S */ 9025 /* 9026 * Handle an optimized "super" method call. 9027 * 9028 * for: [opt] invoke-super-quick, invoke-super-quick/range 9029 */ 9030 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 9031 # op vAA, {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 9032 FETCH(t0, 2) # t0 <- GFED or CCCC 9033 LOAD_rSELF_method(a2) # a2 <- current method 9034 .if (!0) 9035 and t0, t0, 15 # t0 <- D (or stays CCCC) 9036 .endif 9037 FETCH(a1, 1) # a1 <- BBBB 9038 LOAD_base_offMethod_clazz(a2, a2) # a2 <- method->clazz 9039 EXPORT_PC() # must export for invoke 9040 LOAD_base_offClassObject_super(a2, a2) # a2 <- method->clazz->super 9041 GET_VREG(rOBJ, t0) # rOBJ <- "this" 9042 LOAD_base_offClassObject_vtable(a2, a2) # a2 <- ...clazz->super->vtable 9043 # is "this" null ? 9044 LOAD_eas2(a0, a2, a1) # a0 <- super->vtable[BBBB] 9045 beqz rOBJ, common_errNullObject # "this" is null, throw exception 9046 b common_invokeMethodNoRange # (a0=method, rOBJ="this") 9047 9048 9049 /* ------------------------------ */ 9050 .balign 128 9051 .L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 9052 /* File: mips/OP_INVOKE_SUPER_QUICK_RANGE.S */ 9053 /* File: mips/OP_INVOKE_SUPER_QUICK.S */ 9054 /* 9055 * Handle an optimized "super" method call. 9056 * 9057 * for: [opt] invoke-super-quick, invoke-super-quick/range 9058 */ 9059 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 9060 # op vAA, {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 9061 FETCH(t0, 2) # t0 <- GFED or CCCC 9062 LOAD_rSELF_method(a2) # a2 <- current method 9063 .if (!1) 9064 and t0, t0, 15 # t0 <- D (or stays CCCC) 9065 .endif 9066 FETCH(a1, 1) # a1 <- BBBB 9067 LOAD_base_offMethod_clazz(a2, a2) # a2 <- method->clazz 9068 EXPORT_PC() # must export for invoke 9069 LOAD_base_offClassObject_super(a2, a2) # a2 <- method->clazz->super 9070 GET_VREG(rOBJ, t0) # rOBJ <- "this" 9071 LOAD_base_offClassObject_vtable(a2, a2) # a2 <- ...clazz->super->vtable 9072 # is "this" null ? 9073 LOAD_eas2(a0, a2, a1) # a0 <- super->vtable[BBBB] 9074 beqz rOBJ, common_errNullObject # "this" is null, throw exception 9075 b common_invokeMethodRange # (a0=method, rOBJ="this") 9076 9077 9078 9079 /* ------------------------------ */ 9080 .balign 128 9081 .L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 9082 /* File: mips/OP_IPUT_OBJECT_VOLATILE.S */ 9083 /* File: mips/OP_IPUT_OBJECT.S */ 9084 /* 9085 * 32-bit instance field put. 9086 * 9087 * for: iput-object, iput-object-volatile 9088 */ 9089 # op vA, vB, field /* CCCC */ 9090 GET_OPB(a0) # a0 <- B 9091 LOAD_rSELF_methodClassDex(a3) # a3 <- DvmDex 9092 FETCH(a1, 1) # a1 <- field ref CCCC 9093 LOAD_base_offDvmDex_pResFields(a2, a3) # a2 <- pDvmDex->pResFields 9094 GET_VREG(rOBJ, a0) # rOBJ <- fp[B], the object pointer 9095 LOAD_eas2(a0, a2, a1) # a0 <- resolved InstField ptr 9096 # is resolved entry null? 9097 bnez a0, .LOP_IPUT_OBJECT_VOLATILE_finish # no, already resolved 9098 LOAD_rSELF_method(a2) # a2 <- current method 9099 EXPORT_PC() # resolve() could throw 9100 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 9101 JAL(dvmResolveInstField) # v0 <- resolved InstField ptr 9102 # success? 9103 move a0, v0 9104 bnez v0, .LOP_IPUT_OBJECT_VOLATILE_finish # yes, finish up 9105 b common_exceptionThrown 9106 9107 9108 /* ------------------------------ */ 9109 .balign 128 9110 .L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 9111 /* File: mips/OP_SGET_OBJECT_VOLATILE.S */ 9112 /* File: mips/OP_SGET.S */ 9113 /* 9114 * General 32-bit SGET handler. 9115 * 9116 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 9117 */ 9118 # op vAA, field /* BBBB */ 9119 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 9120 FETCH(a1, 1) # a1 <- field ref BBBB 9121 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 9122 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 9123 # is resolved entry !null? 9124 bnez a0, .LOP_SGET_OBJECT_VOLATILE_finish 9125 9126 /* 9127 * Continuation if the field has not yet been resolved. 9128 * a1: BBBB field ref 9129 * rBIX: dvmDex->pResFields 9130 */ 9131 LOAD_rSELF_method(a2) # a2 <- current method 9132 #if defined(WITH_JIT) 9133 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 9134 #endif 9135 EXPORT_PC() # resolve() could throw, so export now 9136 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 9137 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 9138 move a0, v0 9139 # success? 9140 beqz v0, common_exceptionThrown # no, handle exception 9141 #if defined(WITH_JIT) 9142 /* 9143 * If the JIT is actively building a trace we need to make sure 9144 * that the field is fully resolved before including this instruction. 9145 */ 9146 JAL(common_verifyField) 9147 #endif 9148 b .LOP_SGET_OBJECT_VOLATILE_finish # resume 9149 9150 9151 /* ------------------------------ */ 9152 .balign 128 9153 .L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 9154 /* File: mips/OP_SPUT_OBJECT_VOLATILE.S */ 9155 /* File: mips/OP_SPUT_OBJECT.S */ 9156 /* 9157 * General 32-bit SPUT handler. 9158 * 9159 * for: sput-object, sput-object-volatile 9160 */ 9161 /* op vAA, field@BBBB */ 9162 LOAD_rSELF_methodClassDex(a2) # a2 <- DvmDex 9163 FETCH(a1, 1) # a1 <- field ref BBBB 9164 LOAD_base_offDvmDex_pResFields(rBIX, a2) # rBIX <- dvmDex->pResFields 9165 LOAD_eas2(a0, rBIX, a1) # a0 <- resolved StaticField ptr 9166 bnez a0, .LOP_SPUT_OBJECT_VOLATILE_finish # is resolved entry null? 9167 9168 /* Continuation if the field has not yet been resolved. 9169 * a1: BBBB field ref 9170 * rBIX: dvmDex->pResFields 9171 */ 9172 LOAD_rSELF_method(a2) # a2 <- current method 9173 #if defined(WITH_JIT) 9174 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 9175 #endif 9176 EXPORT_PC() # resolve() may throw, so export now 9177 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 9178 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 9179 move a0, v0 9180 beqz v0, common_exceptionThrown # success? no, handle exception 9181 #if defined(WITH_JIT) 9182 /* 9183 * If the JIT is actively building a trace we need to make sure 9184 * that the field is fully resolved before including this instruction. 9185 */ 9186 JAL(common_verifyField) 9187 #endif 9188 b .LOP_SPUT_OBJECT_VOLATILE_finish # resume 9189 9190 9191 9192 /* ------------------------------ */ 9193 .balign 128 9194 .L_OP_UNUSED_FF: /* 0xff */ 9195 /* File: mips/OP_UNUSED_FF.S */ 9196 /* File: mips/unused.S */ 9197 BAL(common_abort) 9198 9199 9200 9201 .balign 128 9202 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 9203 .global dvmAsmInstructionEnd 9204 dvmAsmInstructionEnd: 9205 9206 /* 9207 * =========================================================================== 9208 * Sister implementations 9209 * =========================================================================== 9210 */ 9211 .global dvmAsmSisterStart 9212 .type dvmAsmSisterStart, %function 9213 .text 9214 .balign 4 9215 dvmAsmSisterStart: 9216 9217 /* continuation for OP_CHECK_CAST */ 9218 9219 .LOP_CHECK_CAST_castfailure: 9220 # A cast has failed. We need to throw a ClassCastException with the 9221 # class of the object that failed to be cast. 9222 EXPORT_PC() # about to throw 9223 LOAD_base_offObject_clazz(a0, rOBJ) # a0 <- obj->clazz 9224 move a1,rBIX # r1<- desired class 9225 JAL(dvmThrowClassCastException) 9226 b common_exceptionThrown 9227 9228 /* 9229 * Resolution required. This is the least-likely path. 9230 * 9231 * a2 holds BBBB 9232 * rOBJ holds object 9233 */ 9234 .LOP_CHECK_CAST_resolve: 9235 EXPORT_PC() # resolve() could throw 9236 LOAD_rSELF_method(a3) # a3 <- self->method 9237 move a1, a2 # a1 <- BBBB 9238 li a2, 0 # a2 <- false 9239 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 9240 JAL(dvmResolveClass) # v0 <- resolved ClassObject ptr 9241 # got null? 9242 beqz v0, common_exceptionThrown # yes, handle exception 9243 move a1, v0 # a1 <- class resolved from BBB 9244 LOAD_base_offObject_clazz(a0, rOBJ) # a0 <- obj->clazz 9245 b .LOP_CHECK_CAST_resolved # pick up where we left off 9246 9247 /* continuation for OP_INSTANCE_OF */ 9248 9249 /* 9250 * Trivial test failed, need to perform full check. This is common. 9251 * a0 holds obj->clazz 9252 * a1 holds class resolved from BBBB 9253 * rOBJ holds A 9254 */ 9255 .LOP_INSTANCE_OF_fullcheck: 9256 JAL(dvmInstanceofNonTrivial) # v0 <- boolean result 9257 move a0, v0 # fall through to OP_INSTANCE_OF_store 9258 b .LOP_INSTANCE_OF_store 9259 9260 /* 9261 * Resolution required. This is the least-likely path. 9262 * 9263 * a3 holds BBBB 9264 * rOBJ holds A 9265 */ 9266 .LOP_INSTANCE_OF_resolve: 9267 EXPORT_PC() # resolve() could throw 9268 LOAD_rSELF_method(a0) # a0 <- self->method 9269 move a1, a3 # a1 <- BBBB 9270 li a2, 1 # a2 <- true 9271 LOAD_base_offMethod_clazz(a0, a0) # a0 <- method->clazz 9272 JAL(dvmResolveClass) # v0 <- resolved ClassObject ptr 9273 # got null? 9274 move a1, v0 # a1 <- class resolved from BBB 9275 beqz v0, common_exceptionThrown # yes, handle exception 9276 GET_OPB(a3) # a3 <- B 9277 GET_VREG(a0, a3) # a0 <- vB (object) 9278 LOAD_base_offObject_clazz(a0, a0) # a0 <- obj->clazz 9279 b .LOP_INSTANCE_OF_resolved # pick up where we left off 9280 9281 9282 /* continuation for OP_NEW_INSTANCE */ 9283 9284 .LOP_NEW_INSTANCE_continue: 9285 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9286 GET_INST_OPCODE(t0) # extract opcode from rINST 9287 SET_VREG(v0, a3) # vAA <- v0 9288 GOTO_OPCODE(t0) # jump to next instruction 9289 9290 #if defined(WITH_JIT) 9291 /* 9292 * Check to see if we need to stop the trace building early. 9293 * v0: new object 9294 * a3: vAA 9295 */ 9296 .LOP_NEW_INSTANCE_jitCheck: 9297 lw a1, 0(rBIX) # reload resolved class 9298 # okay? 9299 bnez a1, .LOP_NEW_INSTANCE_continue # yes, finish 9300 move rOBJ, v0 # preserve new object 9301 move rBIX, a3 # preserve vAA 9302 move a0, rSELF 9303 move a1, rPC 9304 JAL(dvmJitEndTraceSelect) # (self, pc) 9305 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9306 GET_INST_OPCODE(t0) # extract opcode from rINST 9307 SET_VREG(rOBJ, rBIX) # vAA <- new object 9308 GOTO_OPCODE(t0) # jump to next instruction 9309 #endif 9310 9311 /* 9312 * Class initialization required. 9313 * 9314 * a0 holds class object 9315 */ 9316 .LOP_NEW_INSTANCE_needinit: 9317 JAL(dvmInitClass) # initialize class 9318 move a0, rOBJ # restore a0 9319 # check boolean result 9320 bnez v0, .LOP_NEW_INSTANCE_initialized # success, continue 9321 b common_exceptionThrown # failed, deal with init exception 9322 9323 9324 /* 9325 * Resolution required. This is the least-likely path. 9326 * 9327 * a1 holds BBBB 9328 */ 9329 .LOP_NEW_INSTANCE_resolve: 9330 LOAD_rSELF_method(a3) # a3 <- self->method 9331 li a2, 0 # a2 <- false 9332 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 9333 JAL(dvmResolveClass) # v0 <- resolved ClassObject ptr 9334 move a0, v0 9335 # got null? 9336 bnez v0, .LOP_NEW_INSTANCE_resolved # no, continue 9337 b common_exceptionThrown # yes, handle exception 9338 9339 /* continuation for OP_NEW_ARRAY */ 9340 9341 /* 9342 * Resolve class. (This is an uncommon case.) 9343 * 9344 * a1 holds array length 9345 * a2 holds class ref CCCC 9346 */ 9347 .LOP_NEW_ARRAY_resolve: 9348 LOAD_rSELF_method(a3) # a3 <- self->method 9349 move rOBJ, a1 # rOBJ <- length (save) 9350 move a1, a2 # a1 <- CCCC 9351 li a2, 0 # a2 <- false 9352 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 9353 JAL(dvmResolveClass) # v0 <- call(clazz, ref) 9354 move a1, rOBJ # a1 <- length (restore) 9355 # got null? 9356 beqz v0, common_exceptionThrown # yes, handle exception 9357 move a0, v0 9358 b .LOP_NEW_ARRAY_finish # continue with OP_NEW_ARRAY_finish 9359 9360 9361 9362 /* continuation for OP_FILLED_NEW_ARRAY */ 9363 9364 /* 9365 * On entry: 9366 * a0 holds array class 9367 * rOBJ holds AA or BA 9368 */ 9369 .LOP_FILLED_NEW_ARRAY_continue: 9370 LOAD_base_offClassObject_descriptor(a3, a0) # a3 <- arrayClass->descriptor 9371 li a2, ALLOC_DONT_TRACK # a2 <- alloc flags 9372 lbu rINST, 1(a3) # rINST <- descriptor[1] 9373 .if 0 9374 move a1, rOBJ # a1 <- AA (length) 9375 .else 9376 srl a1, rOBJ, 4 # rOBJ <- B (length) 9377 .endif 9378 seq t0, rINST, 'I' # array of ints? 9379 seq t1, rINST, 'L' # array of objects? 9380 or t0, t1 9381 seq t1, rINST, '[' # array of arrays? 9382 or t0, t1 9383 move rBIX, a1 # save length in rBIX 9384 beqz t0, .LOP_FILLED_NEW_ARRAY_notimpl # no, not handled yet 9385 JAL(dvmAllocArrayByClass) # v0 <- call(arClass, length, flags) 9386 # null return? 9387 beqz v0, common_exceptionThrown # alloc failed, handle exception 9388 9389 FETCH(a1, 2) # a1 <- FEDC or CCCC 9390 sw v0, offThread_retval(rSELF) # retval.l <- new array 9391 sw rINST, (offThread_retval+4)(rSELF) # retval.h <- type 9392 addu a0, v0, offArrayObject_contents # a0 <- newArray->contents 9393 subu rBIX, rBIX, 1 # length--, check for neg 9394 FETCH_ADVANCE_INST(3) # advance to next instr, load rINST 9395 bltz rBIX, 2f # was zero, bail 9396 9397 # copy values from registers into the array 9398 # a0=array, a1=CCCC/FEDC, t0=length (from AA or B), rOBJ=AA/BA 9399 move t0, rBIX 9400 .if 0 9401 EAS2(a2, rFP, a1) # a2 <- &fp[CCCC] 9402 1: 9403 lw a3, 0(a2) # a3 <- *a2++ 9404 addu a2, 4 9405 subu t0, t0, 1 # count-- 9406 sw a3, (a0) # *contents++ = vX 9407 addu a0, 4 9408 bgez t0, 1b 9409 9410 # continue at 2 9411 .else 9412 slt t1, t0, 4 # length was initially 5? 9413 and a2, rOBJ, 15 # a2 <- A 9414 bnez t1, 1f # <= 4 args, branch 9415 GET_VREG(a3, a2) # a3 <- vA 9416 subu t0, t0, 1 # count-- 9417 sw a3, 16(a0) # contents[4] = vA 9418 1: 9419 and a2, a1, 15 # a2 <- F/E/D/C 9420 GET_VREG(a3, a2) # a3 <- vF/vE/vD/vC 9421 srl a1, a1, 4 # a1 <- next reg in low 4 9422 subu t0, t0, 1 # count-- 9423 sw a3, 0(a0) # *contents++ = vX 9424 addu a0, a0, 4 9425 bgez t0, 1b 9426 # continue at 2 9427 .endif 9428 9429 2: 9430 lw a0, offThread_retval(rSELF) # a0 <- object 9431 lw a1, (offThread_retval+4)(rSELF) # a1 <- type 9432 seq t1, a1, 'I' # Is int array? 9433 bnez t1, 3f 9434 lw a2, offThread_cardTable(rSELF) # a2 <- card table base 9435 srl t3, a0, GC_CARD_SHIFT 9436 addu t2, a2, t3 9437 sb a2, (t2) 9438 3: 9439 GET_INST_OPCODE(t0) # ip <- opcode from rINST 9440 GOTO_OPCODE(t0) # execute it 9441 9442 9443 /* 9444 * Throw an exception indicating that we have not implemented this 9445 * mode of filled-new-array. 9446 */ 9447 .LOP_FILLED_NEW_ARRAY_notimpl: 9448 la a0, .LstrFilledNewArrayNotImpl 9449 JAL(dvmThrowInternalError) 9450 b common_exceptionThrown 9451 9452 /* 9453 * Ideally we'd only define this once, but depending on layout we can 9454 * exceed the range of the load above. 9455 */ 9456 9457 /* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 9458 9459 /* 9460 * On entry: 9461 * a0 holds array class 9462 * rOBJ holds AA or BA 9463 */ 9464 .LOP_FILLED_NEW_ARRAY_RANGE_continue: 9465 LOAD_base_offClassObject_descriptor(a3, a0) # a3 <- arrayClass->descriptor 9466 li a2, ALLOC_DONT_TRACK # a2 <- alloc flags 9467 lbu rINST, 1(a3) # rINST <- descriptor[1] 9468 .if 1 9469 move a1, rOBJ # a1 <- AA (length) 9470 .else 9471 srl a1, rOBJ, 4 # rOBJ <- B (length) 9472 .endif 9473 seq t0, rINST, 'I' # array of ints? 9474 seq t1, rINST, 'L' # array of objects? 9475 or t0, t1 9476 seq t1, rINST, '[' # array of arrays? 9477 or t0, t1 9478 move rBIX, a1 # save length in rBIX 9479 beqz t0, .LOP_FILLED_NEW_ARRAY_RANGE_notimpl # no, not handled yet 9480 JAL(dvmAllocArrayByClass) # v0 <- call(arClass, length, flags) 9481 # null return? 9482 beqz v0, common_exceptionThrown # alloc failed, handle exception 9483 9484 FETCH(a1, 2) # a1 <- FEDC or CCCC 9485 sw v0, offThread_retval(rSELF) # retval.l <- new array 9486 sw rINST, (offThread_retval+4)(rSELF) # retval.h <- type 9487 addu a0, v0, offArrayObject_contents # a0 <- newArray->contents 9488 subu rBIX, rBIX, 1 # length--, check for neg 9489 FETCH_ADVANCE_INST(3) # advance to next instr, load rINST 9490 bltz rBIX, 2f # was zero, bail 9491 9492 # copy values from registers into the array 9493 # a0=array, a1=CCCC/FEDC, t0=length (from AA or B), rOBJ=AA/BA 9494 move t0, rBIX 9495 .if 1 9496 EAS2(a2, rFP, a1) # a2 <- &fp[CCCC] 9497 1: 9498 lw a3, 0(a2) # a3 <- *a2++ 9499 addu a2, 4 9500 subu t0, t0, 1 # count-- 9501 sw a3, (a0) # *contents++ = vX 9502 addu a0, 4 9503 bgez t0, 1b 9504 9505 # continue at 2 9506 .else 9507 slt t1, t0, 4 # length was initially 5? 9508 and a2, rOBJ, 15 # a2 <- A 9509 bnez t1, 1f # <= 4 args, branch 9510 GET_VREG(a3, a2) # a3 <- vA 9511 subu t0, t0, 1 # count-- 9512 sw a3, 16(a0) # contents[4] = vA 9513 1: 9514 and a2, a1, 15 # a2 <- F/E/D/C 9515 GET_VREG(a3, a2) # a3 <- vF/vE/vD/vC 9516 srl a1, a1, 4 # a1 <- next reg in low 4 9517 subu t0, t0, 1 # count-- 9518 sw a3, 0(a0) # *contents++ = vX 9519 addu a0, a0, 4 9520 bgez t0, 1b 9521 # continue at 2 9522 .endif 9523 9524 2: 9525 lw a0, offThread_retval(rSELF) # a0 <- object 9526 lw a1, (offThread_retval+4)(rSELF) # a1 <- type 9527 seq t1, a1, 'I' # Is int array? 9528 bnez t1, 3f 9529 lw a2, offThread_cardTable(rSELF) # a2 <- card table base 9530 srl t3, a0, GC_CARD_SHIFT 9531 addu t2, a2, t3 9532 sb a2, (t2) 9533 3: 9534 GET_INST_OPCODE(t0) # ip <- opcode from rINST 9535 GOTO_OPCODE(t0) # execute it 9536 9537 9538 /* 9539 * Throw an exception indicating that we have not implemented this 9540 * mode of filled-new-array. 9541 */ 9542 .LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 9543 la a0, .LstrFilledNewArrayNotImpl 9544 JAL(dvmThrowInternalError) 9545 b common_exceptionThrown 9546 9547 /* 9548 * Ideally we'd only define this once, but depending on layout we can 9549 * exceed the range of the load above. 9550 */ 9551 9552 /* continuation for OP_CMPL_FLOAT */ 9553 9554 OP_CMPL_FLOAT_nan: 9555 li rTEMP, -1 9556 b OP_CMPL_FLOAT_finish 9557 9558 #ifdef SOFT_FLOAT 9559 OP_CMPL_FLOAT_continue: 9560 JAL(__gtsf2) # v0 <- (vBB > vCC) 9561 li rTEMP, 1 # rTEMP = 1 if v0 != 0 9562 bgtz v0, OP_CMPL_FLOAT_finish 9563 b OP_CMPL_FLOAT_nan 9564 #endif 9565 9566 OP_CMPL_FLOAT_finish: 9567 GET_OPA(t0) 9568 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9569 SET_VREG(rTEMP, t0) # vAA <- rTEMP 9570 GET_INST_OPCODE(t0) # extract opcode from rINST 9571 GOTO_OPCODE(t0) 9572 9573 /* continuation for OP_CMPG_FLOAT */ 9574 9575 OP_CMPG_FLOAT_nan: 9576 li rTEMP, 1 9577 b OP_CMPG_FLOAT_finish 9578 9579 #ifdef SOFT_FLOAT 9580 OP_CMPG_FLOAT_continue: 9581 JAL(__gtsf2) # v0 <- (vBB > vCC) 9582 li rTEMP, 1 # rTEMP = 1 if v0 != 0 9583 bgtz v0, OP_CMPG_FLOAT_finish 9584 b OP_CMPG_FLOAT_nan 9585 #endif 9586 9587 OP_CMPG_FLOAT_finish: 9588 GET_OPA(t0) 9589 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9590 SET_VREG(rTEMP, t0) # vAA <- rTEMP 9591 GET_INST_OPCODE(t0) # extract opcode from rINST 9592 GOTO_OPCODE(t0) 9593 9594 /* continuation for OP_CMPL_DOUBLE */ 9595 9596 OP_CMPL_DOUBLE_nan: 9597 li rTEMP, -1 9598 b OP_CMPL_DOUBLE_finish 9599 9600 #ifdef SOFT_FLOAT 9601 OP_CMPL_DOUBLE_continue: 9602 LOAD64(rARG2, rARG3, rBIX) # a2/a3 <- vCC/vCC+1 9603 JAL(__gtdf2) # fallthru 9604 li rTEMP, 1 # rTEMP = 1 if v0 != 0 9605 blez v0, OP_CMPL_DOUBLE_nan # fall thru for finish 9606 #endif 9607 9608 OP_CMPL_DOUBLE_finish: 9609 GET_OPA(rOBJ) 9610 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9611 GET_INST_OPCODE(t0) # extract opcode from rINST 9612 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 9613 9614 /* continuation for OP_CMPG_DOUBLE */ 9615 9616 OP_CMPG_DOUBLE_nan: 9617 li rTEMP, 1 9618 b OP_CMPG_DOUBLE_finish 9619 9620 #ifdef SOFT_FLOAT 9621 OP_CMPG_DOUBLE_continue: 9622 LOAD64(rARG2, rARG3, rBIX) # a2/a3 <- vCC/vCC+1 9623 JAL(__gtdf2) # fallthru 9624 li rTEMP, 1 # rTEMP = 1 if v0 != 0 9625 blez v0, OP_CMPG_DOUBLE_nan # fall thru for finish 9626 #endif 9627 9628 OP_CMPG_DOUBLE_finish: 9629 GET_OPA(rOBJ) 9630 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9631 GET_INST_OPCODE(t0) # extract opcode from rINST 9632 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 9633 9634 /* continuation for OP_APUT_OBJECT */ 9635 .LOP_APUT_OBJECT_checks: 9636 LOAD_base_offObject_clazz(a0, rBIX) # a0 <- obj->clazz 9637 LOAD_base_offObject_clazz(a1, rINST) # a1 <- arrayObj->clazz 9638 JAL(dvmCanPutArrayElement) # test object type vs. array type 9639 beqz v0, .LOP_APUT_OBJECT_throw # okay ? 9640 lw a2, offThread_cardTable(rSELF) 9641 srl t1, rINST, GC_CARD_SHIFT 9642 addu t2, a2, t1 9643 sb a2, (t2) 9644 b .LOP_APUT_OBJECT_finish # yes, skip type checks 9645 .LOP_APUT_OBJECT_throw: 9646 LOAD_base_offObject_clazz(a0, rBIX) # a0 <- obj->clazz 9647 LOAD_base_offObject_clazz(a1, rINST) # a1 <- arrayObj->clazz 9648 EXPORT_PC() 9649 JAL(dvmThrowArrayStoreExceptionIncompatibleElement) 9650 b common_exceptionThrown 9651 9652 /* continuation for OP_IGET */ 9653 9654 /* 9655 * Currently: 9656 * v0 holds resolved field 9657 * rOBJ holds object (caller saved) 9658 */ 9659 .LOP_IGET_finish: 9660 #BAL(common_squeak0) 9661 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9662 # check object for null 9663 beqz rOBJ, common_errNullObject # object was null 9664 addu a3, a3, rOBJ # form address 9665 lw a0, (a3) # a0 <- obj.field (8/16/32 bits) 9666 # noop # acquiring load 9667 GET_OPA4(a2) # a2 <- A+ 9668 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9669 GET_INST_OPCODE(t0) # extract opcode from rINST 9670 SET_VREG(a0, a2) # fp[A] <- a0 9671 GOTO_OPCODE(t0) # jump to next instruction 9672 9673 9674 /* continuation for OP_IGET_WIDE */ 9675 9676 /* 9677 * Currently: 9678 * a0 holds resolved field 9679 * rOBJ holds object 9680 */ 9681 .LOP_IGET_WIDE_finish: 9682 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9683 beqz rOBJ, common_errNullObject # object was null 9684 GET_OPA4(a2) # a2 <- A+ 9685 addu rOBJ, rOBJ, a3 # form address 9686 .if 0 9687 vLOAD64(a0, a1, rOBJ) # a0/a1 <- obj.field (64-bit align ok) 9688 .else 9689 LOAD64(a0, a1, rOBJ) # a0/a1 <- obj.field (64-bit align ok) 9690 .endif 9691 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9692 EAS2(a3, rFP, a2) # a3 <- &fp[A] 9693 GET_INST_OPCODE(t0) # extract opcode from rINST 9694 STORE64(a0, a1, a3) # fp[A] <- a0/a1 9695 GOTO_OPCODE(t0) # jump to next instruction 9696 9697 9698 /* continuation for OP_IGET_OBJECT */ 9699 9700 /* 9701 * Currently: 9702 * v0 holds resolved field 9703 * rOBJ holds object (caller saved) 9704 */ 9705 .LOP_IGET_OBJECT_finish: 9706 #BAL(common_squeak0) 9707 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9708 # check object for null 9709 beqz rOBJ, common_errNullObject # object was null 9710 addu a3, a3, rOBJ # form address 9711 lw a0, (a3) # a0 <- obj.field (8/16/32 bits) 9712 # noop # acquiring load 9713 GET_OPA4(a2) # a2 <- A+ 9714 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9715 GET_INST_OPCODE(t0) # extract opcode from rINST 9716 SET_VREG(a0, a2) # fp[A] <- a0 9717 GOTO_OPCODE(t0) # jump to next instruction 9718 9719 9720 /* continuation for OP_IGET_BOOLEAN */ 9721 9722 /* 9723 * Currently: 9724 * v0 holds resolved field 9725 * rOBJ holds object (caller saved) 9726 */ 9727 .LOP_IGET_BOOLEAN_finish: 9728 #BAL(common_squeak0) 9729 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9730 # check object for null 9731 beqz rOBJ, common_errNullObject # object was null 9732 addu a3, a3, rOBJ # form address 9733 lw a0, (a3) # a0 <- obj.field (8/16/32 bits) 9734 # noop # acquiring load 9735 GET_OPA4(a2) # a2 <- A+ 9736 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9737 GET_INST_OPCODE(t0) # extract opcode from rINST 9738 SET_VREG(a0, a2) # fp[A] <- a0 9739 GOTO_OPCODE(t0) # jump to next instruction 9740 9741 9742 /* continuation for OP_IGET_BYTE */ 9743 9744 /* 9745 * Currently: 9746 * v0 holds resolved field 9747 * rOBJ holds object (caller saved) 9748 */ 9749 .LOP_IGET_BYTE_finish: 9750 #BAL(common_squeak0) 9751 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9752 # check object for null 9753 beqz rOBJ, common_errNullObject # object was null 9754 addu a3, a3, rOBJ # form address 9755 lw a0, (a3) # a0 <- obj.field (8/16/32 bits) 9756 # noop # acquiring load 9757 GET_OPA4(a2) # a2 <- A+ 9758 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9759 GET_INST_OPCODE(t0) # extract opcode from rINST 9760 SET_VREG(a0, a2) # fp[A] <- a0 9761 GOTO_OPCODE(t0) # jump to next instruction 9762 9763 9764 /* continuation for OP_IGET_CHAR */ 9765 9766 /* 9767 * Currently: 9768 * v0 holds resolved field 9769 * rOBJ holds object (caller saved) 9770 */ 9771 .LOP_IGET_CHAR_finish: 9772 #BAL(common_squeak0) 9773 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9774 # check object for null 9775 beqz rOBJ, common_errNullObject # object was null 9776 addu a3, a3, rOBJ # form address 9777 lw a0, (a3) # a0 <- obj.field (8/16/32 bits) 9778 # noop # acquiring load 9779 GET_OPA4(a2) # a2 <- A+ 9780 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9781 GET_INST_OPCODE(t0) # extract opcode from rINST 9782 SET_VREG(a0, a2) # fp[A] <- a0 9783 GOTO_OPCODE(t0) # jump to next instruction 9784 9785 9786 /* continuation for OP_IGET_SHORT */ 9787 9788 /* 9789 * Currently: 9790 * v0 holds resolved field 9791 * rOBJ holds object (caller saved) 9792 */ 9793 .LOP_IGET_SHORT_finish: 9794 #BAL(common_squeak0) 9795 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9796 # check object for null 9797 beqz rOBJ, common_errNullObject # object was null 9798 addu a3, a3, rOBJ # form address 9799 lw a0, (a3) # a0 <- obj.field (8/16/32 bits) 9800 # noop # acquiring load 9801 GET_OPA4(a2) # a2 <- A+ 9802 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9803 GET_INST_OPCODE(t0) # extract opcode from rINST 9804 SET_VREG(a0, a2) # fp[A] <- a0 9805 GOTO_OPCODE(t0) # jump to next instruction 9806 9807 9808 /* continuation for OP_IPUT */ 9809 9810 /* 9811 * Currently: 9812 * a0 holds resolved field 9813 * rOBJ holds object 9814 */ 9815 .LOP_IPUT_finish: 9816 #BAL(common_squeak0) 9817 GET_OPA4(a1) # a1 <- A+ 9818 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9819 GET_VREG(a0, a1) # a0 <- fp[A] 9820 # check object for null 9821 beqz rOBJ, common_errNullObject # object was null 9822 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9823 GET_INST_OPCODE(t0) # extract opcode from rINST 9824 addu rOBJ, rOBJ, a3 # form address 9825 # noop # releasing store 9826 sw a0, (rOBJ) # obj.field (8/16/32 bits) <- a0 9827 # noop 9828 GOTO_OPCODE(t0) # jump to next instruction 9829 9830 9831 /* continuation for OP_IPUT_WIDE */ 9832 9833 /* 9834 * Currently: 9835 * a0 holds resolved field 9836 * rOBJ holds object 9837 */ 9838 .LOP_IPUT_WIDE_finish: 9839 GET_OPA4(a2) # a2 <- A+ 9840 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9841 EAS2(a2, rFP, a2) # a2 <- &fp[A] 9842 # check object for null 9843 beqz rOBJ, common_errNullObject # object was null 9844 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9845 LOAD64(a0, a1, a2) # a0/a1 <- fp[A] 9846 GET_INST_OPCODE(rBIX) # extract opcode from rINST 9847 addu a2, rOBJ, a3 # form address 9848 .if 0 9849 JAL(dvmQuasiAtomicSwap64Sync) # stores r0/r1 into addr r2 9850 # STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0 a1 9851 .else 9852 STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0 a1 9853 .endif 9854 GOTO_OPCODE(rBIX) # jump to next instruction 9855 9856 9857 /* continuation for OP_IPUT_OBJECT */ 9858 9859 /* 9860 * Currently: 9861 * a0 holds resolved field 9862 * rOBJ holds object 9863 */ 9864 .LOP_IPUT_OBJECT_finish: 9865 #BAL(common_squeak0) 9866 GET_OPA4(a1) # a1 <- A+ 9867 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9868 GET_VREG(a0, a1) # a0 <- fp[A] 9869 lw a2, offThread_cardTable(rSELF) # a2 <- card table base 9870 # check object for null 9871 beqz rOBJ, common_errNullObject # object was null 9872 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9873 GET_INST_OPCODE(t0) # extract opcode from rINST 9874 addu t2, rOBJ, a3 # form address 9875 # noop # releasing store 9876 sw a0, (t2) # obj.field (32 bits) <- a0 9877 # noop 9878 beqz a0, 1f # stored a null reference? 9879 srl t1, rOBJ, GC_CARD_SHIFT 9880 addu t2, a2, t1 9881 sb a2, (t2) # mark card if not 9882 1: 9883 GOTO_OPCODE(t0) # jump to next instruction 9884 9885 9886 /* continuation for OP_IPUT_BOOLEAN */ 9887 9888 /* 9889 * Currently: 9890 * a0 holds resolved field 9891 * rOBJ holds object 9892 */ 9893 .LOP_IPUT_BOOLEAN_finish: 9894 #BAL(common_squeak0) 9895 GET_OPA4(a1) # a1 <- A+ 9896 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9897 GET_VREG(a0, a1) # a0 <- fp[A] 9898 # check object for null 9899 beqz rOBJ, common_errNullObject # object was null 9900 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9901 GET_INST_OPCODE(t0) # extract opcode from rINST 9902 addu rOBJ, rOBJ, a3 # form address 9903 # noop # releasing store 9904 sw a0, (rOBJ) # obj.field (8/16/32 bits) <- a0 9905 # noop 9906 GOTO_OPCODE(t0) # jump to next instruction 9907 9908 9909 /* continuation for OP_IPUT_BYTE */ 9910 9911 /* 9912 * Currently: 9913 * a0 holds resolved field 9914 * rOBJ holds object 9915 */ 9916 .LOP_IPUT_BYTE_finish: 9917 #BAL(common_squeak0) 9918 GET_OPA4(a1) # a1 <- A+ 9919 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9920 GET_VREG(a0, a1) # a0 <- fp[A] 9921 # check object for null 9922 beqz rOBJ, common_errNullObject # object was null 9923 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9924 GET_INST_OPCODE(t0) # extract opcode from rINST 9925 addu rOBJ, rOBJ, a3 # form address 9926 # noop # releasing store 9927 sw a0, (rOBJ) # obj.field (8/16/32 bits) <- a0 9928 # noop 9929 GOTO_OPCODE(t0) # jump to next instruction 9930 9931 9932 /* continuation for OP_IPUT_CHAR */ 9933 9934 /* 9935 * Currently: 9936 * a0 holds resolved field 9937 * rOBJ holds object 9938 */ 9939 .LOP_IPUT_CHAR_finish: 9940 #BAL(common_squeak0) 9941 GET_OPA4(a1) # a1 <- A+ 9942 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9943 GET_VREG(a0, a1) # a0 <- fp[A] 9944 # check object for null 9945 beqz rOBJ, common_errNullObject # object was null 9946 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9947 GET_INST_OPCODE(t0) # extract opcode from rINST 9948 addu rOBJ, rOBJ, a3 # form address 9949 # noop # releasing store 9950 sw a0, (rOBJ) # obj.field (8/16/32 bits) <- a0 9951 # noop 9952 GOTO_OPCODE(t0) # jump to next instruction 9953 9954 9955 /* continuation for OP_IPUT_SHORT */ 9956 9957 /* 9958 * Currently: 9959 * a0 holds resolved field 9960 * rOBJ holds object 9961 */ 9962 .LOP_IPUT_SHORT_finish: 9963 #BAL(common_squeak0) 9964 GET_OPA4(a1) # a1 <- A+ 9965 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 9966 GET_VREG(a0, a1) # a0 <- fp[A] 9967 # check object for null 9968 beqz rOBJ, common_errNullObject # object was null 9969 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9970 GET_INST_OPCODE(t0) # extract opcode from rINST 9971 addu rOBJ, rOBJ, a3 # form address 9972 # noop # releasing store 9973 sw a0, (rOBJ) # obj.field (8/16/32 bits) <- a0 9974 # noop 9975 GOTO_OPCODE(t0) # jump to next instruction 9976 9977 9978 /* continuation for OP_SGET */ 9979 9980 .LOP_SGET_finish: 9981 LOAD_base_offStaticField_value(a1, a0) # a1 <- field value 9982 # no-op # acquiring load 9983 GET_OPA(a2) # a2 <- AA 9984 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9985 GET_INST_OPCODE(t0) # extract opcode from rINST 9986 SET_VREG_GOTO(a1, a2, t0) # fp[AA] <- a1 9987 9988 /* continuation for OP_SGET_WIDE */ 9989 9990 .LOP_SGET_WIDE_finish: 9991 GET_OPA(a1) # a1 <- AA 9992 .if 0 9993 vLOAD64_off(a2, a3, a0, offStaticField_value) # a2/a3 <- field value (aligned) 9994 .else 9995 LOAD64_off(a2, a3, a0, offStaticField_value) # a2/a3 <- field value (aligned) 9996 .endif 9997 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 9998 EAS2(a1, rFP, a1) # a1 <- &fp[AA] 9999 STORE64(a2, a3, a1) # vAA/vAA+1 <- a2/a3 10000 GET_INST_OPCODE(t0) # extract opcode from rINST 10001 GOTO_OPCODE(t0) # jump to next instruction 10002 10003 10004 10005 /* continuation for OP_SGET_OBJECT */ 10006 10007 .LOP_SGET_OBJECT_finish: 10008 LOAD_base_offStaticField_value(a1, a0) # a1 <- field value 10009 # no-op # acquiring load 10010 GET_OPA(a2) # a2 <- AA 10011 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10012 GET_INST_OPCODE(t0) # extract opcode from rINST 10013 SET_VREG_GOTO(a1, a2, t0) # fp[AA] <- a1 10014 10015 /* continuation for OP_SGET_BOOLEAN */ 10016 10017 .LOP_SGET_BOOLEAN_finish: 10018 LOAD_base_offStaticField_value(a1, a0) # a1 <- field value 10019 # no-op # acquiring load 10020 GET_OPA(a2) # a2 <- AA 10021 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10022 GET_INST_OPCODE(t0) # extract opcode from rINST 10023 SET_VREG_GOTO(a1, a2, t0) # fp[AA] <- a1 10024 10025 /* continuation for OP_SGET_BYTE */ 10026 10027 .LOP_SGET_BYTE_finish: 10028 LOAD_base_offStaticField_value(a1, a0) # a1 <- field value 10029 # no-op # acquiring load 10030 GET_OPA(a2) # a2 <- AA 10031 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10032 GET_INST_OPCODE(t0) # extract opcode from rINST 10033 SET_VREG_GOTO(a1, a2, t0) # fp[AA] <- a1 10034 10035 /* continuation for OP_SGET_CHAR */ 10036 10037 .LOP_SGET_CHAR_finish: 10038 LOAD_base_offStaticField_value(a1, a0) # a1 <- field value 10039 # no-op # acquiring load 10040 GET_OPA(a2) # a2 <- AA 10041 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10042 GET_INST_OPCODE(t0) # extract opcode from rINST 10043 SET_VREG_GOTO(a1, a2, t0) # fp[AA] <- a1 10044 10045 /* continuation for OP_SGET_SHORT */ 10046 10047 .LOP_SGET_SHORT_finish: 10048 LOAD_base_offStaticField_value(a1, a0) # a1 <- field value 10049 # no-op # acquiring load 10050 GET_OPA(a2) # a2 <- AA 10051 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10052 GET_INST_OPCODE(t0) # extract opcode from rINST 10053 SET_VREG_GOTO(a1, a2, t0) # fp[AA] <- a1 10054 10055 /* continuation for OP_SPUT */ 10056 10057 .LOP_SPUT_finish: 10058 # field ptr in a0 10059 GET_OPA(a2) # a2 <- AA 10060 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10061 GET_VREG(a1, a2) # a1 <- fp[AA] 10062 GET_INST_OPCODE(t0) # extract opcode from rINST 10063 # no-op # releasing store 10064 sw a1, offStaticField_value(a0) # field <- vAA 10065 # no-op 10066 GOTO_OPCODE(t0) # jump to next instruction 10067 10068 /* continuation for OP_SPUT_WIDE */ 10069 10070 /* 10071 * Continuation if the field has not yet been resolved. 10072 * a1: BBBB field ref 10073 * rOBJ: &fp[AA] 10074 * rBIX: dvmDex->pResFields 10075 * 10076 * Returns StaticField pointer in a2. 10077 */ 10078 .LOP_SPUT_WIDE_resolve: 10079 LOAD_rSELF_method(a2) # a2 <- current method 10080 #if defined(WITH_JIT) 10081 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 10082 #endif 10083 EXPORT_PC() # resolve() could throw, so export now 10084 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 10085 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 10086 # success ? 10087 move a0, v0 10088 beqz v0, common_exceptionThrown # no, handle exception 10089 #if defined(WITH_JIT) 10090 /* 10091 * If the JIT is actively building a trace we need to make sure 10092 * that the field is fully resolved before including this instruction. 10093 */ 10094 JAL(common_verifyField) 10095 #endif 10096 move a2, v0 10097 b .LOP_SPUT_WIDE_finish # resume 10098 10099 /* continuation for OP_SPUT_OBJECT */ 10100 .LOP_SPUT_OBJECT_finish: # field ptr in a0 10101 GET_OPA(a2) # a2 <- AA 10102 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10103 GET_VREG(a1, a2) # a1 <- fp[AA] 10104 lw a2, offThread_cardTable(rSELF) # a2 <- card table base 10105 lw t1, offField_clazz(a0) # t1 <- field->clazz 10106 GET_INST_OPCODE(t0) # extract opcode from rINST 10107 # no-op # releasing store 10108 sw a1, offStaticField_value(a0) # field <- vAA 10109 # no-op 10110 beqz a1, 1f 10111 srl t2, t1, GC_CARD_SHIFT 10112 addu t3, a2, t2 10113 sb a2, (t3) 10114 1: 10115 GOTO_OPCODE(t0) # jump to next instruction 10116 10117 /* continuation for OP_SPUT_BOOLEAN */ 10118 10119 .LOP_SPUT_BOOLEAN_finish: 10120 # field ptr in a0 10121 GET_OPA(a2) # a2 <- AA 10122 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10123 GET_VREG(a1, a2) # a1 <- fp[AA] 10124 GET_INST_OPCODE(t0) # extract opcode from rINST 10125 # no-op # releasing store 10126 sw a1, offStaticField_value(a0) # field <- vAA 10127 # no-op 10128 GOTO_OPCODE(t0) # jump to next instruction 10129 10130 /* continuation for OP_SPUT_BYTE */ 10131 10132 .LOP_SPUT_BYTE_finish: 10133 # field ptr in a0 10134 GET_OPA(a2) # a2 <- AA 10135 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10136 GET_VREG(a1, a2) # a1 <- fp[AA] 10137 GET_INST_OPCODE(t0) # extract opcode from rINST 10138 # no-op # releasing store 10139 sw a1, offStaticField_value(a0) # field <- vAA 10140 # no-op 10141 GOTO_OPCODE(t0) # jump to next instruction 10142 10143 /* continuation for OP_SPUT_CHAR */ 10144 10145 .LOP_SPUT_CHAR_finish: 10146 # field ptr in a0 10147 GET_OPA(a2) # a2 <- AA 10148 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10149 GET_VREG(a1, a2) # a1 <- fp[AA] 10150 GET_INST_OPCODE(t0) # extract opcode from rINST 10151 # no-op # releasing store 10152 sw a1, offStaticField_value(a0) # field <- vAA 10153 # no-op 10154 GOTO_OPCODE(t0) # jump to next instruction 10155 10156 /* continuation for OP_SPUT_SHORT */ 10157 10158 .LOP_SPUT_SHORT_finish: 10159 # field ptr in a0 10160 GET_OPA(a2) # a2 <- AA 10161 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10162 GET_VREG(a1, a2) # a1 <- fp[AA] 10163 GET_INST_OPCODE(t0) # extract opcode from rINST 10164 # no-op # releasing store 10165 sw a1, offStaticField_value(a0) # field <- vAA 10166 # no-op 10167 GOTO_OPCODE(t0) # jump to next instruction 10168 10169 /* continuation for OP_INVOKE_VIRTUAL */ 10170 10171 /* 10172 * At this point: 10173 * a0 = resolved base method 10174 * rBIX= C or CCCC (index of first arg, which is the "this" ptr) 10175 */ 10176 .LOP_INVOKE_VIRTUAL_continue: 10177 GET_VREG(rOBJ, rBIX) # rOBJ <- "this" ptr 10178 LOADu2_offMethod_methodIndex(a2, a0) # a2 <- baseMethod->methodIndex 10179 # is "this" null? 10180 beqz rOBJ, common_errNullObject # null "this", throw exception 10181 LOAD_base_offObject_clazz(a3, rOBJ) # a3 <- thisPtr->clazz 10182 LOAD_base_offClassObject_vtable(a3, a3) # a3 <- thisPtr->clazz->vtable 10183 LOAD_eas2(a0, a3, a2) # a0 <- vtable[methodIndex] 10184 b common_invokeMethodNoRange # (a0=method, rOBJ="this") 10185 10186 10187 /* continuation for OP_INVOKE_SUPER */ 10188 10189 /* 10190 * At this point: 10191 * a0 = resolved base method 10192 * rBIX = method->clazz 10193 */ 10194 .LOP_INVOKE_SUPER_continue: 10195 LOAD_base_offClassObject_super(a1, rBIX) # a1 <- method->clazz->super 10196 LOADu2_offMethod_methodIndex(a2, a0) # a2 <- baseMethod->methodIndex 10197 LOAD_base_offClassObject_vtableCount(a3, a1) # a3 <- super->vtableCount 10198 EXPORT_PC() # must export for invoke 10199 # compare (methodIndex, vtableCount) 10200 bgeu a2, a3, .LOP_INVOKE_SUPER_nsm # method not present in superclass 10201 LOAD_base_offClassObject_vtable(a1, a1) # a1 <- ...clazz->super->vtable 10202 LOAD_eas2(a0, a1, a2) # a0 <- vtable[methodIndex] 10203 b common_invokeMethodNoRange # continue on 10204 10205 /* 10206 * Throw a NoSuchMethodError with the method name as the message. 10207 * a0 = resolved base method 10208 */ 10209 .LOP_INVOKE_SUPER_nsm: 10210 LOAD_base_offMethod_name(a1, a0) # a1 <- method name 10211 b common_errNoSuchMethod 10212 10213 10214 /* continuation for OP_INVOKE_STATIC */ 10215 10216 .LOP_INVOKE_STATIC_resolve: 10217 LOAD_rSELF_method(a3) # a3 <- self->method 10218 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 10219 li a2, METHOD_STATIC # resolver method type 10220 JAL(dvmResolveMethod) # v0 <- call(clazz, ref, flags) 10221 move a0, v0 10222 #if defined(WITH_JIT) 10223 /* 10224 * Check to see if we're actively building a trace. If so, 10225 * we need to keep this instruction out of it. 10226 * rBIX: &resolved_methodToCall 10227 */ 10228 lhu a2, offThread_subMode(rSELF) 10229 beqz v0, common_exceptionThrown # null, handle exception 10230 and a2, kSubModeJitTraceBuild # trace under construction? 10231 beqz a2, common_invokeMethodNoRange # no, (a0=method, rOBJ="this") 10232 lw a1, 0(rBIX) # reload resolved method 10233 # finished resloving? 10234 bnez a1, common_invokeMethodNoRange # yes, (a0=method, rOBJ="this") 10235 move rBIX, a0 # preserve method 10236 move a0, rSELF 10237 move a1, rPC 10238 JAL(dvmJitEndTraceSelect) # (self, pc) 10239 move a0, rBIX 10240 b common_invokeMethodNoRange # whew, finally! 10241 #else 10242 # got null? 10243 bnez v0, common_invokeMethodNoRange # (a0=method, rOBJ="this") 10244 b common_exceptionThrown # yes, handle exception 10245 #endif 10246 10247 /* continuation for OP_INVOKE_VIRTUAL_RANGE */ 10248 10249 /* 10250 * At this point: 10251 * a0 = resolved base method 10252 * rBIX= C or CCCC (index of first arg, which is the "this" ptr) 10253 */ 10254 .LOP_INVOKE_VIRTUAL_RANGE_continue: 10255 GET_VREG(rOBJ, rBIX) # rOBJ <- "this" ptr 10256 LOADu2_offMethod_methodIndex(a2, a0) # a2 <- baseMethod->methodIndex 10257 # is "this" null? 10258 beqz rOBJ, common_errNullObject # null "this", throw exception 10259 LOAD_base_offObject_clazz(a3, rOBJ) # a3 <- thisPtr->clazz 10260 LOAD_base_offClassObject_vtable(a3, a3) # a3 <- thisPtr->clazz->vtable 10261 LOAD_eas2(a0, a3, a2) # a0 <- vtable[methodIndex] 10262 b common_invokeMethodRange # (a0=method, rOBJ="this") 10263 10264 10265 /* continuation for OP_INVOKE_SUPER_RANGE */ 10266 10267 /* 10268 * At this point: 10269 * a0 = resolved base method 10270 * rBIX = method->clazz 10271 */ 10272 .LOP_INVOKE_SUPER_RANGE_continue: 10273 LOAD_base_offClassObject_super(a1, rBIX) # a1 <- method->clazz->super 10274 LOADu2_offMethod_methodIndex(a2, a0) # a2 <- baseMethod->methodIndex 10275 LOAD_base_offClassObject_vtableCount(a3, a1) # a3 <- super->vtableCount 10276 EXPORT_PC() # must export for invoke 10277 # compare (methodIndex, vtableCount) 10278 bgeu a2, a3, .LOP_INVOKE_SUPER_RANGE_nsm # method not present in superclass 10279 LOAD_base_offClassObject_vtable(a1, a1) # a1 <- ...clazz->super->vtable 10280 LOAD_eas2(a0, a1, a2) # a0 <- vtable[methodIndex] 10281 b common_invokeMethodRange # continue on 10282 10283 /* 10284 * Throw a NoSuchMethodError with the method name as the message. 10285 * a0 = resolved base method 10286 */ 10287 .LOP_INVOKE_SUPER_RANGE_nsm: 10288 LOAD_base_offMethod_name(a1, a0) # a1 <- method name 10289 b common_errNoSuchMethod 10290 10291 10292 /* continuation for OP_INVOKE_STATIC_RANGE */ 10293 10294 .LOP_INVOKE_STATIC_RANGE_resolve: 10295 LOAD_rSELF_method(a3) # a3 <- self->method 10296 LOAD_base_offMethod_clazz(a0, a3) # a0 <- method->clazz 10297 li a2, METHOD_STATIC # resolver method type 10298 JAL(dvmResolveMethod) # v0 <- call(clazz, ref, flags) 10299 move a0, v0 10300 #if defined(WITH_JIT) 10301 /* 10302 * Check to see if we're actively building a trace. If so, 10303 * we need to keep this instruction out of it. 10304 * rBIX: &resolved_methodToCall 10305 */ 10306 lhu a2, offThread_subMode(rSELF) 10307 beqz v0, common_exceptionThrown # null, handle exception 10308 and a2, kSubModeJitTraceBuild # trace under construction? 10309 beqz a2, common_invokeMethodRange # no, (a0=method, rOBJ="this") 10310 lw a1, 0(rBIX) # reload resolved method 10311 # finished resloving? 10312 bnez a1, common_invokeMethodRange # yes, (a0=method, rOBJ="this") 10313 move rBIX, a0 # preserve method 10314 move a0, rSELF 10315 move a1, rPC 10316 JAL(dvmJitEndTraceSelect) # (self, pc) 10317 move a0, rBIX 10318 b common_invokeMethodRange # whew, finally! 10319 #else 10320 # got null? 10321 bnez v0, common_invokeMethodRange # (a0=method, rOBJ="this") 10322 b common_exceptionThrown # yes, handle exception 10323 #endif 10324 10325 /* continuation for OP_FLOAT_TO_INT */ 10326 10327 /* 10328 * Not an entry point as it is used only once !! 10329 */ 10330 f2i_doconv: 10331 #ifdef SOFT_FLOAT 10332 li a1, 0x4f000000 # (float)maxint 10333 move rBIX, a0 10334 JAL(__gesf2) # is arg >= maxint? 10335 move t0, v0 10336 li v0, ~0x80000000 # return maxint (7fffffff) 10337 bgez t0, .LOP_FLOAT_TO_INT_set_vreg 10338 10339 move a0, rBIX # recover arg 10340 li a1, 0xcf000000 # (float)minint 10341 JAL(__lesf2) 10342 10343 move t0, v0 10344 li v0, 0x80000000 # return minint (80000000) 10345 blez t0, .LOP_FLOAT_TO_INT_set_vreg 10346 move a0, rBIX 10347 move a1, rBIX 10348 JAL(__nesf2) 10349 10350 move t0, v0 10351 li v0, 0 # return zero for NaN 10352 bnez t0, .LOP_FLOAT_TO_INT_set_vreg 10353 10354 move a0, rBIX 10355 JAL(__fixsfsi) 10356 b .LOP_FLOAT_TO_INT_set_vreg 10357 #else 10358 l.s fa1, .LFLOAT_TO_INT_max 10359 c.ole.s fcc0, fa1, fa0 10360 l.s fv0, .LFLOAT_TO_INT_ret_max 10361 bc1t .LOP_FLOAT_TO_INT_set_vreg_f 10362 10363 l.s fa1, .LFLOAT_TO_INT_min 10364 c.ole.s fcc0, fa0, fa1 10365 l.s fv0, .LFLOAT_TO_INT_ret_min 10366 bc1t .LOP_FLOAT_TO_INT_set_vreg_f 10367 10368 mov.s fa1, fa0 10369 c.un.s fcc0, fa0, fa1 10370 li.s fv0, 0 10371 bc1t .LOP_FLOAT_TO_INT_set_vreg_f 10372 10373 trunc.w.s fv0, fa0 10374 b .LOP_FLOAT_TO_INT_set_vreg_f 10375 #endif 10376 10377 .LFLOAT_TO_INT_max: 10378 .word 0x4f000000 10379 .LFLOAT_TO_INT_min: 10380 .word 0xcf000000 10381 .LFLOAT_TO_INT_ret_max: 10382 .word 0x7fffffff 10383 .LFLOAT_TO_INT_ret_min: 10384 .word 0x80000000 10385 10386 10387 /* continuation for OP_FLOAT_TO_LONG */ 10388 10389 f2l_doconv: 10390 #ifdef SOFT_FLOAT 10391 li a1, 0x5f000000 10392 move rBIX, a0 10393 JAL(__gesf2) 10394 10395 move t0, v0 10396 li rRESULT0, ~0 10397 li rRESULT1, ~0x80000000 10398 bgez t0, .LOP_FLOAT_TO_LONG_set_vreg 10399 10400 move a0, rBIX 10401 li a1, 0xdf000000 10402 JAL(__lesf2) 10403 10404 move t0, v0 10405 li rRESULT0, 0 10406 li rRESULT1, 0x80000000 10407 blez t0, .LOP_FLOAT_TO_LONG_set_vreg 10408 10409 move a0, rBIX 10410 move a1, rBIX 10411 JAL(__nesf2) 10412 10413 move t0, v0 10414 li rRESULT0, 0 10415 li rRESULT1, 0 10416 bnez t0, .LOP_FLOAT_TO_LONG_set_vreg 10417 10418 move a0, rBIX 10419 JAL(__fixsfdi) 10420 10421 #else 10422 l.s fa1, .LLONG_TO_max 10423 c.ole.s fcc0, fa1, fa0 10424 li rRESULT0, ~0 10425 li rRESULT1, ~0x80000000 10426 bc1t .LOP_FLOAT_TO_LONG_set_vreg 10427 10428 l.s fa1, .LLONG_TO_min 10429 c.ole.s fcc0, fa0, fa1 10430 li rRESULT0, 0 10431 li rRESULT1, 0x80000000 10432 bc1t .LOP_FLOAT_TO_LONG_set_vreg 10433 10434 mov.s fa1, fa0 10435 c.un.s fcc0, fa0, fa1 10436 li rRESULT0, 0 10437 li rRESULT1, 0 10438 bc1t .LOP_FLOAT_TO_LONG_set_vreg 10439 10440 JAL(__fixsfdi) 10441 #endif 10442 10443 b .LOP_FLOAT_TO_LONG_set_vreg 10444 10445 .LLONG_TO_max: 10446 .word 0x5f000000 10447 10448 .LLONG_TO_min: 10449 .word 0xdf000000 10450 10451 /* continuation for OP_DOUBLE_TO_INT */ 10452 10453 10454 d2i_doconv: 10455 #ifdef SOFT_FLOAT 10456 la t0, .LDOUBLE_TO_INT_max 10457 LOAD64(rARG2, rARG3, t0) 10458 move rBIX, rARG0 # save a0 10459 move rTEMP, rARG1 # and a1 10460 JAL(__gedf2) # is arg >= maxint? 10461 10462 move t0, v0 10463 li v0, ~0x80000000 # return maxint (7fffffff) 10464 bgez t0, .LOP_DOUBLE_TO_INT_set_vreg # nonzero == yes 10465 10466 move rARG0, rBIX # recover arg 10467 move rARG1, rTEMP 10468 la t0, .LDOUBLE_TO_INT_min 10469 LOAD64(rARG2, rARG3, t0) 10470 JAL(__ledf2) # is arg <= minint? 10471 10472 move t0, v0 10473 li v0, 0x80000000 # return minint (80000000) 10474 blez t0, .LOP_DOUBLE_TO_INT_set_vreg # nonzero == yes 10475 10476 move rARG0, rBIX # recover arg 10477 move rARG1, rTEMP 10478 move rARG2, rBIX # compare against self 10479 move rARG3, rTEMP 10480 JAL(__nedf2) # is arg == self? 10481 10482 move t0, v0 # zero == no 10483 li v0, 0 10484 bnez t0, .LOP_DOUBLE_TO_INT_set_vreg # return zero for NaN 10485 10486 move rARG0, rBIX # recover arg 10487 move rARG1, rTEMP 10488 JAL(__fixdfsi) # convert double to int 10489 b .LOP_DOUBLE_TO_INT_set_vreg 10490 #else 10491 la t0, .LDOUBLE_TO_INT_max 10492 LOAD64_F(fa1, fa1f, t0) 10493 c.ole.d fcc0, fa1, fa0 10494 l.s fv0, .LDOUBLE_TO_INT_maxret 10495 bc1t .LOP_DOUBLE_TO_INT_set_vreg_f 10496 10497 la t0, .LDOUBLE_TO_INT_min 10498 LOAD64_F(fa1, fa1f, t0) 10499 c.ole.d fcc0, fa0, fa1 10500 l.s fv0, .LDOUBLE_TO_INT_minret 10501 bc1t .LOP_DOUBLE_TO_INT_set_vreg_f 10502 10503 mov.d fa1, fa0 10504 c.un.d fcc0, fa0, fa1 10505 li.s fv0, 0 10506 bc1t .LOP_DOUBLE_TO_INT_set_vreg_f 10507 10508 trunc.w.d fv0, fa0 10509 b .LOP_DOUBLE_TO_INT_set_vreg_f 10510 #endif 10511 10512 10513 .LDOUBLE_TO_INT_max: 10514 .dword 0x41dfffffffc00000 10515 .LDOUBLE_TO_INT_min: 10516 .dword 0xc1e0000000000000 # minint, as a double (high word) 10517 .LDOUBLE_TO_INT_maxret: 10518 .word 0x7fffffff 10519 .LDOUBLE_TO_INT_minret: 10520 .word 0x80000000 10521 10522 /* continuation for OP_DOUBLE_TO_LONG */ 10523 10524 d2l_doconv: 10525 #ifdef SOFT_FLOAT 10526 la t0, .LDOUBLE_TO_LONG_max 10527 LOAD64(rARG2, rARG3, t0) 10528 move rBIX, rARG0 # save a0 10529 move rTEMP, rARG1 # and a1 10530 JAL(__gedf2) 10531 10532 move t1, v0 10533 la t0, .LDOUBLE_TO_LONG_ret_max 10534 LOAD64(rRESULT0, rRESULT1, t0) 10535 bgez t1, .LOP_DOUBLE_TO_LONG_set_vreg 10536 10537 move rARG0, rBIX 10538 move rARG1, rTEMP 10539 la t0, .LDOUBLE_TO_LONG_min 10540 LOAD64(rARG2, rARG3, t0) 10541 JAL(__ledf2) 10542 10543 move t1, v0 10544 la t0, .LDOUBLE_TO_LONG_ret_min 10545 LOAD64(rRESULT0, rRESULT1, t0) 10546 blez t1, .LOP_DOUBLE_TO_LONG_set_vreg 10547 10548 move rARG0, rBIX 10549 move rARG1, rTEMP 10550 move rARG2, rBIX 10551 move rARG3, rTEMP 10552 JAL(__nedf2) 10553 10554 move t0, v0 10555 li rRESULT0, 0 10556 li rRESULT1, 0 10557 bnez t0, .LOP_DOUBLE_TO_LONG_set_vreg 10558 10559 move rARG0, rBIX 10560 move rARG1, rTEMP 10561 JAL(__fixdfdi) 10562 10563 #else 10564 la t0, .LDOUBLE_TO_LONG_max 10565 LOAD64_F(fa1, fa1f, t0) 10566 c.ole.d fcc0, fa1, fa0 10567 la t0, .LDOUBLE_TO_LONG_ret_max 10568 LOAD64(rRESULT0, rRESULT1, t0) 10569 bc1t .LOP_DOUBLE_TO_LONG_set_vreg 10570 10571 la t0, .LDOUBLE_TO_LONG_min 10572 LOAD64_F(fa1, fa1f, t0) 10573 c.ole.d fcc0, fa0, fa1 10574 la t0, .LDOUBLE_TO_LONG_ret_min 10575 LOAD64(rRESULT0, rRESULT1, t0) 10576 bc1t .LOP_DOUBLE_TO_LONG_set_vreg 10577 10578 mov.d fa1, fa0 10579 c.un.d fcc0, fa0, fa1 10580 li rRESULT0, 0 10581 li rRESULT1, 0 10582 bc1t .LOP_DOUBLE_TO_LONG_set_vreg 10583 JAL(__fixdfdi) 10584 #endif 10585 b .LOP_DOUBLE_TO_LONG_set_vreg 10586 10587 10588 .LDOUBLE_TO_LONG_max: 10589 .dword 0x43e0000000000000 # maxlong, as a double (high word) 10590 .LDOUBLE_TO_LONG_min: 10591 .dword 0xc3e0000000000000 # minlong, as a double (high word) 10592 .LDOUBLE_TO_LONG_ret_max: 10593 .dword 0x7fffffffffffffff 10594 .LDOUBLE_TO_LONG_ret_min: 10595 .dword 0x8000000000000000 10596 10597 /* continuation for OP_MUL_LONG */ 10598 10599 .LOP_MUL_LONG_finish: 10600 GET_INST_OPCODE(t0) # extract opcode from rINST 10601 STORE64(v0, v1, a0) # vAA::vAA+1 <- v0(low) :: v1(high) 10602 GOTO_OPCODE(t0) # jump to next instruction 10603 10604 10605 /* continuation for OP_IGET_VOLATILE */ 10606 10607 /* 10608 * Currently: 10609 * v0 holds resolved field 10610 * rOBJ holds object (caller saved) 10611 */ 10612 .LOP_IGET_VOLATILE_finish: 10613 #BAL(common_squeak0) 10614 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 10615 # check object for null 10616 beqz rOBJ, common_errNullObject # object was null 10617 addu a3, a3, rOBJ # form address 10618 lw a0, (a3) # a0 <- obj.field (8/16/32 bits) 10619 SMP_DMB # acquiring load 10620 GET_OPA4(a2) # a2 <- A+ 10621 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10622 GET_INST_OPCODE(t0) # extract opcode from rINST 10623 SET_VREG(a0, a2) # fp[A] <- a0 10624 GOTO_OPCODE(t0) # jump to next instruction 10625 10626 10627 /* continuation for OP_IPUT_VOLATILE */ 10628 10629 /* 10630 * Currently: 10631 * a0 holds resolved field 10632 * rOBJ holds object 10633 */ 10634 .LOP_IPUT_VOLATILE_finish: 10635 #BAL(common_squeak0) 10636 GET_OPA4(a1) # a1 <- A+ 10637 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 10638 GET_VREG(a0, a1) # a0 <- fp[A] 10639 # check object for null 10640 beqz rOBJ, common_errNullObject # object was null 10641 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10642 GET_INST_OPCODE(t0) # extract opcode from rINST 10643 addu rOBJ, rOBJ, a3 # form address 10644 SMP_DMB_ST # releasing store 10645 sw a0, (rOBJ) # obj.field (8/16/32 bits) <- a0 10646 SMP_DMB 10647 GOTO_OPCODE(t0) # jump to next instruction 10648 10649 10650 /* continuation for OP_SGET_VOLATILE */ 10651 10652 .LOP_SGET_VOLATILE_finish: 10653 LOAD_base_offStaticField_value(a1, a0) # a1 <- field value 10654 SMP_DMB # acquiring load 10655 GET_OPA(a2) # a2 <- AA 10656 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10657 GET_INST_OPCODE(t0) # extract opcode from rINST 10658 SET_VREG_GOTO(a1, a2, t0) # fp[AA] <- a1 10659 10660 /* continuation for OP_SPUT_VOLATILE */ 10661 10662 .LOP_SPUT_VOLATILE_finish: 10663 # field ptr in a0 10664 GET_OPA(a2) # a2 <- AA 10665 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10666 GET_VREG(a1, a2) # a1 <- fp[AA] 10667 GET_INST_OPCODE(t0) # extract opcode from rINST 10668 SMP_DMB_ST # releasing store 10669 sw a1, offStaticField_value(a0) # field <- vAA 10670 SMP_DMB 10671 GOTO_OPCODE(t0) # jump to next instruction 10672 10673 /* continuation for OP_IGET_OBJECT_VOLATILE */ 10674 10675 /* 10676 * Currently: 10677 * v0 holds resolved field 10678 * rOBJ holds object (caller saved) 10679 */ 10680 .LOP_IGET_OBJECT_VOLATILE_finish: 10681 #BAL(common_squeak0) 10682 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 10683 # check object for null 10684 beqz rOBJ, common_errNullObject # object was null 10685 addu a3, a3, rOBJ # form address 10686 lw a0, (a3) # a0 <- obj.field (8/16/32 bits) 10687 SMP_DMB # acquiring load 10688 GET_OPA4(a2) # a2 <- A+ 10689 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10690 GET_INST_OPCODE(t0) # extract opcode from rINST 10691 SET_VREG(a0, a2) # fp[A] <- a0 10692 GOTO_OPCODE(t0) # jump to next instruction 10693 10694 10695 /* continuation for OP_IGET_WIDE_VOLATILE */ 10696 10697 /* 10698 * Currently: 10699 * a0 holds resolved field 10700 * rOBJ holds object 10701 */ 10702 .LOP_IGET_WIDE_VOLATILE_finish: 10703 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 10704 beqz rOBJ, common_errNullObject # object was null 10705 GET_OPA4(a2) # a2 <- A+ 10706 addu rOBJ, rOBJ, a3 # form address 10707 .if 1 10708 vLOAD64(a0, a1, rOBJ) # a0/a1 <- obj.field (64-bit align ok) 10709 .else 10710 LOAD64(a0, a1, rOBJ) # a0/a1 <- obj.field (64-bit align ok) 10711 .endif 10712 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10713 EAS2(a3, rFP, a2) # a3 <- &fp[A] 10714 GET_INST_OPCODE(t0) # extract opcode from rINST 10715 STORE64(a0, a1, a3) # fp[A] <- a0/a1 10716 GOTO_OPCODE(t0) # jump to next instruction 10717 10718 10719 /* continuation for OP_IPUT_WIDE_VOLATILE */ 10720 10721 /* 10722 * Currently: 10723 * a0 holds resolved field 10724 * rOBJ holds object 10725 */ 10726 .LOP_IPUT_WIDE_VOLATILE_finish: 10727 GET_OPA4(a2) # a2 <- A+ 10728 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 10729 EAS2(a2, rFP, a2) # a2 <- &fp[A] 10730 # check object for null 10731 beqz rOBJ, common_errNullObject # object was null 10732 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10733 LOAD64(a0, a1, a2) # a0/a1 <- fp[A] 10734 GET_INST_OPCODE(rBIX) # extract opcode from rINST 10735 addu a2, rOBJ, a3 # form address 10736 .if 1 10737 JAL(dvmQuasiAtomicSwap64Sync) # stores r0/r1 into addr r2 10738 # STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0 a1 10739 .else 10740 STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0 a1 10741 .endif 10742 GOTO_OPCODE(rBIX) # jump to next instruction 10743 10744 10745 /* continuation for OP_SGET_WIDE_VOLATILE */ 10746 10747 .LOP_SGET_WIDE_VOLATILE_finish: 10748 GET_OPA(a1) # a1 <- AA 10749 .if 1 10750 vLOAD64_off(a2, a3, a0, offStaticField_value) # a2/a3 <- field value (aligned) 10751 .else 10752 LOAD64_off(a2, a3, a0, offStaticField_value) # a2/a3 <- field value (aligned) 10753 .endif 10754 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10755 EAS2(a1, rFP, a1) # a1 <- &fp[AA] 10756 STORE64(a2, a3, a1) # vAA/vAA+1 <- a2/a3 10757 GET_INST_OPCODE(t0) # extract opcode from rINST 10758 GOTO_OPCODE(t0) # jump to next instruction 10759 10760 10761 10762 /* continuation for OP_SPUT_WIDE_VOLATILE */ 10763 10764 /* 10765 * Continuation if the field has not yet been resolved. 10766 * a1: BBBB field ref 10767 * rOBJ: &fp[AA] 10768 * rBIX: dvmDex->pResFields 10769 * 10770 * Returns StaticField pointer in a2. 10771 */ 10772 .LOP_SPUT_WIDE_VOLATILE_resolve: 10773 LOAD_rSELF_method(a2) # a2 <- current method 10774 #if defined(WITH_JIT) 10775 EAS2(rBIX, rBIX, a1) # rBIX<- &dvmDex->pResFields[field] 10776 #endif 10777 EXPORT_PC() # resolve() could throw, so export now 10778 LOAD_base_offMethod_clazz(a0, a2) # a0 <- method->clazz 10779 JAL(dvmResolveStaticField) # v0 <- resolved StaticField ptr 10780 # success ? 10781 move a0, v0 10782 beqz v0, common_exceptionThrown # no, handle exception 10783 #if defined(WITH_JIT) 10784 /* 10785 * If the JIT is actively building a trace we need to make sure 10786 * that the field is fully resolved before including this instruction. 10787 */ 10788 JAL(common_verifyField) 10789 #endif 10790 move a2, v0 10791 b .LOP_SPUT_WIDE_VOLATILE_finish # resume 10792 10793 /* continuation for OP_EXECUTE_INLINE */ 10794 10795 /* 10796 * Extract args, call function. 10797 * a0 = #of args (0-4) 10798 * rBIX = call index 10799 * 10800 * Other ideas: 10801 * - Use a jump table from the main piece to jump directly into the 10802 * AND/LW pairs. Costs a data load, saves a branch. 10803 * - Have five separate pieces that do the loading, so we can work the 10804 * interleave a little better. Increases code size. 10805 */ 10806 .LOP_EXECUTE_INLINE_continue: 10807 FETCH(rINST, 2) # rINST <- FEDC 10808 beq a0, 0, 0f 10809 beq a0, 1, 1f 10810 beq a0, 2, 2f 10811 beq a0, 3, 3f 10812 beq a0, 4, 4f 10813 JAL(common_abort) # too many arguments 10814 10815 4: 10816 and t0, rINST, 0xf000 # isolate F 10817 ESRN(t1, rFP, t0, 10) 10818 lw a3, 0(t1) # a3 <- vF (shift right 12, left 2) 10819 3: 10820 and t0, rINST, 0x0f00 # isolate E 10821 ESRN(t1, rFP, t0, 6) 10822 lw a2, 0(t1) # a2 <- vE 10823 2: 10824 and t0, rINST, 0x00f0 # isolate D 10825 ESRN(t1, rFP, t0, 2) 10826 lw a1, 0(t1) # a1 <- vD 10827 1: 10828 and t0, rINST, 0x000f # isolate C 10829 EASN(t1, rFP, t0, 2) 10830 lw a0, 0(t1) # a0 <- vC 10831 0: 10832 la rINST, gDvmInlineOpsTable # table of InlineOperation 10833 EAS4(t1, rINST, rBIX) # t1 <- rINST + rBIX<<4 10834 lw t9, 0(t1) 10835 jr t9 # sizeof=16, "func" is first entry 10836 # (not reached) 10837 10838 /* 10839 * We're debugging or profiling. 10840 * rBIX: opIndex 10841 */ 10842 .LOP_EXECUTE_INLINE_debugmode: 10843 move a0, rBIX 10844 JAL(dvmResolveInlineNative) 10845 beqz v0, .LOP_EXECUTE_INLINE_resume # did it resolve? no, just move on 10846 move rOBJ, v0 # remember method 10847 move a0, v0 10848 move a1, rSELF 10849 JAL(dvmFastMethodTraceEnter) # (method, self) 10850 addu a1, rSELF, offThread_retval # a1<- &self->retval 10851 GET_OPB(a0) # a0 <- B 10852 # Stack should have 16/20 available 10853 sw a1, 16(sp) # push &self->retval 10854 BAL(.LOP_EXECUTE_INLINE_continue) # make call; will return after 10855 lw gp, STACK_OFFSET_GP(sp) # restore gp 10856 move rINST, v0 # save result of inline 10857 move a0, rOBJ # a0<- method 10858 move a1, rSELF # a1<- self 10859 JAL(dvmFastMethodTraceExit) # (method, self) 10860 beqz v0, common_exceptionThrown # returned false, handle exception 10861 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 10862 GET_INST_OPCODE(t0) # extract opcode from rINST 10863 GOTO_OPCODE(t0) # jump to next instruction 10864 10865 /* continuation for OP_EXECUTE_INLINE_RANGE */ 10866 10867 /* 10868 * Extract args, call function. 10869 * a0 = #of args (0-4) 10870 * rBIX = call index 10871 * ra = return addr, above [DO NOT JAL out of here w/o preserving ra] 10872 */ 10873 .LOP_EXECUTE_INLINE_RANGE_continue: 10874 FETCH(rOBJ, 2) # rOBJ <- CCCC 10875 beq a0, 0, 0f 10876 beq a0, 1, 1f 10877 beq a0, 2, 2f 10878 beq a0, 3, 3f 10879 beq a0, 4, 4f 10880 JAL(common_abort) # too many arguments 10881 10882 4: 10883 add t0, rOBJ, 3 10884 GET_VREG(a3, t0) 10885 3: 10886 add t0, rOBJ, 2 10887 GET_VREG(a2, t0) 10888 2: 10889 add t0, rOBJ, 1 10890 GET_VREG(a1, t0) 10891 1: 10892 GET_VREG(a0, rOBJ) 10893 0: 10894 la rOBJ, gDvmInlineOpsTable # table of InlineOperation 10895 EAS4(t1, rOBJ, rBIX) # t1 <- rINST + rBIX<<4 10896 lw t9, 0(t1) 10897 jr t9 # sizeof=16, "func" is first entry 10898 # not reached 10899 10900 /* 10901 * We're debugging or profiling. 10902 * rBIX: opIndex 10903 */ 10904 .LOP_EXECUTE_INLINE_RANGE_debugmode: 10905 move a0, rBIX 10906 JAL(dvmResolveInlineNative) 10907 beqz v0, .LOP_EXECUTE_INLINE_RANGE_resume # did it resolve? no, just move on 10908 move rOBJ, v0 # remember method 10909 move a0, v0 10910 move a1, rSELF 10911 JAL(dvmFastMethodTraceEnter) # (method, self) 10912 addu a1, rSELF, offThread_retval # a1<- &self->retval 10913 GET_OPA(a0) # a0 <- A 10914 # Stack should have 16/20 available 10915 sw a1, 16(sp) # push &self->retval 10916 move rINST, rOBJ # rINST<- method 10917 BAL(.LOP_EXECUTE_INLINE_RANGE_continue) # make call; will return after 10918 lw gp, STACK_OFFSET_GP(sp) # restore gp 10919 move rOBJ, v0 # save result of inline 10920 move a0, rINST # a0<- method 10921 move a1, rSELF # a1<- self 10922 JAL(dvmFastNativeMethodTraceExit) # (method, self) 10923 beqz rOBJ, common_exceptionThrown # returned false, handle exception 10924 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 10925 GET_INST_OPCODE(t0) # extract opcode from rINST 10926 GOTO_OPCODE(t0) # jump to next instruction 10927 10928 /* continuation for OP_INVOKE_OBJECT_INIT_RANGE */ 10929 /* 10930 * A debugger is attached, so we need to go ahead and do 10931 * this. For simplicity, we'll just jump directly to the 10932 * corresponding handler. Note that we can't use 10933 * rIBASE here because it may be in single-step mode. 10934 * Load the primary table base directly. 10935 */ 10936 .LOP_INVOKE_OBJECT_INIT_RANGE_debugger: 10937 lw a1, offThread_mainHandlerTable(rSELF) 10938 .if 0 10939 li t0, OP_INVOKE_DIRECT_JUMBO 10940 .else 10941 li t0, OP_INVOKE_DIRECT_RANGE 10942 .endif 10943 GOTO_OPCODE_BASE(a1, t0) # execute it 10944 10945 /* continuation for OP_IPUT_OBJECT_VOLATILE */ 10946 10947 /* 10948 * Currently: 10949 * a0 holds resolved field 10950 * rOBJ holds object 10951 */ 10952 .LOP_IPUT_OBJECT_VOLATILE_finish: 10953 #BAL(common_squeak0) 10954 GET_OPA4(a1) # a1 <- A+ 10955 LOAD_base_offInstField_byteOffset(a3, a0) # a3 <- byte offset of field 10956 GET_VREG(a0, a1) # a0 <- fp[A] 10957 lw a2, offThread_cardTable(rSELF) # a2 <- card table base 10958 # check object for null 10959 beqz rOBJ, common_errNullObject # object was null 10960 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10961 GET_INST_OPCODE(t0) # extract opcode from rINST 10962 addu t2, rOBJ, a3 # form address 10963 SMP_DMB_ST # releasing store 10964 sw a0, (t2) # obj.field (32 bits) <- a0 10965 SMP_DMB 10966 beqz a0, 1f # stored a null reference? 10967 srl t1, rOBJ, GC_CARD_SHIFT 10968 addu t2, a2, t1 10969 sb a2, (t2) # mark card if not 10970 1: 10971 GOTO_OPCODE(t0) # jump to next instruction 10972 10973 10974 /* continuation for OP_SGET_OBJECT_VOLATILE */ 10975 10976 .LOP_SGET_OBJECT_VOLATILE_finish: 10977 LOAD_base_offStaticField_value(a1, a0) # a1 <- field value 10978 SMP_DMB # acquiring load 10979 GET_OPA(a2) # a2 <- AA 10980 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10981 GET_INST_OPCODE(t0) # extract opcode from rINST 10982 SET_VREG_GOTO(a1, a2, t0) # fp[AA] <- a1 10983 10984 /* continuation for OP_SPUT_OBJECT_VOLATILE */ 10985 .LOP_SPUT_OBJECT_VOLATILE_finish: # field ptr in a0 10986 GET_OPA(a2) # a2 <- AA 10987 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 10988 GET_VREG(a1, a2) # a1 <- fp[AA] 10989 lw a2, offThread_cardTable(rSELF) # a2 <- card table base 10990 lw t1, offField_clazz(a0) # t1 <- field->clazz 10991 GET_INST_OPCODE(t0) # extract opcode from rINST 10992 SMP_DMB_ST # releasing store 10993 sw a1, offStaticField_value(a0) # field <- vAA 10994 SMP_DMB 10995 beqz a1, 1f 10996 srl t2, t1, GC_CARD_SHIFT 10997 addu t3, a2, t2 10998 sb a2, (t3) 10999 1: 11000 GOTO_OPCODE(t0) # jump to next instruction 11001 11002 .size dvmAsmSisterStart, .-dvmAsmSisterStart 11003 .global dvmAsmSisterEnd 11004 dvmAsmSisterEnd: 11005 11006 /* File: mips/footer.S */ 11007 /* 11008 * =========================================================================== 11009 * Common subroutines and data 11010 * =========================================================================== 11011 */ 11012 11013 .text 11014 .align 2 11015 11016 #if defined(WITH_JIT) 11017 #if defined(WITH_SELF_VERIFICATION) 11018 11019 /* 11020 * "longjmp" to a translation after single-stepping. Before returning 11021 * to translation, must save state for self-verification. 11022 */ 11023 .global dvmJitResumeTranslation # (Thread* self, u4* dFP) 11024 dvmJitResumeTranslation: 11025 move rSELF, a0 # restore self 11026 move rPC, a1 # restore Dalvik pc 11027 move rFP, a2 # restore Dalvik fp 11028 lw rBIX, offThread_jitResumeNPC(rSELF) 11029 sw zero, offThread_jitResumeNPC(rSELF) # reset resume address 11030 lw sp, offThread_jitResumeNSP(rSELF) # cut back native stack 11031 b jitSVShadowRunStart # resume as if cache hit 11032 # expects resume addr in rBIX 11033 11034 .global dvmJitToInterpPunt 11035 dvmJitToInterpPunt: 11036 li a2, kSVSPunt # a2 <- interpreter entry point 11037 sw zero, offThread_inJitCodeCache(rSELF) # Back to the interp land 11038 b jitSVShadowRunEnd # doesn't return 11039 11040 .global dvmJitToInterpSingleStep 11041 dvmJitToInterpSingleStep: 11042 move rPC, a0 # set up dalvik pc 11043 EXPORT_PC() 11044 sw ra, offThread_jitResumeNPC(rSELF) 11045 sw a1, offThread_jitResumeDPC(rSELF) 11046 li a2, kSVSSingleStep # a2 <- interpreter entry point 11047 b jitSVShadowRunEnd # doesn't return 11048 11049 .global dvmJitToInterpNoChainNoProfile 11050 dvmJitToInterpNoChainNoProfile: 11051 move a0, rPC # pass our target PC 11052 li a2, kSVSNoProfile # a2 <- interpreter entry point 11053 sw zero, offThread_inJitCodeCache(rSELF) # Back to the interp land 11054 b jitSVShadowRunEnd # doesn't return 11055 11056 .global dvmJitToInterpTraceSelectNoChain 11057 dvmJitToInterpTraceSelectNoChain: 11058 move a0, rPC # pass our target PC 11059 li a2, kSVSTraceSelect # a2 <- interpreter entry point 11060 sw zero, offThread_inJitCodeCache(rSELF) # Back to the interp land 11061 b jitSVShadowRunEnd # doesn't return 11062 11063 .global dvmJitToInterpTraceSelect 11064 dvmJitToInterpTraceSelect: 11065 lw a0, 0(ra) # pass our target PC 11066 li a2, kSVSTraceSelect # a2 <- interpreter entry point 11067 sw zero, offThread_inJitCodeCache(rSELF) # Back to the interp land 11068 b jitSVShadowRunEnd # doesn't return 11069 11070 .global dvmJitToInterpBackwardBranch 11071 dvmJitToInterpBackwardBranch: 11072 lw a0, 0(ra) # pass our target PC 11073 li a2, kSVSBackwardBranch # a2 <- interpreter entry point 11074 sw zero, offThread_inJitCodeCache(rSELF) # Back to the interp land 11075 b jitSVShadowRunEnd # doesn't return 11076 11077 .global dvmJitToInterpNormal 11078 dvmJitToInterpNormal: 11079 lw a0, 0(ra) # pass our target PC 11080 li a2, kSVSNormal # a2 <- interpreter entry point 11081 sw zero, offThread_inJitCodeCache(rSELF) # Back to the interp land 11082 b jitSVShadowRunEnd # doesn't return 11083 11084 .global dvmJitToInterpNoChain 11085 dvmJitToInterpNoChain: 11086 move a0, rPC # pass our target PC 11087 li a2, kSVSNoChain # a2 <- interpreter entry point 11088 sw zero, offThread_inJitCodeCache(rSELF) # Back to the interp land 11089 b jitSVShadowRunEnd # doesn't return 11090 #else /* WITH_SELF_VERIFICATION */ 11091 11092 11093 /* 11094 * "longjmp" to a translation after single-stepping. 11095 */ 11096 .global dvmJitResumeTranslation # (Thread* self, u4* dFP) 11097 dvmJitResumeTranslation: 11098 move rSELF, a0 # restore self 11099 move rPC, a1 # restore Dalvik pc 11100 move rFP, a2 # restore Dalvik fp 11101 lw a0, offThread_jitResumeNPC(rSELF) 11102 sw zero, offThread_jitResumeNPC(rSELF) # reset resume address 11103 lw sp, offThread_jitResumeNSP(rSELF) # cut back native stack 11104 jr a0 # resume translation 11105 11106 11107 /* 11108 * Return from the translation cache to the interpreter when the compiler is 11109 * having issues translating/executing a Dalvik instruction. We have to skip 11110 * the code cache lookup otherwise it is possible to indefinitely bouce 11111 * between the interpreter and the code cache if the instruction that fails 11112 * to be compiled happens to be at a trace start. 11113 */ 11114 .global dvmJitToInterpPunt 11115 dvmJitToInterpPunt: 11116 lw gp, STACK_OFFSET_GP(sp) 11117 move rPC, a0 11118 #if defined(WITH_JIT_TUNING) 11119 move a0, ra 11120 JAL(dvmBumpPunt) 11121 #endif 11122 EXPORT_PC() 11123 sw zero, offThread_inJitCodeCache(rSELF) # Back to the interp land 11124 lw rIBASE, offThread_curHandlerTable(rSELF) 11125 FETCH_INST() 11126 GET_INST_OPCODE(t0) 11127 GOTO_OPCODE(t0) 11128 11129 /* 11130 * Return to the interpreter to handle a single instruction. 11131 * On entry: 11132 * rPC <= Dalvik PC of instrucion to interpret 11133 * a1 <= Dalvik PC of resume instruction 11134 * ra <= resume point in translation 11135 */ 11136 11137 .global dvmJitToInterpSingleStep 11138 dvmJitToInterpSingleStep: 11139 lw gp, STACK_OFFSET_GP(sp) 11140 move rPC, a0 # set up dalvik pc 11141 EXPORT_PC() 11142 sw ra, offThread_jitResumeNPC(rSELF) 11143 sw sp, offThread_jitResumeNSP(rSELF) 11144 sw a1, offThread_jitResumeDPC(rSELF) 11145 li a1, 1 11146 sw a1, offThread_singleStepCount(rSELF) # just step once 11147 move a0, rSELF 11148 li a1, kSubModeCountedStep 11149 JAL(dvmEnableSubMode) # (self, subMode) 11150 lw rIBASE, offThread_curHandlerTable(rSELF) 11151 FETCH_INST() 11152 GET_INST_OPCODE(t0) 11153 GOTO_OPCODE(t0) 11154 /* 11155 * Return from the translation cache and immediately request 11156 * a translation for the exit target. Commonly used for callees. 11157 */ 11158 .global dvmJitToInterpTraceSelectNoChain 11159 dvmJitToInterpTraceSelectNoChain: 11160 lw gp, STACK_OFFSET_GP(sp) 11161 #if defined(WITH_JIT_TUNING) 11162 JAL(dvmBumpNoChain) 11163 #endif 11164 move a0, rPC 11165 move a1, rSELF 11166 JAL(dvmJitGetTraceAddrThread) # (pc, self) 11167 move a0, v0 11168 sw a0, offThread_inJitCodeCache(rSELF) # set the inJitCodeCache flag 11169 move a1, rPC # arg1 of translation may need this 11170 move ra, zero # in case target is HANDLER_INTERPRET 11171 beqz a0, 2f # 0 means translation does not exist 11172 jr a0 11173 11174 /* 11175 * Return from the translation cache and immediately request 11176 * a translation for the exit target. Commonly used following 11177 * invokes. 11178 */ 11179 .global dvmJitToInterpTraceSelect 11180 dvmJitToInterpTraceSelect: 11181 lw gp, STACK_OFFSET_GP(sp) 11182 lw rPC, (ra) # get our target PC 11183 subu rINST, ra, 8 # save start of chain branch 11184 move a0, rPC 11185 move a1, rSELF 11186 JAL(dvmJitGetTraceAddrThread) # @ (pc, self) 11187 sw v0, offThread_inJitCodeCache(rSELF) # set the inJitCodeCache flag 11188 beqz v0, 2f 11189 move a0, v0 11190 move a1, rINST 11191 JAL(dvmJitChain) # v0 <- dvmJitChain(codeAddr, chainAddr) 11192 move a1, rPC # arg1 of translation may need this 11193 move ra, zero # in case target is HANDLER_INTERPRET 11194 move a0, v0 11195 beqz a0, toInterpreter # didn't chain - resume with interpreter 11196 11197 jr a0 # continue native execution 11198 11199 /* No translation, so request one if profiling isn't disabled */ 11200 2: 11201 lw rIBASE, offThread_curHandlerTable(rSELF) 11202 lw a0, offThread_pJitProfTable(rSELF) 11203 FETCH_INST() 11204 li t0, kJitTSelectRequestHot 11205 movn a2, t0, a0 # ask for trace selection 11206 bnez a0, common_selectTrace 11207 GET_INST_OPCODE(t0) 11208 GOTO_OPCODE(t0) 11209 11210 /* 11211 * Return from the translation cache to the interpreter. 11212 * The return was done with a BLX from thumb mode, and 11213 * the following 32-bit word contains the target rPC value. 11214 * Note that lr (r14) will have its low-order bit set to denote 11215 * its thumb-mode origin. 11216 * 11217 * We'll need to stash our lr origin away, recover the new 11218 * target and then check to see if there is a translation available 11219 * for our new target. If so, we do a translation chain and 11220 * go back to native execution. Otherwise, it's back to the 11221 * interpreter (after treating this entry as a potential 11222 * trace start). 11223 */ 11224 .global dvmJitToInterpNormal 11225 dvmJitToInterpNormal: 11226 lw gp, STACK_OFFSET_GP(sp) 11227 lw rPC, (ra) # get our target PC 11228 subu rINST, ra, 8 # save start of chain branch 11229 #if defined(WITH_JIT_TUNING) 11230 JAL(dvmBumpNormal) 11231 #endif 11232 move a0, rPC 11233 move a1, rSELF 11234 JAL(dvmJitGetTraceAddrThread) # @ (pc, self) 11235 move a0, v0 11236 sw a0, offThread_inJitCodeCache(rSELF) # set the inJitCodeCache flag 11237 beqz a0, toInterpreter # go if not, otherwise do chain 11238 move a1, rINST 11239 JAL(dvmJitChain) # v0 <- dvmJitChain(codeAddr, chainAddr) 11240 move a1, rPC # arg1 of translation may need this 11241 move ra, zero # in case target is HANDLER_INTERPRET 11242 move a0, v0 11243 beqz a0, toInterpreter # didn't chain - resume with interpreter 11244 11245 jr a0 # continue native execution 11246 11247 /* 11248 * Return from the translation cache to the interpreter to do method invocation. 11249 * Check if translation exists for the callee, but don't chain to it. 11250 */ 11251 .global dvmJitToInterpNoChainNoProfile 11252 dvmJitToInterpNoChainNoProfile: 11253 #if defined(WITH_JIT_TUNING) 11254 JAL(dvmBumpNoChain) 11255 #endif 11256 move a0, rPC 11257 move a1, rSELF 11258 JAL(dvmJitGetTraceAddrThread) # (pc, self) 11259 move a0, v0 11260 sw a0, offThread_inJitCodeCache(rSELF) # set the inJitCodeCache flag 11261 move a1, rPC # arg1 of translation may need this 11262 move ra, zero # in case target is HANDLER_INTERPRET 11263 beqz a0, footer235 11264 11265 jr a0 # continue native execution if so 11266 footer235: 11267 EXPORT_PC() 11268 lw rIBASE, offThread_curHandlerTable(rSELF) 11269 FETCH_INST() 11270 GET_INST_OPCODE(t0) # extract opcode from rINST 11271 GOTO_OPCODE(t0) # jump to next instruction 11272 11273 /* 11274 * Return from the translation cache to the interpreter to do method invocation. 11275 * Check if translation exists for the callee, but don't chain to it. 11276 */ 11277 11278 .global dvmJitToInterpNoChain 11279 dvmJitToInterpNoChain: 11280 lw gp, STACK_OFFSET_GP(sp) 11281 #if defined(WITH_JIT_TUNING) 11282 JAL(dvmBumpNoChain) 11283 #endif 11284 move a0, rPC 11285 move a1, rSELF 11286 JAL(dvmJitGetTraceAddrThread) # (pc, self) 11287 move a0, v0 11288 sw a0, offThread_inJitCodeCache(rSELF) # set the inJitCodeCache flag 11289 move a1, rPC # arg1 of translation may need this 11290 move ra, zero # in case target is HANDLER_INTERPRET 11291 beqz a0, 1f 11292 jr a0 # continue native execution if so 11293 1: 11294 #endif /* WITH_SELF_VERIFICATION */ 11295 11296 /* 11297 * No translation, restore interpreter regs and start interpreting. 11298 * rSELF & rFP were preserved in the translated code, and rPC has 11299 * already been restored by the time we get here. We'll need to set 11300 * up rIBASE & rINST, and load the address of the JitTable into r0. 11301 */ 11302 11303 toInterpreter: 11304 EXPORT_PC() 11305 lw rIBASE, offThread_curHandlerTable(rSELF) 11306 FETCH_INST() 11307 lw a0, offThread_pJitProfTable(rSELF) 11308 lw rIBASE, offThread_curHandlerTable(rSELF) 11309 # NOTE: intended fallthrough 11310 11311 /* 11312 * Similar to common_updateProfile, but tests for null pJitProfTable 11313 * r0 holds pJifProfTAble, rINST is loaded, rPC is current and 11314 * rIBASE has been recently refreshed. 11315 */ 11316 11317 common_testUpdateProfile: 11318 11319 beqz a0, 4f 11320 11321 /* 11322 * Common code to update potential trace start counter, and initiate 11323 * a trace-build if appropriate. 11324 * On entry here: 11325 * r0 <= pJitProfTable (verified non-NULL) 11326 * rPC <= Dalvik PC 11327 * rINST <= next instruction 11328 */ 11329 common_updateProfile: 11330 srl a3, rPC, 12 # cheap, but fast hash function 11331 xor a3, a3, rPC 11332 andi a3, a3, JIT_PROF_SIZE-1 # eliminate excess bits 11333 addu t1, a0, a3 11334 lbu a1, (t1) # get counter 11335 GET_INST_OPCODE(t0) 11336 subu a1, a1, 1 # decrement counter 11337 sb a1, (t1) # and store it 11338 beqz a1, 1f 11339 GOTO_OPCODE(t0) # if not threshold, fallthrough otherwise 11340 1: 11341 /* Looks good, reset the counter */ 11342 lw a1, offThread_jitThreshold(rSELF) 11343 sb a1, (t1) 11344 EXPORT_PC() 11345 move a0, rPC 11346 move a1, rSELF 11347 JAL(dvmJitGetTraceAddrThread) # (pc, self) 11348 move a0, v0 11349 sw v0, offThread_inJitCodeCache(rSELF) # set the inJitCodeCache flag 11350 move a1, rPC # arg1 of translation may need this 11351 move ra, zero # in case target is HANDLER_INTERPRET 11352 11353 #if !defined(WITH_SELF_VERIFICATION) 11354 li t0, kJitTSelectRequest # ask for trace selection 11355 movz a2, t0, a0 11356 beqz a0, common_selectTrace 11357 jr a0 # jump to the translation 11358 #else 11359 11360 bne a0, zero, skip_ask_for_trace_selection 11361 li a2, kJitTSelectRequest # ask for trace selection 11362 j common_selectTrace 11363 11364 skip_ask_for_trace_selection: 11365 /* 11366 * At this point, we have a target translation. However, if 11367 * that translation is actually the interpret-only pseudo-translation 11368 * we want to treat it the same as no translation. 11369 */ 11370 move rBIX, a0 # save target 11371 jal dvmCompilerGetInterpretTemplate 11372 # special case? 11373 bne v0, rBIX, jitSVShadowRunStart # set up self verification shadow space 11374 # Need to clear the inJitCodeCache flag 11375 sw zero, offThread_inJitCodeCache(rSELF) # back to the interp land 11376 GET_INST_OPCODE(t0) 11377 GOTO_OPCODE(t0) 11378 /* no return */ 11379 #endif 11380 11381 /* 11382 * On entry: 11383 * r2 is jit state. 11384 */ 11385 11386 common_selectTrace: 11387 lhu a0, offThread_subMode(rSELF) 11388 andi a0, (kSubModeJitTraceBuild | kSubModeJitSV) 11389 bnez a0, 3f # already doing JIT work, continue 11390 sw a2, offThread_jitState(rSELF) 11391 move a0, rSELF 11392 11393 /* 11394 * Call out to validate trace-building request. If successful, 11395 * rIBASE will be swapped to to send us into single-stepping trace 11396 * building mode, so we need to refresh before we continue. 11397 */ 11398 11399 EXPORT_PC() 11400 SAVE_PC_TO_SELF() 11401 SAVE_FP_TO_SELF() 11402 JAL(dvmJitCheckTraceRequest) 11403 3: 11404 FETCH_INST() 11405 lw rIBASE, offThread_curHandlerTable(rSELF) 11406 4: 11407 GET_INST_OPCODE(t0) # extract opcode from rINST 11408 GOTO_OPCODE(t0) 11409 /* no return */ 11410 #endif 11411 11412 #if defined(WITH_SELF_VERIFICATION) 11413 11414 /* 11415 * Save PC and registers to shadow memory for self verification mode 11416 * before jumping to native translation. 11417 * On entry: 11418 * rPC, rFP, rSELF: the values that they should contain 11419 * r10: the address of the target translation. 11420 */ 11421 jitSVShadowRunStart: 11422 move a0, rPC # r0 <- program counter 11423 move a1, rFP # r1 <- frame pointer 11424 move a2, rSELF # r2 <- InterpState pointer 11425 move a3, rBIX # r3 <- target translation 11426 jal dvmSelfVerificationSaveState # save registers to shadow space 11427 lw rFP, offShadowSpace_shadowFP(v0) # rFP <- fp in shadow space 11428 jr rBIX # jump to the translation 11429 11430 /* 11431 * Restore PC, registers, and interpState to original values 11432 * before jumping back to the interpreter. 11433 */ 11434 jitSVShadowRunEnd: 11435 move a1, rFP # pass ending fp 11436 move a3, rSELF # pass self ptr for convenience 11437 jal dvmSelfVerificationRestoreState # restore pc and fp values 11438 LOAD_PC_FP_FROM_SELF() # restore pc, fp 11439 lw a1, offShadowSpace_svState(a0) # get self verification state 11440 beq a1, zero, 1f # check for punt condition 11441 11442 # Setup SV single-stepping 11443 move a0, rSELF 11444 li a1, kSubModeJitSV 11445 JAL(dvmEnableSubMode) # (self, subMode) 11446 li a2, kJitSelfVerification # ask for self verification 11447 sw a2, offThread_jitState(rSELF) 11448 # Intentional fallthrough 11449 11450 1: 11451 # exit to interpreter without check 11452 EXPORT_PC() 11453 lw rIBASE, offThread_curHandlerTable(rSELF) 11454 FETCH_INST() 11455 GET_INST_OPCODE(t0) 11456 GOTO_OPCODE(t0) 11457 #endif 11458 11459 /* 11460 * The equivalent of "goto bail", this calls through the "bail handler". 11461 * It will end this interpreter activation, and return to the caller 11462 * of dvmMterpStdRun. 11463 * 11464 * State registers will be saved to the "thread" area before bailing 11465 * debugging purposes 11466 */ 11467 .ent common_gotoBail 11468 common_gotoBail: 11469 SAVE_PC_FP_TO_SELF() # export state to "thread" 11470 move a0, rSELF # a0 <- self ptr 11471 b dvmMterpStdBail # call(self, changeInterp) 11472 .end common_gotoBail 11473 11474 /* 11475 * The JIT's invoke method needs to remember the callsite class and 11476 * target pair. Save them here so that they are available to 11477 * dvmCheckJit following the interpretation of this invoke. 11478 */ 11479 #if defined(WITH_JIT) 11480 save_callsiteinfo: 11481 beqz rOBJ, 1f 11482 lw rOBJ, offObject_clazz(rOBJ) 11483 1: 11484 sw a0, offThread_methodToCall(rSELF) 11485 sw rOBJ, offThread_callsiteClass(rSELF) 11486 jr ra 11487 #endif 11488 11489 /* 11490 * Common code for jumbo method invocation. 11491 * NOTE: this adjusts rPC to account for the difference in instruction width. 11492 * As a result, the savedPc in the stack frame will not be wholly accurate. So 11493 * long as that is only used for source file line number calculations, we're 11494 * okay. 11495 */ 11496 common_invokeMethodJumboNoThis: 11497 #if defined(WITH_JIT) 11498 /* On entry: a0 is "Method* methodToCall */ 11499 li rOBJ, 0 # clear "this" 11500 #endif 11501 common_invokeMethodJumbo: 11502 /* On entry: a0 is "Method* methodToCall, rOBJ is "this" */ 11503 .LinvokeNewJumbo: 11504 #if defined(WITH_JIT) 11505 lhu a1, offThread_subMode(rSELF) 11506 andi a1, kSubModeJitTraceBuild 11507 beqz a1, 1f 11508 JAL(save_callsiteinfo) 11509 #endif 11510 /* prepare to copy args to "outs" area of current frame */ 11511 1: 11512 add rPC, rPC, 4 # adjust pc to make return consistent 11513 FETCH(a2, 1) 11514 SAVEAREA_FROM_FP(rBIX, rFP) # rBIX <- stack save area 11515 beqz a2, .LinvokeArgsDone # if no args, skip the rest 11516 FETCH(a1, 2) # a1 <- CCCC 11517 b .LinvokeRangeArgs # handle args like invoke range 11518 11519 11520 /* 11521 * Common code for method invocation with range. 11522 * 11523 * On entry: 11524 * a0 is "Method* methodToCall", the method we're trying to call 11525 */ 11526 common_invokeMethodRange: 11527 .LinvokeNewRange: 11528 #if defined(WITH_JIT) 11529 lhu a1, offThread_subMode(rSELF) 11530 andi a1, kSubModeJitTraceBuild 11531 beqz a1, 1f 11532 JAL(save_callsiteinfo) 11533 #endif 11534 # prepare to copy args to "outs" area of current frame 11535 1: 11536 GET_OPA(a2) 11537 SAVEAREA_FROM_FP(rBIX, rFP) # rBIX <- stack save area 11538 beqz a2, .LinvokeArgsDone 11539 FETCH(a1, 2) # a1 <- CCCC 11540 .LinvokeRangeArgs: 11541 # a0=methodToCall, a1=CCCC, a2=count, rBIX=outs 11542 # (very few methods have > 10 args; could unroll for common cases) 11543 EAS2(a3, rFP, a1) 11544 sll t0, a2, 2 11545 subu rBIX, rBIX, t0 11546 11547 1: 11548 lw a1, 0(a3) 11549 addu a3, a3, 4 11550 subu a2, a2, 1 11551 sw a1, 0(rBIX) 11552 addu rBIX, 4 11553 bnez a2, 1b 11554 b .LinvokeArgsDone 11555 11556 /* 11557 * Common code for method invocation without range. 11558 * 11559 * On entry: 11560 * a0 is "Method* methodToCall", "rOBJ is this" 11561 */ 11562 common_invokeMethodNoRange: 11563 .LinvokeNewNoRange: 11564 #if defined(WITH_JIT) 11565 lhu a1, offThread_subMode(rSELF) 11566 andi a1, kSubModeJitTraceBuild 11567 beqz a1, 1f 11568 JAL(save_callsiteinfo) 11569 #endif 11570 11571 # prepare to copy args to "outs" area of current frame 11572 1: 11573 GET_OPB(a2) 11574 SAVEAREA_FROM_FP(rBIX, rFP) 11575 beqz a2, .LinvokeArgsDone 11576 FETCH(a1, 2) 11577 11578 # a0=methodToCall, a1=GFED, a2=count, 11579 .LinvokeNonRange: 11580 beq a2, 0, 0f 11581 beq a2, 1, 1f 11582 beq a2, 2, 2f 11583 beq a2, 3, 3f 11584 beq a2, 4, 4f 11585 beq a2, 5, 5f 11586 11587 5: 11588 and t0, rINST, 0x0f00 11589 ESRN(t2, rFP, t0, 6) 11590 lw a3, (t2) 11591 subu rBIX, 4 11592 sw a3, 0(rBIX) 11593 11594 4: 11595 and t0, a1, 0xf000 11596 ESRN(t2, rFP, t0, 10) 11597 lw a3, (t2) 11598 subu rBIX, 4 11599 sw a3, 0(rBIX) 11600 11601 3: 11602 and t0, a1, 0x0f00 11603 ESRN(t2, rFP, t0, 6) 11604 lw a3, (t2) 11605 subu rBIX, 4 11606 sw a3, 0(rBIX) 11607 11608 2: 11609 and t0, a1, 0x00f0 11610 ESRN(t2, rFP, t0, 2) 11611 lw a3, (t2) 11612 subu rBIX, 4 11613 sw a3, 0(rBIX) 11614 11615 1: 11616 and t0, a1, 0x000f 11617 EASN(t2, rFP, t0, 2) 11618 lw a3, (t2) 11619 subu rBIX, 4 11620 sw a3, 0(rBIX) 11621 11622 0: 11623 #fall through .LinvokeArgsDone 11624 11625 11626 .LinvokeArgsDone: # a0=methodToCall 11627 lhu rOBJ, offMethod_registersSize(a0) 11628 lhu a3, offMethod_outsSize(a0) 11629 lw a2, offMethod_insns(a0) 11630 lw rINST, offMethod_clazz(a0) 11631 # find space for the new stack frame, check for overflow 11632 SAVEAREA_FROM_FP(a1, rFP) # a1 <- stack save area 11633 sll t0, rOBJ, 2 # a1 <- newFp (old savearea - regsSize) 11634 subu a1, a1, t0 11635 SAVEAREA_FROM_FP(rBIX, a1) 11636 lw rOBJ, offThread_interpStackEnd(rSELF) # t3 <- interpStackEnd 11637 sll t2, a3, 2 11638 subu t0, rBIX, t2 11639 lhu ra, offThread_subMode(rSELF) 11640 lw a3, offMethod_accessFlags(a0) # a3 <- methodToCall->accessFlags 11641 bltu t0, rOBJ, .LstackOverflow # yes, this frame will overflow stack 11642 11643 11644 # set up newSaveArea 11645 #ifdef EASY_GDB 11646 SAVEAREA_FROM_FP(t0, rFP) 11647 sw t0, offStackSaveArea_prevSave(rBIX) 11648 #endif 11649 sw rFP, (offStackSaveArea_prevFrame)(rBIX) 11650 sw rPC, (offStackSaveArea_savedPc)(rBIX) 11651 #if defined(WITH_JIT) 11652 sw zero, (offStackSaveArea_returnAddr)(rBIX) 11653 #endif 11654 sw a0, (offStackSaveArea_method)(rBIX) 11655 # Profiling? 11656 bnez ra, 2f 11657 1: 11658 and t2, a3, ACC_NATIVE 11659 bnez t2, .LinvokeNative 11660 lhu rOBJ, (a2) # rOBJ -< load Inst from New PC 11661 lw a3, offClassObject_pDvmDex(rINST) 11662 move rPC, a2 # Publish new rPC 11663 # Update state values for the new method 11664 # a0=methodToCall, a1=newFp, a3=newMethodClass, rOBJ=newINST 11665 sw a0, offThread_method(rSELF) 11666 sw a3, offThread_methodClassDex(rSELF) 11667 li a2, 1 11668 sw a2, offThread_debugIsMethodEntry(rSELF) 11669 11670 #if defined(WITH_JIT) 11671 lw a0, offThread_pJitProfTable(rSELF) 11672 move rFP, a1 # fp = newFp 11673 GET_PREFETCHED_OPCODE(t0, rOBJ) # extract prefetched opcode from rOBJ 11674 move rINST, rOBJ # publish new rINST 11675 sw a1, offThread_curFrame(rSELF) 11676 bnez a0, common_updateProfile 11677 GOTO_OPCODE(t0) 11678 #else 11679 move rFP, a1 11680 GET_PREFETCHED_OPCODE(t0, rOBJ) 11681 move rINST, rOBJ 11682 sw a1, offThread_curFrame(rSELF) 11683 GOTO_OPCODE(t0) 11684 #endif 11685 11686 2: 11687 # Profiling - record method entry. a0: methodToCall 11688 STACK_STORE(a0, 0) 11689 STACK_STORE(a1, 4) 11690 STACK_STORE(a2, 8) 11691 STACK_STORE(a3, 12) 11692 sw rPC, offThread_pc(rSELF) # update interpSave.pc 11693 move a1, a0 11694 move a0, rSELF 11695 JAL(dvmReportInvoke) 11696 STACK_LOAD(a3, 12) # restore a0-a3 11697 STACK_LOAD(a2, 8) 11698 STACK_LOAD(a1, 4) 11699 STACK_LOAD(a0, 0) 11700 b 1b 11701 .LinvokeNative: 11702 # Prep for the native call 11703 # a0=methodToCall, a1=newFp, rBIX=newSaveArea 11704 lhu ra, offThread_subMode(rSELF) 11705 lw t3, offThread_jniLocal_topCookie(rSELF) 11706 sw a1, offThread_curFrame(rSELF) 11707 sw t3, offStackSaveArea_localRefCookie(rBIX) # newFp->localRefCookie=top 11708 move a2, a0 11709 move a0, a1 11710 addu a1, rSELF, offThread_retval 11711 move a3, rSELF 11712 #ifdef ASSIST_DEBUGGER 11713 /* insert fake function header to help gdb find the stack frame */ 11714 b .Lskip 11715 .ent dalvik_mterp 11716 dalvik_mterp: 11717 STACK_STORE_FULL() 11718 .Lskip: 11719 #endif 11720 bnez ra, 11f # Any special SubModes active? 11721 lw t9, offMethod_nativeFunc(a2) 11722 jalr t9 11723 lw gp, STACK_OFFSET_GP(sp) 11724 7: 11725 # native return; rBIX=newSaveArea 11726 # equivalent to dvmPopJniLocals 11727 lw a0, offStackSaveArea_localRefCookie(rBIX) 11728 lw a1, offThread_exception(rSELF) 11729 sw rFP, offThread_curFrame(rSELF) 11730 sw a0, offThread_jniLocal_topCookie(rSELF) # new top <- old top 11731 bnez a1, common_exceptionThrown 11732 11733 FETCH_ADVANCE_INST(3) 11734 GET_INST_OPCODE(t0) 11735 GOTO_OPCODE(t0) 11736 11: 11737 # a0=newFp, a1=&retval, a2=methodToCall, a3=self, ra=subModes 11738 SCRATCH_STORE(a0, 0) 11739 SCRATCH_STORE(a1, 4) 11740 SCRATCH_STORE(a2, 8) 11741 SCRATCH_STORE(a3, 12) 11742 move a0, a2 # a0 <- methodToCall 11743 move a1, rSELF 11744 move a2, rFP 11745 JAL(dvmReportPreNativeInvoke) # (methodToCall, self, fp) 11746 SCRATCH_LOAD(a3, 12) # restore a0-a3 11747 SCRATCH_LOAD(a2, 8) 11748 SCRATCH_LOAD(a1, 4) 11749 SCRATCH_LOAD(a0, 0) 11750 11751 # Call the native method 11752 lw t9, offMethod_nativeFunc(a2) # t9<-methodToCall->nativeFunc 11753 jalr t9 11754 lw gp, STACK_OFFSET_GP(sp) 11755 11756 # Restore the pre-call arguments 11757 SCRATCH_LOAD(a3, 12) # restore a0-a3 11758 SCRATCH_LOAD(a2, 8) 11759 SCRATCH_LOAD(a1, 4) 11760 SCRATCH_LOAD(a0, 0) 11761 11762 # Finish up any post-invoke subMode requirements 11763 move a0, a2 11764 move a1, rSELF 11765 move a2, rFP 11766 JAL(dvmReportPostNativeInvoke) # (methodToCall, self, fp) 11767 b 7b 11768 11769 11770 .LstackOverflow: # a0=methodToCall 11771 move a1, a0 # a1 <- methodToCall 11772 move a0, rSELF # a0 <- self 11773 JAL(dvmHandleStackOverflow) # dvmHandleStackOverflow(self, methodToCall) 11774 b common_exceptionThrown 11775 #ifdef ASSIST_DEBUGGER 11776 .end dalvik_mterp 11777 #endif 11778 11779 /* 11780 * Common code for method invocation, calling through "glue code". 11781 * 11782 * TODO: now that we have range and non-range invoke handlers, this 11783 * needs to be split into two. Maybe just create entry points 11784 * that set r9 and jump here? 11785 * 11786 * On entry: 11787 * r0 is "Method* methodToCall", the method we're trying to call 11788 * r9 is "bool methodCallRange", indicating if this is a /range variant 11789 */ 11790 11791 /* 11792 * Common code for handling a return instruction. 11793 * 11794 * This does not return. 11795 */ 11796 common_returnFromMethod: 11797 .LreturnNew: 11798 lhu t0, offThread_subMode(rSELF) 11799 SAVEAREA_FROM_FP(a0, rFP) 11800 lw rOBJ, offStackSaveArea_savedPc(a0) # rOBJ = saveArea->savedPc 11801 bnez t0, 19f 11802 14: 11803 lw rFP, offStackSaveArea_prevFrame(a0) # fp = saveArea->prevFrame 11804 lw a2, (offStackSaveArea_method - sizeofStackSaveArea)(rFP) 11805 # a2<- method we're returning to 11806 # is this a break frame? 11807 beqz a2, common_gotoBail # break frame, bail out completely 11808 11809 lw rBIX, offMethod_clazz(a2) # rBIX<- method->clazz 11810 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh rIBASE 11811 PREFETCH_ADVANCE_INST(rINST, rOBJ, 3) # advance rOBJ, update new rINST 11812 sw a2, offThread_method(rSELF) # self->method = newSave->method 11813 lw a1, offClassObject_pDvmDex(rBIX) # r1<- method->clazz->pDvmDex 11814 sw rFP, offThread_curFrame(rSELF) # curFrame = fp 11815 #if defined(WITH_JIT) 11816 lw rBIX, offStackSaveArea_returnAddr(a0) 11817 move rPC, rOBJ # publish new rPC 11818 sw a1, offThread_methodClassDex(rSELF) 11819 sw rBIX, offThread_inJitCodeCache(rSELF) # may return to JIT'ed land 11820 beqz rBIX, 15f # caller is compiled code 11821 move t9, rBIX 11822 jalr t9 11823 lw gp, STACK_OFFSET_GP(sp) 11824 15: 11825 GET_INST_OPCODE(t0) # extract opcode from rINST 11826 GOTO_OPCODE(t0) # jump to next instruction 11827 #else 11828 GET_INST_OPCODE(t0) # extract opcode from rINST 11829 move rPC, rOBJ # publish new rPC 11830 sw a1, offThread_methodClassDex(rSELF) 11831 GOTO_OPCODE(t0) 11832 #endif 11833 11834 19: 11835 # Handle special actions 11836 # On entry, a0: StackSaveArea 11837 lw a1, offStackSaveArea_prevFrame(a0) # a1<- prevFP 11838 sw rPC, offThread_pc(rSELF) # update interpSave.pc 11839 sw a1, offThread_curFrame(rSELF) # update interpSave.curFrame 11840 move a0, rSELF 11841 JAL(dvmReportReturn) 11842 SAVEAREA_FROM_FP(a0, rFP) # restore StackSaveArea 11843 b 14b 11844 11845 .if 0 11846 /* 11847 * Return handling, calls through "glue code". 11848 */ 11849 .LreturnOld: 11850 SAVE_PC_FP_TO_SELF() # export state 11851 move a0, rSELF # arg to function 11852 JAL(dvmMterp_returnFromMethod) 11853 b common_resumeAfterGlueCall 11854 .endif 11855 11856 /* 11857 * Somebody has thrown an exception. Handle it. 11858 * 11859 * If the exception processing code returns to us (instead of falling 11860 * out of the interpreter), continue with whatever the next instruction 11861 * now happens to be. 11862 * 11863 * This does not return. 11864 */ 11865 .global dvmMterpCommonExceptionThrown 11866 dvmMterpCommonExceptionThrown: 11867 common_exceptionThrown: 11868 .LexceptionNew: 11869 11870 EXPORT_PC() 11871 move a0, rSELF 11872 JAL(dvmCheckSuspendPending) 11873 lw rOBJ, offThread_exception(rSELF) 11874 move a1, rSELF 11875 move a0, rOBJ 11876 JAL(dvmAddTrackedAlloc) 11877 lhu a2, offThread_subMode(rSELF) 11878 sw zero, offThread_exception(rSELF) 11879 11880 # Special subMode? 11881 bnez a2, 7f # any special subMode handling needed? 11882 8: 11883 /* set up args and a local for "&fp" */ 11884 sw rFP, 20(sp) # store rFP => tmp 11885 addu t0, sp, 20 # compute &tmp 11886 sw t0, STACK_OFFSET_ARG04(sp) # save it in arg4 as per ABI 11887 li a3, 0 # a3 <- false 11888 lw a1, offThread_method(rSELF) 11889 move a0, rSELF 11890 lw a1, offMethod_insns(a1) 11891 lhu ra, offThread_subMode(rSELF) 11892 move a2, rOBJ 11893 subu a1, rPC, a1 11894 sra a1, a1, 1 11895 11896 /* call, r0 gets catchRelPc (a code-unit offset) */ 11897 JAL(dvmFindCatchBlock) # call(self, relPc, exc, scan?, &fp) 11898 lw rFP, 20(sp) # retrieve the updated rFP 11899 11900 /* update frame pointer and check result from dvmFindCatchBlock */ 11901 move a0, v0 11902 bltz v0, .LnotCaughtLocally 11903 11904 /* fix earlier stack overflow if necessary; Preserve a0 */ 11905 lbu a1, offThread_stackOverflowed(rSELF) 11906 beqz a1, 1f 11907 move rBIX, a0 11908 move a0, rSELF 11909 move a1, rOBJ 11910 JAL(dvmCleanupStackOverflow) 11911 move a0, rBIX 11912 11913 1: 11914 11915 /* adjust locals to match self->interpSave.curFrame and updated PC */ 11916 SAVEAREA_FROM_FP(a1, rFP) # a1<- new save area 11917 lw a1, offStackSaveArea_method(a1) 11918 sw a1, offThread_method(rSELF) 11919 lw a2, offMethod_clazz(a1) 11920 lw a3, offMethod_insns(a1) 11921 lw a2, offClassObject_pDvmDex(a2) 11922 EAS1(rPC, a3, a0) 11923 sw a2, offThread_methodClassDex(rSELF) 11924 11925 /* release the tracked alloc on the exception */ 11926 move a0, rOBJ 11927 move a1, rSELF 11928 JAL(dvmReleaseTrackedAlloc) 11929 11930 /* restore the exception if the handler wants it */ 11931 lw rIBASE, offThread_curHandlerTable(rSELF) 11932 FETCH_INST() 11933 GET_INST_OPCODE(t0) 11934 bne t0, OP_MOVE_EXCEPTION, 2f 11935 sw rOBJ, offThread_exception(rSELF) 11936 2: 11937 GOTO_OPCODE(t0) 11938 11939 # Manage debugger bookkeeping 11940 7: 11941 sw rPC, offThread_pc(rSELF) 11942 sw rFP, offThread_curFrame(rSELF) 11943 move a0, rSELF 11944 move a1, rOBJ 11945 JAL(dvmReportExceptionThrow) 11946 b 8b 11947 11948 .LnotCaughtLocally: # rOBJ = exception 11949 /* fix stack overflow if necessary */ 11950 lbu a1, offThread_stackOverflowed(rSELF) 11951 beqz a1, 3f 11952 move a0, rSELF 11953 move a1, rOBJ 11954 JAL(dvmCleanupStackOverflow) # dvmCleanupStackOverflow(self, exception) 11955 11956 3: 11957 # may want to show "not caught locally" debug messages here 11958 #if DVM_SHOW_EXCEPTION >= 2 11959 /* call __android_log_print(prio, tag, format, ...) */ 11960 /* "Exception %s from %s:%d not caught locally" */ 11961 lw a0, offThread_method(rSELF) 11962 lw a1, offMethod_insns(a0) 11963 subu a1, rPC, a1 11964 sra a1, a1, 1 11965 JAL(dvmLineNumFromPC) 11966 sw v0, 20(sp) 11967 # dvmGetMethodSourceFile(method) 11968 lw a0, offThread_method(rSELF) 11969 JAL(dvmGetMethodSourceFile) 11970 sw v0, 16(sp) 11971 # exception->clazz->descriptor 11972 lw a3, offObject_clazz(rOBJ) 11973 lw a3, offClassObject_descriptor(a3) 11974 la a2, .LstrExceptionNotCaughtLocally 11975 la a1, .LstrLogTag 11976 li a0, 3 11977 JAL(__android_log_print) 11978 #endif 11979 sw rOBJ, offThread_exception(rSELF) 11980 move a0, rOBJ 11981 move a1, rSELF 11982 JAL(dvmReleaseTrackedAlloc) 11983 b common_gotoBail 11984 11985 /* 11986 * Exception handling, calls through "glue code". 11987 */ 11988 .if 0 11989 .LexceptionOld: 11990 SAVE_PC_TO_SELF() # export state 11991 SAVE_FP_TO_SELF() 11992 move a0, rSELF # arg to function 11993 JAL(dvmMterp_exceptionThrown) 11994 b common_resumeAfterGlueCall 11995 .endif 11996 11997 #if defined(WITH_JIT) 11998 /* 11999 * If the JIT is actively building a trace we need to make sure 12000 * that the field is fully resolved before including the current 12001 * instruction. 12002 * 12003 * On entry: 12004 * rBIX: &dvmDex->pResFields[field] 12005 * a0: field pointer (must preserve) 12006 */ 12007 common_verifyField: 12008 lhu a3, offThread_subMode(rSELF) 12009 andi a3, kSubModeJitTraceBuild 12010 bnez a3, 1f # Not building trace, continue 12011 jr ra 12012 1: 12013 lw a1, (rBIX) 12014 beqz a1, 2f # resolution complete ? 12015 jr ra 12016 2: 12017 SCRATCH_STORE(a0, 0) 12018 SCRATCH_STORE(a1, 4) 12019 SCRATCH_STORE(a2, 8) 12020 SCRATCH_STORE(a3, 12) 12021 SCRATCH_STORE(ra, 16) 12022 move a0, rSELF 12023 move a1, rPC 12024 JAL(dvmJitEndTraceSelect) #(self,pc) end trace before this inst) 12025 SCRATCH_LOAD(a0, 0) 12026 SCRATCH_LOAD(a1, 4) 12027 SCRATCH_LOAD(a2, 8) 12028 SCRATCH_LOAD(a3, 12) 12029 SCRATCH_LOAD(ra, 16) 12030 jr ra # return 12031 #endif 12032 12033 /* 12034 * After returning from a "glued" function, pull out the updated 12035 * values and start executing at the next instruction. 12036 */ 12037 common_resumeAfterGlueCall: 12038 LOAD_PC_FP_FROM_SELF() # pull rPC and rFP out of thread 12039 lw rIBASE, offThread_curHandlerTable(rSELF) # refresh 12040 FETCH_INST() # load rINST from rPC 12041 GET_INST_OPCODE(t0) # extract opcode from rINST 12042 GOTO_OPCODE(t0) # jump to next instruction 12043 12044 /* 12045 * Invalid array index. Note that our calling convention is strange; we use a1 12046 * and a3 because those just happen to be the registers all our callers are 12047 * using. We move a3 before calling the C function, but a1 happens to match. 12048 * a1: index 12049 * a3: size 12050 */ 12051 common_errArrayIndex: 12052 EXPORT_PC() 12053 move a0, a3 12054 JAL(dvmThrowArrayIndexOutOfBoundsException) 12055 b common_exceptionThrown 12056 12057 /* 12058 * Integer divide or mod by zero. 12059 */ 12060 common_errDivideByZero: 12061 EXPORT_PC() 12062 la a0, .LstrDivideByZero 12063 JAL(dvmThrowArithmeticException) 12064 b common_exceptionThrown 12065 12066 /* 12067 * Attempt to allocate an array with a negative size. 12068 * On entry: length in a1 12069 */ 12070 common_errNegativeArraySize: 12071 EXPORT_PC() 12072 move a0, a1 # arg0 <- len 12073 JAL(dvmThrowNegativeArraySizeException) # (len) 12074 b common_exceptionThrown 12075 12076 /* 12077 * Invocation of a non-existent method. 12078 * On entry: method name in a1 12079 */ 12080 common_errNoSuchMethod: 12081 EXPORT_PC() 12082 move a0, a1 12083 JAL(dvmThrowNoSuchMethodError) 12084 b common_exceptionThrown 12085 12086 /* 12087 * We encountered a null object when we weren't expecting one. We 12088 * export the PC, throw a NullPointerException, and goto the exception 12089 * processing code. 12090 */ 12091 common_errNullObject: 12092 EXPORT_PC() 12093 li a0, 0 12094 JAL(dvmThrowNullPointerException) 12095 b common_exceptionThrown 12096 12097 /* 12098 * For debugging, cause an immediate fault. The source address will be in ra. Use a jal to jump here. 12099 */ 12100 common_abort: 12101 lw zero,-4(zero) # generate SIGSEGV 12102 12103 /* 12104 * Spit out a "we were here", preserving all registers. 12105 */ 12106 .macro SQUEAK num 12107 common_squeak\num: 12108 STACK_STORE_RA(); 12109 la a0, .LstrSqueak 12110 LOAD_IMM(a1, \num); 12111 JAL(printf); 12112 STACK_LOAD_RA(); 12113 RETURN; 12114 .endm 12115 12116 SQUEAK 0 12117 SQUEAK 1 12118 SQUEAK 2 12119 SQUEAK 3 12120 SQUEAK 4 12121 SQUEAK 5 12122 12123 /* 12124 * Spit out the number in a0, preserving registers. 12125 */ 12126 common_printNum: 12127 STACK_STORE_RA() 12128 MOVE_REG(a1, a0) 12129 la a0, .LstrSqueak 12130 JAL(printf) 12131 STACK_LOAD_RA() 12132 RETURN 12133 12134 /* 12135 * Print a newline, preserving registers. 12136 */ 12137 common_printNewline: 12138 STACK_STORE_RA() 12139 la a0, .LstrNewline 12140 JAL(printf) 12141 STACK_LOAD_RA() 12142 RETURN 12143 12144 /* 12145 * Print the 32-bit quantity in a0 as a hex value, preserving registers. 12146 */ 12147 common_printHex: 12148 STACK_STORE_RA() 12149 MOVE_REG(a1, a0) 12150 la a0, .LstrPrintHex 12151 JAL(printf) 12152 STACK_LOAD_RA() 12153 RETURN; 12154 12155 /* 12156 * Print the 64-bit quantity in a0-a1, preserving registers. 12157 */ 12158 common_printLong: 12159 STACK_STORE_RA() 12160 MOVE_REG(a3, a1) 12161 MOVE_REG(a2, a0) 12162 la a0, .LstrPrintLong 12163 JAL(printf) 12164 STACK_LOAD_RA() 12165 RETURN; 12166 12167 /* 12168 * Print full method info. Pass the Method* in a0. Preserves regs. 12169 */ 12170 common_printMethod: 12171 STACK_STORE_RA() 12172 JAL(dvmMterpPrintMethod) 12173 STACK_LOAD_RA() 12174 RETURN 12175 12176 /* 12177 * Call a C helper function that dumps regs and possibly some 12178 * additional info. Requires the C function to be compiled in. 12179 */ 12180 .if 0 12181 common_dumpRegs: 12182 STACK_STORE_RA() 12183 JAL(dvmMterpDumpMipsRegs) 12184 STACK_LOAD_RA() 12185 RETURN 12186 .endif 12187 12188 /* 12189 * Zero-terminated ASCII string data. 12190 */ 12191 .data 12192 12193 .LstrBadEntryPoint: 12194 .asciiz "Bad entry point %d\n" 12195 .LstrDivideByZero: 12196 .asciiz "divide by zero" 12197 .LstrFilledNewArrayNotImpl: 12198 .asciiz "filled-new-array only implemented for 'int'" 12199 .LstrLogTag: 12200 .asciiz "mterp" 12201 .LstrExceptionNotCaughtLocally: 12202 .asciiz "Exception %s from %s:%d not caught locally\n" 12203 12204 .LstrNewline: 12205 .asciiz "\n" 12206 .LstrSqueak: 12207 .asciiz "<%d>" 12208 .LstrPrintHex: 12209 .asciiz "<0x%x>" 12210 .LstrPrintLong: 12211 .asciiz "<%lld>" 12212 12213 12214 .global dvmAsmAltInstructionStart 12215 .type dvmAsmAltInstructionStart, %function 12216 .text 12217 12218 dvmAsmAltInstructionStart = .L_ALT_OP_NOP 12219 /* ------------------------------ */ 12220 .balign 128 12221 .L_ALT_OP_NOP: /* 0x00 */ 12222 /* File: mips/alt_stub.S */ 12223 /* 12224 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12225 * any interesting requests and then jump to the real instruction 12226 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12227 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12228 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12229 * bail to the real handler if breakFlags==0. 12230 */ 12231 lbu a3, offThread_breakFlags(rSELF) 12232 la rBIX, dvmAsmInstructionStart + (0 * 128) 12233 lw rIBASE, offThread_curHandlerTable(rSELF) 12234 bnez a3, 1f 12235 jr rBIX # nothing to do - jump to real handler 12236 1: 12237 EXPORT_PC() 12238 move a0, rPC # arg0 12239 move a1, rFP # arg1 12240 move a2, rSELF # arg2 12241 JAL(dvmCheckBefore) 12242 jr rBIX 12243 12244 /* ------------------------------ */ 12245 .balign 128 12246 .L_ALT_OP_MOVE: /* 0x01 */ 12247 /* File: mips/alt_stub.S */ 12248 /* 12249 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12250 * any interesting requests and then jump to the real instruction 12251 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12252 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12253 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12254 * bail to the real handler if breakFlags==0. 12255 */ 12256 lbu a3, offThread_breakFlags(rSELF) 12257 la rBIX, dvmAsmInstructionStart + (1 * 128) 12258 lw rIBASE, offThread_curHandlerTable(rSELF) 12259 bnez a3, 1f 12260 jr rBIX # nothing to do - jump to real handler 12261 1: 12262 EXPORT_PC() 12263 move a0, rPC # arg0 12264 move a1, rFP # arg1 12265 move a2, rSELF # arg2 12266 JAL(dvmCheckBefore) 12267 jr rBIX 12268 12269 /* ------------------------------ */ 12270 .balign 128 12271 .L_ALT_OP_MOVE_FROM16: /* 0x02 */ 12272 /* File: mips/alt_stub.S */ 12273 /* 12274 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12275 * any interesting requests and then jump to the real instruction 12276 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12277 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12278 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12279 * bail to the real handler if breakFlags==0. 12280 */ 12281 lbu a3, offThread_breakFlags(rSELF) 12282 la rBIX, dvmAsmInstructionStart + (2 * 128) 12283 lw rIBASE, offThread_curHandlerTable(rSELF) 12284 bnez a3, 1f 12285 jr rBIX # nothing to do - jump to real handler 12286 1: 12287 EXPORT_PC() 12288 move a0, rPC # arg0 12289 move a1, rFP # arg1 12290 move a2, rSELF # arg2 12291 JAL(dvmCheckBefore) 12292 jr rBIX 12293 12294 /* ------------------------------ */ 12295 .balign 128 12296 .L_ALT_OP_MOVE_16: /* 0x03 */ 12297 /* File: mips/alt_stub.S */ 12298 /* 12299 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12300 * any interesting requests and then jump to the real instruction 12301 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12302 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12303 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12304 * bail to the real handler if breakFlags==0. 12305 */ 12306 lbu a3, offThread_breakFlags(rSELF) 12307 la rBIX, dvmAsmInstructionStart + (3 * 128) 12308 lw rIBASE, offThread_curHandlerTable(rSELF) 12309 bnez a3, 1f 12310 jr rBIX # nothing to do - jump to real handler 12311 1: 12312 EXPORT_PC() 12313 move a0, rPC # arg0 12314 move a1, rFP # arg1 12315 move a2, rSELF # arg2 12316 JAL(dvmCheckBefore) 12317 jr rBIX 12318 12319 /* ------------------------------ */ 12320 .balign 128 12321 .L_ALT_OP_MOVE_WIDE: /* 0x04 */ 12322 /* File: mips/alt_stub.S */ 12323 /* 12324 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12325 * any interesting requests and then jump to the real instruction 12326 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12327 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12328 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12329 * bail to the real handler if breakFlags==0. 12330 */ 12331 lbu a3, offThread_breakFlags(rSELF) 12332 la rBIX, dvmAsmInstructionStart + (4 * 128) 12333 lw rIBASE, offThread_curHandlerTable(rSELF) 12334 bnez a3, 1f 12335 jr rBIX # nothing to do - jump to real handler 12336 1: 12337 EXPORT_PC() 12338 move a0, rPC # arg0 12339 move a1, rFP # arg1 12340 move a2, rSELF # arg2 12341 JAL(dvmCheckBefore) 12342 jr rBIX 12343 12344 /* ------------------------------ */ 12345 .balign 128 12346 .L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */ 12347 /* File: mips/alt_stub.S */ 12348 /* 12349 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12350 * any interesting requests and then jump to the real instruction 12351 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12352 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12353 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12354 * bail to the real handler if breakFlags==0. 12355 */ 12356 lbu a3, offThread_breakFlags(rSELF) 12357 la rBIX, dvmAsmInstructionStart + (5 * 128) 12358 lw rIBASE, offThread_curHandlerTable(rSELF) 12359 bnez a3, 1f 12360 jr rBIX # nothing to do - jump to real handler 12361 1: 12362 EXPORT_PC() 12363 move a0, rPC # arg0 12364 move a1, rFP # arg1 12365 move a2, rSELF # arg2 12366 JAL(dvmCheckBefore) 12367 jr rBIX 12368 12369 /* ------------------------------ */ 12370 .balign 128 12371 .L_ALT_OP_MOVE_WIDE_16: /* 0x06 */ 12372 /* File: mips/alt_stub.S */ 12373 /* 12374 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12375 * any interesting requests and then jump to the real instruction 12376 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12377 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12378 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12379 * bail to the real handler if breakFlags==0. 12380 */ 12381 lbu a3, offThread_breakFlags(rSELF) 12382 la rBIX, dvmAsmInstructionStart + (6 * 128) 12383 lw rIBASE, offThread_curHandlerTable(rSELF) 12384 bnez a3, 1f 12385 jr rBIX # nothing to do - jump to real handler 12386 1: 12387 EXPORT_PC() 12388 move a0, rPC # arg0 12389 move a1, rFP # arg1 12390 move a2, rSELF # arg2 12391 JAL(dvmCheckBefore) 12392 jr rBIX 12393 12394 /* ------------------------------ */ 12395 .balign 128 12396 .L_ALT_OP_MOVE_OBJECT: /* 0x07 */ 12397 /* File: mips/alt_stub.S */ 12398 /* 12399 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12400 * any interesting requests and then jump to the real instruction 12401 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12402 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12403 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12404 * bail to the real handler if breakFlags==0. 12405 */ 12406 lbu a3, offThread_breakFlags(rSELF) 12407 la rBIX, dvmAsmInstructionStart + (7 * 128) 12408 lw rIBASE, offThread_curHandlerTable(rSELF) 12409 bnez a3, 1f 12410 jr rBIX # nothing to do - jump to real handler 12411 1: 12412 EXPORT_PC() 12413 move a0, rPC # arg0 12414 move a1, rFP # arg1 12415 move a2, rSELF # arg2 12416 JAL(dvmCheckBefore) 12417 jr rBIX 12418 12419 /* ------------------------------ */ 12420 .balign 128 12421 .L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 12422 /* File: mips/alt_stub.S */ 12423 /* 12424 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12425 * any interesting requests and then jump to the real instruction 12426 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12427 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12428 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12429 * bail to the real handler if breakFlags==0. 12430 */ 12431 lbu a3, offThread_breakFlags(rSELF) 12432 la rBIX, dvmAsmInstructionStart + (8 * 128) 12433 lw rIBASE, offThread_curHandlerTable(rSELF) 12434 bnez a3, 1f 12435 jr rBIX # nothing to do - jump to real handler 12436 1: 12437 EXPORT_PC() 12438 move a0, rPC # arg0 12439 move a1, rFP # arg1 12440 move a2, rSELF # arg2 12441 JAL(dvmCheckBefore) 12442 jr rBIX 12443 12444 /* ------------------------------ */ 12445 .balign 128 12446 .L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */ 12447 /* File: mips/alt_stub.S */ 12448 /* 12449 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12450 * any interesting requests and then jump to the real instruction 12451 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12452 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12453 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12454 * bail to the real handler if breakFlags==0. 12455 */ 12456 lbu a3, offThread_breakFlags(rSELF) 12457 la rBIX, dvmAsmInstructionStart + (9 * 128) 12458 lw rIBASE, offThread_curHandlerTable(rSELF) 12459 bnez a3, 1f 12460 jr rBIX # nothing to do - jump to real handler 12461 1: 12462 EXPORT_PC() 12463 move a0, rPC # arg0 12464 move a1, rFP # arg1 12465 move a2, rSELF # arg2 12466 JAL(dvmCheckBefore) 12467 jr rBIX 12468 12469 /* ------------------------------ */ 12470 .balign 128 12471 .L_ALT_OP_MOVE_RESULT: /* 0x0a */ 12472 /* File: mips/alt_stub.S */ 12473 /* 12474 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12475 * any interesting requests and then jump to the real instruction 12476 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12477 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12478 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12479 * bail to the real handler if breakFlags==0. 12480 */ 12481 lbu a3, offThread_breakFlags(rSELF) 12482 la rBIX, dvmAsmInstructionStart + (10 * 128) 12483 lw rIBASE, offThread_curHandlerTable(rSELF) 12484 bnez a3, 1f 12485 jr rBIX # nothing to do - jump to real handler 12486 1: 12487 EXPORT_PC() 12488 move a0, rPC # arg0 12489 move a1, rFP # arg1 12490 move a2, rSELF # arg2 12491 JAL(dvmCheckBefore) 12492 jr rBIX 12493 12494 /* ------------------------------ */ 12495 .balign 128 12496 .L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */ 12497 /* File: mips/alt_stub.S */ 12498 /* 12499 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12500 * any interesting requests and then jump to the real instruction 12501 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12502 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12503 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12504 * bail to the real handler if breakFlags==0. 12505 */ 12506 lbu a3, offThread_breakFlags(rSELF) 12507 la rBIX, dvmAsmInstructionStart + (11 * 128) 12508 lw rIBASE, offThread_curHandlerTable(rSELF) 12509 bnez a3, 1f 12510 jr rBIX # nothing to do - jump to real handler 12511 1: 12512 EXPORT_PC() 12513 move a0, rPC # arg0 12514 move a1, rFP # arg1 12515 move a2, rSELF # arg2 12516 JAL(dvmCheckBefore) 12517 jr rBIX 12518 12519 /* ------------------------------ */ 12520 .balign 128 12521 .L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 12522 /* File: mips/alt_stub.S */ 12523 /* 12524 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12525 * any interesting requests and then jump to the real instruction 12526 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12527 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12528 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12529 * bail to the real handler if breakFlags==0. 12530 */ 12531 lbu a3, offThread_breakFlags(rSELF) 12532 la rBIX, dvmAsmInstructionStart + (12 * 128) 12533 lw rIBASE, offThread_curHandlerTable(rSELF) 12534 bnez a3, 1f 12535 jr rBIX # nothing to do - jump to real handler 12536 1: 12537 EXPORT_PC() 12538 move a0, rPC # arg0 12539 move a1, rFP # arg1 12540 move a2, rSELF # arg2 12541 JAL(dvmCheckBefore) 12542 jr rBIX 12543 12544 /* ------------------------------ */ 12545 .balign 128 12546 .L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */ 12547 /* File: mips/alt_stub.S */ 12548 /* 12549 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12550 * any interesting requests and then jump to the real instruction 12551 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12552 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12553 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12554 * bail to the real handler if breakFlags==0. 12555 */ 12556 lbu a3, offThread_breakFlags(rSELF) 12557 la rBIX, dvmAsmInstructionStart + (13 * 128) 12558 lw rIBASE, offThread_curHandlerTable(rSELF) 12559 bnez a3, 1f 12560 jr rBIX # nothing to do - jump to real handler 12561 1: 12562 EXPORT_PC() 12563 move a0, rPC # arg0 12564 move a1, rFP # arg1 12565 move a2, rSELF # arg2 12566 JAL(dvmCheckBefore) 12567 jr rBIX 12568 12569 /* ------------------------------ */ 12570 .balign 128 12571 .L_ALT_OP_RETURN_VOID: /* 0x0e */ 12572 /* File: mips/alt_stub.S */ 12573 /* 12574 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12575 * any interesting requests and then jump to the real instruction 12576 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12577 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12578 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12579 * bail to the real handler if breakFlags==0. 12580 */ 12581 lbu a3, offThread_breakFlags(rSELF) 12582 la rBIX, dvmAsmInstructionStart + (14 * 128) 12583 lw rIBASE, offThread_curHandlerTable(rSELF) 12584 bnez a3, 1f 12585 jr rBIX # nothing to do - jump to real handler 12586 1: 12587 EXPORT_PC() 12588 move a0, rPC # arg0 12589 move a1, rFP # arg1 12590 move a2, rSELF # arg2 12591 JAL(dvmCheckBefore) 12592 jr rBIX 12593 12594 /* ------------------------------ */ 12595 .balign 128 12596 .L_ALT_OP_RETURN: /* 0x0f */ 12597 /* File: mips/alt_stub.S */ 12598 /* 12599 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12600 * any interesting requests and then jump to the real instruction 12601 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12602 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12603 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12604 * bail to the real handler if breakFlags==0. 12605 */ 12606 lbu a3, offThread_breakFlags(rSELF) 12607 la rBIX, dvmAsmInstructionStart + (15 * 128) 12608 lw rIBASE, offThread_curHandlerTable(rSELF) 12609 bnez a3, 1f 12610 jr rBIX # nothing to do - jump to real handler 12611 1: 12612 EXPORT_PC() 12613 move a0, rPC # arg0 12614 move a1, rFP # arg1 12615 move a2, rSELF # arg2 12616 JAL(dvmCheckBefore) 12617 jr rBIX 12618 12619 /* ------------------------------ */ 12620 .balign 128 12621 .L_ALT_OP_RETURN_WIDE: /* 0x10 */ 12622 /* File: mips/alt_stub.S */ 12623 /* 12624 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12625 * any interesting requests and then jump to the real instruction 12626 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12627 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12628 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12629 * bail to the real handler if breakFlags==0. 12630 */ 12631 lbu a3, offThread_breakFlags(rSELF) 12632 la rBIX, dvmAsmInstructionStart + (16 * 128) 12633 lw rIBASE, offThread_curHandlerTable(rSELF) 12634 bnez a3, 1f 12635 jr rBIX # nothing to do - jump to real handler 12636 1: 12637 EXPORT_PC() 12638 move a0, rPC # arg0 12639 move a1, rFP # arg1 12640 move a2, rSELF # arg2 12641 JAL(dvmCheckBefore) 12642 jr rBIX 12643 12644 /* ------------------------------ */ 12645 .balign 128 12646 .L_ALT_OP_RETURN_OBJECT: /* 0x11 */ 12647 /* File: mips/alt_stub.S */ 12648 /* 12649 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12650 * any interesting requests and then jump to the real instruction 12651 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12652 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12653 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12654 * bail to the real handler if breakFlags==0. 12655 */ 12656 lbu a3, offThread_breakFlags(rSELF) 12657 la rBIX, dvmAsmInstructionStart + (17 * 128) 12658 lw rIBASE, offThread_curHandlerTable(rSELF) 12659 bnez a3, 1f 12660 jr rBIX # nothing to do - jump to real handler 12661 1: 12662 EXPORT_PC() 12663 move a0, rPC # arg0 12664 move a1, rFP # arg1 12665 move a2, rSELF # arg2 12666 JAL(dvmCheckBefore) 12667 jr rBIX 12668 12669 /* ------------------------------ */ 12670 .balign 128 12671 .L_ALT_OP_CONST_4: /* 0x12 */ 12672 /* File: mips/alt_stub.S */ 12673 /* 12674 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12675 * any interesting requests and then jump to the real instruction 12676 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12677 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12678 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12679 * bail to the real handler if breakFlags==0. 12680 */ 12681 lbu a3, offThread_breakFlags(rSELF) 12682 la rBIX, dvmAsmInstructionStart + (18 * 128) 12683 lw rIBASE, offThread_curHandlerTable(rSELF) 12684 bnez a3, 1f 12685 jr rBIX # nothing to do - jump to real handler 12686 1: 12687 EXPORT_PC() 12688 move a0, rPC # arg0 12689 move a1, rFP # arg1 12690 move a2, rSELF # arg2 12691 JAL(dvmCheckBefore) 12692 jr rBIX 12693 12694 /* ------------------------------ */ 12695 .balign 128 12696 .L_ALT_OP_CONST_16: /* 0x13 */ 12697 /* File: mips/alt_stub.S */ 12698 /* 12699 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12700 * any interesting requests and then jump to the real instruction 12701 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12702 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12703 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12704 * bail to the real handler if breakFlags==0. 12705 */ 12706 lbu a3, offThread_breakFlags(rSELF) 12707 la rBIX, dvmAsmInstructionStart + (19 * 128) 12708 lw rIBASE, offThread_curHandlerTable(rSELF) 12709 bnez a3, 1f 12710 jr rBIX # nothing to do - jump to real handler 12711 1: 12712 EXPORT_PC() 12713 move a0, rPC # arg0 12714 move a1, rFP # arg1 12715 move a2, rSELF # arg2 12716 JAL(dvmCheckBefore) 12717 jr rBIX 12718 12719 /* ------------------------------ */ 12720 .balign 128 12721 .L_ALT_OP_CONST: /* 0x14 */ 12722 /* File: mips/alt_stub.S */ 12723 /* 12724 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12725 * any interesting requests and then jump to the real instruction 12726 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12727 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12728 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12729 * bail to the real handler if breakFlags==0. 12730 */ 12731 lbu a3, offThread_breakFlags(rSELF) 12732 la rBIX, dvmAsmInstructionStart + (20 * 128) 12733 lw rIBASE, offThread_curHandlerTable(rSELF) 12734 bnez a3, 1f 12735 jr rBIX # nothing to do - jump to real handler 12736 1: 12737 EXPORT_PC() 12738 move a0, rPC # arg0 12739 move a1, rFP # arg1 12740 move a2, rSELF # arg2 12741 JAL(dvmCheckBefore) 12742 jr rBIX 12743 12744 /* ------------------------------ */ 12745 .balign 128 12746 .L_ALT_OP_CONST_HIGH16: /* 0x15 */ 12747 /* File: mips/alt_stub.S */ 12748 /* 12749 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12750 * any interesting requests and then jump to the real instruction 12751 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12752 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12753 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12754 * bail to the real handler if breakFlags==0. 12755 */ 12756 lbu a3, offThread_breakFlags(rSELF) 12757 la rBIX, dvmAsmInstructionStart + (21 * 128) 12758 lw rIBASE, offThread_curHandlerTable(rSELF) 12759 bnez a3, 1f 12760 jr rBIX # nothing to do - jump to real handler 12761 1: 12762 EXPORT_PC() 12763 move a0, rPC # arg0 12764 move a1, rFP # arg1 12765 move a2, rSELF # arg2 12766 JAL(dvmCheckBefore) 12767 jr rBIX 12768 12769 /* ------------------------------ */ 12770 .balign 128 12771 .L_ALT_OP_CONST_WIDE_16: /* 0x16 */ 12772 /* File: mips/alt_stub.S */ 12773 /* 12774 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12775 * any interesting requests and then jump to the real instruction 12776 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12777 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12778 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12779 * bail to the real handler if breakFlags==0. 12780 */ 12781 lbu a3, offThread_breakFlags(rSELF) 12782 la rBIX, dvmAsmInstructionStart + (22 * 128) 12783 lw rIBASE, offThread_curHandlerTable(rSELF) 12784 bnez a3, 1f 12785 jr rBIX # nothing to do - jump to real handler 12786 1: 12787 EXPORT_PC() 12788 move a0, rPC # arg0 12789 move a1, rFP # arg1 12790 move a2, rSELF # arg2 12791 JAL(dvmCheckBefore) 12792 jr rBIX 12793 12794 /* ------------------------------ */ 12795 .balign 128 12796 .L_ALT_OP_CONST_WIDE_32: /* 0x17 */ 12797 /* File: mips/alt_stub.S */ 12798 /* 12799 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12800 * any interesting requests and then jump to the real instruction 12801 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12802 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12803 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12804 * bail to the real handler if breakFlags==0. 12805 */ 12806 lbu a3, offThread_breakFlags(rSELF) 12807 la rBIX, dvmAsmInstructionStart + (23 * 128) 12808 lw rIBASE, offThread_curHandlerTable(rSELF) 12809 bnez a3, 1f 12810 jr rBIX # nothing to do - jump to real handler 12811 1: 12812 EXPORT_PC() 12813 move a0, rPC # arg0 12814 move a1, rFP # arg1 12815 move a2, rSELF # arg2 12816 JAL(dvmCheckBefore) 12817 jr rBIX 12818 12819 /* ------------------------------ */ 12820 .balign 128 12821 .L_ALT_OP_CONST_WIDE: /* 0x18 */ 12822 /* File: mips/alt_stub.S */ 12823 /* 12824 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12825 * any interesting requests and then jump to the real instruction 12826 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12827 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12828 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12829 * bail to the real handler if breakFlags==0. 12830 */ 12831 lbu a3, offThread_breakFlags(rSELF) 12832 la rBIX, dvmAsmInstructionStart + (24 * 128) 12833 lw rIBASE, offThread_curHandlerTable(rSELF) 12834 bnez a3, 1f 12835 jr rBIX # nothing to do - jump to real handler 12836 1: 12837 EXPORT_PC() 12838 move a0, rPC # arg0 12839 move a1, rFP # arg1 12840 move a2, rSELF # arg2 12841 JAL(dvmCheckBefore) 12842 jr rBIX 12843 12844 /* ------------------------------ */ 12845 .balign 128 12846 .L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */ 12847 /* File: mips/alt_stub.S */ 12848 /* 12849 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12850 * any interesting requests and then jump to the real instruction 12851 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12852 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12853 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12854 * bail to the real handler if breakFlags==0. 12855 */ 12856 lbu a3, offThread_breakFlags(rSELF) 12857 la rBIX, dvmAsmInstructionStart + (25 * 128) 12858 lw rIBASE, offThread_curHandlerTable(rSELF) 12859 bnez a3, 1f 12860 jr rBIX # nothing to do - jump to real handler 12861 1: 12862 EXPORT_PC() 12863 move a0, rPC # arg0 12864 move a1, rFP # arg1 12865 move a2, rSELF # arg2 12866 JAL(dvmCheckBefore) 12867 jr rBIX 12868 12869 /* ------------------------------ */ 12870 .balign 128 12871 .L_ALT_OP_CONST_STRING: /* 0x1a */ 12872 /* File: mips/alt_stub.S */ 12873 /* 12874 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12875 * any interesting requests and then jump to the real instruction 12876 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12877 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12878 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12879 * bail to the real handler if breakFlags==0. 12880 */ 12881 lbu a3, offThread_breakFlags(rSELF) 12882 la rBIX, dvmAsmInstructionStart + (26 * 128) 12883 lw rIBASE, offThread_curHandlerTable(rSELF) 12884 bnez a3, 1f 12885 jr rBIX # nothing to do - jump to real handler 12886 1: 12887 EXPORT_PC() 12888 move a0, rPC # arg0 12889 move a1, rFP # arg1 12890 move a2, rSELF # arg2 12891 JAL(dvmCheckBefore) 12892 jr rBIX 12893 12894 /* ------------------------------ */ 12895 .balign 128 12896 .L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */ 12897 /* File: mips/alt_stub.S */ 12898 /* 12899 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12900 * any interesting requests and then jump to the real instruction 12901 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12902 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12903 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12904 * bail to the real handler if breakFlags==0. 12905 */ 12906 lbu a3, offThread_breakFlags(rSELF) 12907 la rBIX, dvmAsmInstructionStart + (27 * 128) 12908 lw rIBASE, offThread_curHandlerTable(rSELF) 12909 bnez a3, 1f 12910 jr rBIX # nothing to do - jump to real handler 12911 1: 12912 EXPORT_PC() 12913 move a0, rPC # arg0 12914 move a1, rFP # arg1 12915 move a2, rSELF # arg2 12916 JAL(dvmCheckBefore) 12917 jr rBIX 12918 12919 /* ------------------------------ */ 12920 .balign 128 12921 .L_ALT_OP_CONST_CLASS: /* 0x1c */ 12922 /* File: mips/alt_stub.S */ 12923 /* 12924 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12925 * any interesting requests and then jump to the real instruction 12926 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12927 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12928 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12929 * bail to the real handler if breakFlags==0. 12930 */ 12931 lbu a3, offThread_breakFlags(rSELF) 12932 la rBIX, dvmAsmInstructionStart + (28 * 128) 12933 lw rIBASE, offThread_curHandlerTable(rSELF) 12934 bnez a3, 1f 12935 jr rBIX # nothing to do - jump to real handler 12936 1: 12937 EXPORT_PC() 12938 move a0, rPC # arg0 12939 move a1, rFP # arg1 12940 move a2, rSELF # arg2 12941 JAL(dvmCheckBefore) 12942 jr rBIX 12943 12944 /* ------------------------------ */ 12945 .balign 128 12946 .L_ALT_OP_MONITOR_ENTER: /* 0x1d */ 12947 /* File: mips/alt_stub.S */ 12948 /* 12949 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12950 * any interesting requests and then jump to the real instruction 12951 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12952 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12953 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12954 * bail to the real handler if breakFlags==0. 12955 */ 12956 lbu a3, offThread_breakFlags(rSELF) 12957 la rBIX, dvmAsmInstructionStart + (29 * 128) 12958 lw rIBASE, offThread_curHandlerTable(rSELF) 12959 bnez a3, 1f 12960 jr rBIX # nothing to do - jump to real handler 12961 1: 12962 EXPORT_PC() 12963 move a0, rPC # arg0 12964 move a1, rFP # arg1 12965 move a2, rSELF # arg2 12966 JAL(dvmCheckBefore) 12967 jr rBIX 12968 12969 /* ------------------------------ */ 12970 .balign 128 12971 .L_ALT_OP_MONITOR_EXIT: /* 0x1e */ 12972 /* File: mips/alt_stub.S */ 12973 /* 12974 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 12975 * any interesting requests and then jump to the real instruction 12976 * handler. Note that the call to dvmCheckBefore is done as a tail call. 12977 * rIBASE updates won't be seen until a refresh, and we can tell we have a 12978 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 12979 * bail to the real handler if breakFlags==0. 12980 */ 12981 lbu a3, offThread_breakFlags(rSELF) 12982 la rBIX, dvmAsmInstructionStart + (30 * 128) 12983 lw rIBASE, offThread_curHandlerTable(rSELF) 12984 bnez a3, 1f 12985 jr rBIX # nothing to do - jump to real handler 12986 1: 12987 EXPORT_PC() 12988 move a0, rPC # arg0 12989 move a1, rFP # arg1 12990 move a2, rSELF # arg2 12991 JAL(dvmCheckBefore) 12992 jr rBIX 12993 12994 /* ------------------------------ */ 12995 .balign 128 12996 .L_ALT_OP_CHECK_CAST: /* 0x1f */ 12997 /* File: mips/alt_stub.S */ 12998 /* 12999 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13000 * any interesting requests and then jump to the real instruction 13001 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13002 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13003 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13004 * bail to the real handler if breakFlags==0. 13005 */ 13006 lbu a3, offThread_breakFlags(rSELF) 13007 la rBIX, dvmAsmInstructionStart + (31 * 128) 13008 lw rIBASE, offThread_curHandlerTable(rSELF) 13009 bnez a3, 1f 13010 jr rBIX # nothing to do - jump to real handler 13011 1: 13012 EXPORT_PC() 13013 move a0, rPC # arg0 13014 move a1, rFP # arg1 13015 move a2, rSELF # arg2 13016 JAL(dvmCheckBefore) 13017 jr rBIX 13018 13019 /* ------------------------------ */ 13020 .balign 128 13021 .L_ALT_OP_INSTANCE_OF: /* 0x20 */ 13022 /* File: mips/alt_stub.S */ 13023 /* 13024 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13025 * any interesting requests and then jump to the real instruction 13026 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13027 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13028 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13029 * bail to the real handler if breakFlags==0. 13030 */ 13031 lbu a3, offThread_breakFlags(rSELF) 13032 la rBIX, dvmAsmInstructionStart + (32 * 128) 13033 lw rIBASE, offThread_curHandlerTable(rSELF) 13034 bnez a3, 1f 13035 jr rBIX # nothing to do - jump to real handler 13036 1: 13037 EXPORT_PC() 13038 move a0, rPC # arg0 13039 move a1, rFP # arg1 13040 move a2, rSELF # arg2 13041 JAL(dvmCheckBefore) 13042 jr rBIX 13043 13044 /* ------------------------------ */ 13045 .balign 128 13046 .L_ALT_OP_ARRAY_LENGTH: /* 0x21 */ 13047 /* File: mips/alt_stub.S */ 13048 /* 13049 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13050 * any interesting requests and then jump to the real instruction 13051 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13052 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13053 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13054 * bail to the real handler if breakFlags==0. 13055 */ 13056 lbu a3, offThread_breakFlags(rSELF) 13057 la rBIX, dvmAsmInstructionStart + (33 * 128) 13058 lw rIBASE, offThread_curHandlerTable(rSELF) 13059 bnez a3, 1f 13060 jr rBIX # nothing to do - jump to real handler 13061 1: 13062 EXPORT_PC() 13063 move a0, rPC # arg0 13064 move a1, rFP # arg1 13065 move a2, rSELF # arg2 13066 JAL(dvmCheckBefore) 13067 jr rBIX 13068 13069 /* ------------------------------ */ 13070 .balign 128 13071 .L_ALT_OP_NEW_INSTANCE: /* 0x22 */ 13072 /* File: mips/alt_stub.S */ 13073 /* 13074 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13075 * any interesting requests and then jump to the real instruction 13076 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13077 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13078 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13079 * bail to the real handler if breakFlags==0. 13080 */ 13081 lbu a3, offThread_breakFlags(rSELF) 13082 la rBIX, dvmAsmInstructionStart + (34 * 128) 13083 lw rIBASE, offThread_curHandlerTable(rSELF) 13084 bnez a3, 1f 13085 jr rBIX # nothing to do - jump to real handler 13086 1: 13087 EXPORT_PC() 13088 move a0, rPC # arg0 13089 move a1, rFP # arg1 13090 move a2, rSELF # arg2 13091 JAL(dvmCheckBefore) 13092 jr rBIX 13093 13094 /* ------------------------------ */ 13095 .balign 128 13096 .L_ALT_OP_NEW_ARRAY: /* 0x23 */ 13097 /* File: mips/alt_stub.S */ 13098 /* 13099 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13100 * any interesting requests and then jump to the real instruction 13101 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13102 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13103 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13104 * bail to the real handler if breakFlags==0. 13105 */ 13106 lbu a3, offThread_breakFlags(rSELF) 13107 la rBIX, dvmAsmInstructionStart + (35 * 128) 13108 lw rIBASE, offThread_curHandlerTable(rSELF) 13109 bnez a3, 1f 13110 jr rBIX # nothing to do - jump to real handler 13111 1: 13112 EXPORT_PC() 13113 move a0, rPC # arg0 13114 move a1, rFP # arg1 13115 move a2, rSELF # arg2 13116 JAL(dvmCheckBefore) 13117 jr rBIX 13118 13119 /* ------------------------------ */ 13120 .balign 128 13121 .L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */ 13122 /* File: mips/alt_stub.S */ 13123 /* 13124 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13125 * any interesting requests and then jump to the real instruction 13126 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13127 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13128 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13129 * bail to the real handler if breakFlags==0. 13130 */ 13131 lbu a3, offThread_breakFlags(rSELF) 13132 la rBIX, dvmAsmInstructionStart + (36 * 128) 13133 lw rIBASE, offThread_curHandlerTable(rSELF) 13134 bnez a3, 1f 13135 jr rBIX # nothing to do - jump to real handler 13136 1: 13137 EXPORT_PC() 13138 move a0, rPC # arg0 13139 move a1, rFP # arg1 13140 move a2, rSELF # arg2 13141 JAL(dvmCheckBefore) 13142 jr rBIX 13143 13144 /* ------------------------------ */ 13145 .balign 128 13146 .L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 13147 /* File: mips/alt_stub.S */ 13148 /* 13149 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13150 * any interesting requests and then jump to the real instruction 13151 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13152 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13153 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13154 * bail to the real handler if breakFlags==0. 13155 */ 13156 lbu a3, offThread_breakFlags(rSELF) 13157 la rBIX, dvmAsmInstructionStart + (37 * 128) 13158 lw rIBASE, offThread_curHandlerTable(rSELF) 13159 bnez a3, 1f 13160 jr rBIX # nothing to do - jump to real handler 13161 1: 13162 EXPORT_PC() 13163 move a0, rPC # arg0 13164 move a1, rFP # arg1 13165 move a2, rSELF # arg2 13166 JAL(dvmCheckBefore) 13167 jr rBIX 13168 13169 /* ------------------------------ */ 13170 .balign 128 13171 .L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */ 13172 /* File: mips/alt_stub.S */ 13173 /* 13174 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13175 * any interesting requests and then jump to the real instruction 13176 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13177 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13178 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13179 * bail to the real handler if breakFlags==0. 13180 */ 13181 lbu a3, offThread_breakFlags(rSELF) 13182 la rBIX, dvmAsmInstructionStart + (38 * 128) 13183 lw rIBASE, offThread_curHandlerTable(rSELF) 13184 bnez a3, 1f 13185 jr rBIX # nothing to do - jump to real handler 13186 1: 13187 EXPORT_PC() 13188 move a0, rPC # arg0 13189 move a1, rFP # arg1 13190 move a2, rSELF # arg2 13191 JAL(dvmCheckBefore) 13192 jr rBIX 13193 13194 /* ------------------------------ */ 13195 .balign 128 13196 .L_ALT_OP_THROW: /* 0x27 */ 13197 /* File: mips/alt_stub.S */ 13198 /* 13199 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13200 * any interesting requests and then jump to the real instruction 13201 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13202 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13203 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13204 * bail to the real handler if breakFlags==0. 13205 */ 13206 lbu a3, offThread_breakFlags(rSELF) 13207 la rBIX, dvmAsmInstructionStart + (39 * 128) 13208 lw rIBASE, offThread_curHandlerTable(rSELF) 13209 bnez a3, 1f 13210 jr rBIX # nothing to do - jump to real handler 13211 1: 13212 EXPORT_PC() 13213 move a0, rPC # arg0 13214 move a1, rFP # arg1 13215 move a2, rSELF # arg2 13216 JAL(dvmCheckBefore) 13217 jr rBIX 13218 13219 /* ------------------------------ */ 13220 .balign 128 13221 .L_ALT_OP_GOTO: /* 0x28 */ 13222 /* File: mips/alt_stub.S */ 13223 /* 13224 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13225 * any interesting requests and then jump to the real instruction 13226 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13227 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13228 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13229 * bail to the real handler if breakFlags==0. 13230 */ 13231 lbu a3, offThread_breakFlags(rSELF) 13232 la rBIX, dvmAsmInstructionStart + (40 * 128) 13233 lw rIBASE, offThread_curHandlerTable(rSELF) 13234 bnez a3, 1f 13235 jr rBIX # nothing to do - jump to real handler 13236 1: 13237 EXPORT_PC() 13238 move a0, rPC # arg0 13239 move a1, rFP # arg1 13240 move a2, rSELF # arg2 13241 JAL(dvmCheckBefore) 13242 jr rBIX 13243 13244 /* ------------------------------ */ 13245 .balign 128 13246 .L_ALT_OP_GOTO_16: /* 0x29 */ 13247 /* File: mips/alt_stub.S */ 13248 /* 13249 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13250 * any interesting requests and then jump to the real instruction 13251 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13252 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13253 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13254 * bail to the real handler if breakFlags==0. 13255 */ 13256 lbu a3, offThread_breakFlags(rSELF) 13257 la rBIX, dvmAsmInstructionStart + (41 * 128) 13258 lw rIBASE, offThread_curHandlerTable(rSELF) 13259 bnez a3, 1f 13260 jr rBIX # nothing to do - jump to real handler 13261 1: 13262 EXPORT_PC() 13263 move a0, rPC # arg0 13264 move a1, rFP # arg1 13265 move a2, rSELF # arg2 13266 JAL(dvmCheckBefore) 13267 jr rBIX 13268 13269 /* ------------------------------ */ 13270 .balign 128 13271 .L_ALT_OP_GOTO_32: /* 0x2a */ 13272 /* File: mips/alt_stub.S */ 13273 /* 13274 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13275 * any interesting requests and then jump to the real instruction 13276 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13277 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13278 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13279 * bail to the real handler if breakFlags==0. 13280 */ 13281 lbu a3, offThread_breakFlags(rSELF) 13282 la rBIX, dvmAsmInstructionStart + (42 * 128) 13283 lw rIBASE, offThread_curHandlerTable(rSELF) 13284 bnez a3, 1f 13285 jr rBIX # nothing to do - jump to real handler 13286 1: 13287 EXPORT_PC() 13288 move a0, rPC # arg0 13289 move a1, rFP # arg1 13290 move a2, rSELF # arg2 13291 JAL(dvmCheckBefore) 13292 jr rBIX 13293 13294 /* ------------------------------ */ 13295 .balign 128 13296 .L_ALT_OP_PACKED_SWITCH: /* 0x2b */ 13297 /* File: mips/alt_stub.S */ 13298 /* 13299 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13300 * any interesting requests and then jump to the real instruction 13301 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13302 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13303 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13304 * bail to the real handler if breakFlags==0. 13305 */ 13306 lbu a3, offThread_breakFlags(rSELF) 13307 la rBIX, dvmAsmInstructionStart + (43 * 128) 13308 lw rIBASE, offThread_curHandlerTable(rSELF) 13309 bnez a3, 1f 13310 jr rBIX # nothing to do - jump to real handler 13311 1: 13312 EXPORT_PC() 13313 move a0, rPC # arg0 13314 move a1, rFP # arg1 13315 move a2, rSELF # arg2 13316 JAL(dvmCheckBefore) 13317 jr rBIX 13318 13319 /* ------------------------------ */ 13320 .balign 128 13321 .L_ALT_OP_SPARSE_SWITCH: /* 0x2c */ 13322 /* File: mips/alt_stub.S */ 13323 /* 13324 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13325 * any interesting requests and then jump to the real instruction 13326 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13327 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13328 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13329 * bail to the real handler if breakFlags==0. 13330 */ 13331 lbu a3, offThread_breakFlags(rSELF) 13332 la rBIX, dvmAsmInstructionStart + (44 * 128) 13333 lw rIBASE, offThread_curHandlerTable(rSELF) 13334 bnez a3, 1f 13335 jr rBIX # nothing to do - jump to real handler 13336 1: 13337 EXPORT_PC() 13338 move a0, rPC # arg0 13339 move a1, rFP # arg1 13340 move a2, rSELF # arg2 13341 JAL(dvmCheckBefore) 13342 jr rBIX 13343 13344 /* ------------------------------ */ 13345 .balign 128 13346 .L_ALT_OP_CMPL_FLOAT: /* 0x2d */ 13347 /* File: mips/alt_stub.S */ 13348 /* 13349 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13350 * any interesting requests and then jump to the real instruction 13351 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13352 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13353 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13354 * bail to the real handler if breakFlags==0. 13355 */ 13356 lbu a3, offThread_breakFlags(rSELF) 13357 la rBIX, dvmAsmInstructionStart + (45 * 128) 13358 lw rIBASE, offThread_curHandlerTable(rSELF) 13359 bnez a3, 1f 13360 jr rBIX # nothing to do - jump to real handler 13361 1: 13362 EXPORT_PC() 13363 move a0, rPC # arg0 13364 move a1, rFP # arg1 13365 move a2, rSELF # arg2 13366 JAL(dvmCheckBefore) 13367 jr rBIX 13368 13369 /* ------------------------------ */ 13370 .balign 128 13371 .L_ALT_OP_CMPG_FLOAT: /* 0x2e */ 13372 /* File: mips/alt_stub.S */ 13373 /* 13374 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13375 * any interesting requests and then jump to the real instruction 13376 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13377 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13378 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13379 * bail to the real handler if breakFlags==0. 13380 */ 13381 lbu a3, offThread_breakFlags(rSELF) 13382 la rBIX, dvmAsmInstructionStart + (46 * 128) 13383 lw rIBASE, offThread_curHandlerTable(rSELF) 13384 bnez a3, 1f 13385 jr rBIX # nothing to do - jump to real handler 13386 1: 13387 EXPORT_PC() 13388 move a0, rPC # arg0 13389 move a1, rFP # arg1 13390 move a2, rSELF # arg2 13391 JAL(dvmCheckBefore) 13392 jr rBIX 13393 13394 /* ------------------------------ */ 13395 .balign 128 13396 .L_ALT_OP_CMPL_DOUBLE: /* 0x2f */ 13397 /* File: mips/alt_stub.S */ 13398 /* 13399 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13400 * any interesting requests and then jump to the real instruction 13401 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13402 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13403 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13404 * bail to the real handler if breakFlags==0. 13405 */ 13406 lbu a3, offThread_breakFlags(rSELF) 13407 la rBIX, dvmAsmInstructionStart + (47 * 128) 13408 lw rIBASE, offThread_curHandlerTable(rSELF) 13409 bnez a3, 1f 13410 jr rBIX # nothing to do - jump to real handler 13411 1: 13412 EXPORT_PC() 13413 move a0, rPC # arg0 13414 move a1, rFP # arg1 13415 move a2, rSELF # arg2 13416 JAL(dvmCheckBefore) 13417 jr rBIX 13418 13419 /* ------------------------------ */ 13420 .balign 128 13421 .L_ALT_OP_CMPG_DOUBLE: /* 0x30 */ 13422 /* File: mips/alt_stub.S */ 13423 /* 13424 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13425 * any interesting requests and then jump to the real instruction 13426 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13427 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13428 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13429 * bail to the real handler if breakFlags==0. 13430 */ 13431 lbu a3, offThread_breakFlags(rSELF) 13432 la rBIX, dvmAsmInstructionStart + (48 * 128) 13433 lw rIBASE, offThread_curHandlerTable(rSELF) 13434 bnez a3, 1f 13435 jr rBIX # nothing to do - jump to real handler 13436 1: 13437 EXPORT_PC() 13438 move a0, rPC # arg0 13439 move a1, rFP # arg1 13440 move a2, rSELF # arg2 13441 JAL(dvmCheckBefore) 13442 jr rBIX 13443 13444 /* ------------------------------ */ 13445 .balign 128 13446 .L_ALT_OP_CMP_LONG: /* 0x31 */ 13447 /* File: mips/alt_stub.S */ 13448 /* 13449 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13450 * any interesting requests and then jump to the real instruction 13451 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13452 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13453 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13454 * bail to the real handler if breakFlags==0. 13455 */ 13456 lbu a3, offThread_breakFlags(rSELF) 13457 la rBIX, dvmAsmInstructionStart + (49 * 128) 13458 lw rIBASE, offThread_curHandlerTable(rSELF) 13459 bnez a3, 1f 13460 jr rBIX # nothing to do - jump to real handler 13461 1: 13462 EXPORT_PC() 13463 move a0, rPC # arg0 13464 move a1, rFP # arg1 13465 move a2, rSELF # arg2 13466 JAL(dvmCheckBefore) 13467 jr rBIX 13468 13469 /* ------------------------------ */ 13470 .balign 128 13471 .L_ALT_OP_IF_EQ: /* 0x32 */ 13472 /* File: mips/alt_stub.S */ 13473 /* 13474 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13475 * any interesting requests and then jump to the real instruction 13476 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13477 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13478 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13479 * bail to the real handler if breakFlags==0. 13480 */ 13481 lbu a3, offThread_breakFlags(rSELF) 13482 la rBIX, dvmAsmInstructionStart + (50 * 128) 13483 lw rIBASE, offThread_curHandlerTable(rSELF) 13484 bnez a3, 1f 13485 jr rBIX # nothing to do - jump to real handler 13486 1: 13487 EXPORT_PC() 13488 move a0, rPC # arg0 13489 move a1, rFP # arg1 13490 move a2, rSELF # arg2 13491 JAL(dvmCheckBefore) 13492 jr rBIX 13493 13494 /* ------------------------------ */ 13495 .balign 128 13496 .L_ALT_OP_IF_NE: /* 0x33 */ 13497 /* File: mips/alt_stub.S */ 13498 /* 13499 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13500 * any interesting requests and then jump to the real instruction 13501 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13502 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13503 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13504 * bail to the real handler if breakFlags==0. 13505 */ 13506 lbu a3, offThread_breakFlags(rSELF) 13507 la rBIX, dvmAsmInstructionStart + (51 * 128) 13508 lw rIBASE, offThread_curHandlerTable(rSELF) 13509 bnez a3, 1f 13510 jr rBIX # nothing to do - jump to real handler 13511 1: 13512 EXPORT_PC() 13513 move a0, rPC # arg0 13514 move a1, rFP # arg1 13515 move a2, rSELF # arg2 13516 JAL(dvmCheckBefore) 13517 jr rBIX 13518 13519 /* ------------------------------ */ 13520 .balign 128 13521 .L_ALT_OP_IF_LT: /* 0x34 */ 13522 /* File: mips/alt_stub.S */ 13523 /* 13524 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13525 * any interesting requests and then jump to the real instruction 13526 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13527 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13528 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13529 * bail to the real handler if breakFlags==0. 13530 */ 13531 lbu a3, offThread_breakFlags(rSELF) 13532 la rBIX, dvmAsmInstructionStart + (52 * 128) 13533 lw rIBASE, offThread_curHandlerTable(rSELF) 13534 bnez a3, 1f 13535 jr rBIX # nothing to do - jump to real handler 13536 1: 13537 EXPORT_PC() 13538 move a0, rPC # arg0 13539 move a1, rFP # arg1 13540 move a2, rSELF # arg2 13541 JAL(dvmCheckBefore) 13542 jr rBIX 13543 13544 /* ------------------------------ */ 13545 .balign 128 13546 .L_ALT_OP_IF_GE: /* 0x35 */ 13547 /* File: mips/alt_stub.S */ 13548 /* 13549 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13550 * any interesting requests and then jump to the real instruction 13551 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13552 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13553 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13554 * bail to the real handler if breakFlags==0. 13555 */ 13556 lbu a3, offThread_breakFlags(rSELF) 13557 la rBIX, dvmAsmInstructionStart + (53 * 128) 13558 lw rIBASE, offThread_curHandlerTable(rSELF) 13559 bnez a3, 1f 13560 jr rBIX # nothing to do - jump to real handler 13561 1: 13562 EXPORT_PC() 13563 move a0, rPC # arg0 13564 move a1, rFP # arg1 13565 move a2, rSELF # arg2 13566 JAL(dvmCheckBefore) 13567 jr rBIX 13568 13569 /* ------------------------------ */ 13570 .balign 128 13571 .L_ALT_OP_IF_GT: /* 0x36 */ 13572 /* File: mips/alt_stub.S */ 13573 /* 13574 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13575 * any interesting requests and then jump to the real instruction 13576 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13577 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13578 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13579 * bail to the real handler if breakFlags==0. 13580 */ 13581 lbu a3, offThread_breakFlags(rSELF) 13582 la rBIX, dvmAsmInstructionStart + (54 * 128) 13583 lw rIBASE, offThread_curHandlerTable(rSELF) 13584 bnez a3, 1f 13585 jr rBIX # nothing to do - jump to real handler 13586 1: 13587 EXPORT_PC() 13588 move a0, rPC # arg0 13589 move a1, rFP # arg1 13590 move a2, rSELF # arg2 13591 JAL(dvmCheckBefore) 13592 jr rBIX 13593 13594 /* ------------------------------ */ 13595 .balign 128 13596 .L_ALT_OP_IF_LE: /* 0x37 */ 13597 /* File: mips/alt_stub.S */ 13598 /* 13599 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13600 * any interesting requests and then jump to the real instruction 13601 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13602 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13603 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13604 * bail to the real handler if breakFlags==0. 13605 */ 13606 lbu a3, offThread_breakFlags(rSELF) 13607 la rBIX, dvmAsmInstructionStart + (55 * 128) 13608 lw rIBASE, offThread_curHandlerTable(rSELF) 13609 bnez a3, 1f 13610 jr rBIX # nothing to do - jump to real handler 13611 1: 13612 EXPORT_PC() 13613 move a0, rPC # arg0 13614 move a1, rFP # arg1 13615 move a2, rSELF # arg2 13616 JAL(dvmCheckBefore) 13617 jr rBIX 13618 13619 /* ------------------------------ */ 13620 .balign 128 13621 .L_ALT_OP_IF_EQZ: /* 0x38 */ 13622 /* File: mips/alt_stub.S */ 13623 /* 13624 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13625 * any interesting requests and then jump to the real instruction 13626 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13627 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13628 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13629 * bail to the real handler if breakFlags==0. 13630 */ 13631 lbu a3, offThread_breakFlags(rSELF) 13632 la rBIX, dvmAsmInstructionStart + (56 * 128) 13633 lw rIBASE, offThread_curHandlerTable(rSELF) 13634 bnez a3, 1f 13635 jr rBIX # nothing to do - jump to real handler 13636 1: 13637 EXPORT_PC() 13638 move a0, rPC # arg0 13639 move a1, rFP # arg1 13640 move a2, rSELF # arg2 13641 JAL(dvmCheckBefore) 13642 jr rBIX 13643 13644 /* ------------------------------ */ 13645 .balign 128 13646 .L_ALT_OP_IF_NEZ: /* 0x39 */ 13647 /* File: mips/alt_stub.S */ 13648 /* 13649 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13650 * any interesting requests and then jump to the real instruction 13651 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13652 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13653 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13654 * bail to the real handler if breakFlags==0. 13655 */ 13656 lbu a3, offThread_breakFlags(rSELF) 13657 la rBIX, dvmAsmInstructionStart + (57 * 128) 13658 lw rIBASE, offThread_curHandlerTable(rSELF) 13659 bnez a3, 1f 13660 jr rBIX # nothing to do - jump to real handler 13661 1: 13662 EXPORT_PC() 13663 move a0, rPC # arg0 13664 move a1, rFP # arg1 13665 move a2, rSELF # arg2 13666 JAL(dvmCheckBefore) 13667 jr rBIX 13668 13669 /* ------------------------------ */ 13670 .balign 128 13671 .L_ALT_OP_IF_LTZ: /* 0x3a */ 13672 /* File: mips/alt_stub.S */ 13673 /* 13674 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13675 * any interesting requests and then jump to the real instruction 13676 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13677 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13678 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13679 * bail to the real handler if breakFlags==0. 13680 */ 13681 lbu a3, offThread_breakFlags(rSELF) 13682 la rBIX, dvmAsmInstructionStart + (58 * 128) 13683 lw rIBASE, offThread_curHandlerTable(rSELF) 13684 bnez a3, 1f 13685 jr rBIX # nothing to do - jump to real handler 13686 1: 13687 EXPORT_PC() 13688 move a0, rPC # arg0 13689 move a1, rFP # arg1 13690 move a2, rSELF # arg2 13691 JAL(dvmCheckBefore) 13692 jr rBIX 13693 13694 /* ------------------------------ */ 13695 .balign 128 13696 .L_ALT_OP_IF_GEZ: /* 0x3b */ 13697 /* File: mips/alt_stub.S */ 13698 /* 13699 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13700 * any interesting requests and then jump to the real instruction 13701 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13702 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13703 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13704 * bail to the real handler if breakFlags==0. 13705 */ 13706 lbu a3, offThread_breakFlags(rSELF) 13707 la rBIX, dvmAsmInstructionStart + (59 * 128) 13708 lw rIBASE, offThread_curHandlerTable(rSELF) 13709 bnez a3, 1f 13710 jr rBIX # nothing to do - jump to real handler 13711 1: 13712 EXPORT_PC() 13713 move a0, rPC # arg0 13714 move a1, rFP # arg1 13715 move a2, rSELF # arg2 13716 JAL(dvmCheckBefore) 13717 jr rBIX 13718 13719 /* ------------------------------ */ 13720 .balign 128 13721 .L_ALT_OP_IF_GTZ: /* 0x3c */ 13722 /* File: mips/alt_stub.S */ 13723 /* 13724 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13725 * any interesting requests and then jump to the real instruction 13726 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13727 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13728 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13729 * bail to the real handler if breakFlags==0. 13730 */ 13731 lbu a3, offThread_breakFlags(rSELF) 13732 la rBIX, dvmAsmInstructionStart + (60 * 128) 13733 lw rIBASE, offThread_curHandlerTable(rSELF) 13734 bnez a3, 1f 13735 jr rBIX # nothing to do - jump to real handler 13736 1: 13737 EXPORT_PC() 13738 move a0, rPC # arg0 13739 move a1, rFP # arg1 13740 move a2, rSELF # arg2 13741 JAL(dvmCheckBefore) 13742 jr rBIX 13743 13744 /* ------------------------------ */ 13745 .balign 128 13746 .L_ALT_OP_IF_LEZ: /* 0x3d */ 13747 /* File: mips/alt_stub.S */ 13748 /* 13749 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13750 * any interesting requests and then jump to the real instruction 13751 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13752 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13753 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13754 * bail to the real handler if breakFlags==0. 13755 */ 13756 lbu a3, offThread_breakFlags(rSELF) 13757 la rBIX, dvmAsmInstructionStart + (61 * 128) 13758 lw rIBASE, offThread_curHandlerTable(rSELF) 13759 bnez a3, 1f 13760 jr rBIX # nothing to do - jump to real handler 13761 1: 13762 EXPORT_PC() 13763 move a0, rPC # arg0 13764 move a1, rFP # arg1 13765 move a2, rSELF # arg2 13766 JAL(dvmCheckBefore) 13767 jr rBIX 13768 13769 /* ------------------------------ */ 13770 .balign 128 13771 .L_ALT_OP_UNUSED_3E: /* 0x3e */ 13772 /* File: mips/alt_stub.S */ 13773 /* 13774 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13775 * any interesting requests and then jump to the real instruction 13776 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13777 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13778 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13779 * bail to the real handler if breakFlags==0. 13780 */ 13781 lbu a3, offThread_breakFlags(rSELF) 13782 la rBIX, dvmAsmInstructionStart + (62 * 128) 13783 lw rIBASE, offThread_curHandlerTable(rSELF) 13784 bnez a3, 1f 13785 jr rBIX # nothing to do - jump to real handler 13786 1: 13787 EXPORT_PC() 13788 move a0, rPC # arg0 13789 move a1, rFP # arg1 13790 move a2, rSELF # arg2 13791 JAL(dvmCheckBefore) 13792 jr rBIX 13793 13794 /* ------------------------------ */ 13795 .balign 128 13796 .L_ALT_OP_UNUSED_3F: /* 0x3f */ 13797 /* File: mips/alt_stub.S */ 13798 /* 13799 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13800 * any interesting requests and then jump to the real instruction 13801 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13802 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13803 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13804 * bail to the real handler if breakFlags==0. 13805 */ 13806 lbu a3, offThread_breakFlags(rSELF) 13807 la rBIX, dvmAsmInstructionStart + (63 * 128) 13808 lw rIBASE, offThread_curHandlerTable(rSELF) 13809 bnez a3, 1f 13810 jr rBIX # nothing to do - jump to real handler 13811 1: 13812 EXPORT_PC() 13813 move a0, rPC # arg0 13814 move a1, rFP # arg1 13815 move a2, rSELF # arg2 13816 JAL(dvmCheckBefore) 13817 jr rBIX 13818 13819 /* ------------------------------ */ 13820 .balign 128 13821 .L_ALT_OP_UNUSED_40: /* 0x40 */ 13822 /* File: mips/alt_stub.S */ 13823 /* 13824 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13825 * any interesting requests and then jump to the real instruction 13826 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13827 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13828 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13829 * bail to the real handler if breakFlags==0. 13830 */ 13831 lbu a3, offThread_breakFlags(rSELF) 13832 la rBIX, dvmAsmInstructionStart + (64 * 128) 13833 lw rIBASE, offThread_curHandlerTable(rSELF) 13834 bnez a3, 1f 13835 jr rBIX # nothing to do - jump to real handler 13836 1: 13837 EXPORT_PC() 13838 move a0, rPC # arg0 13839 move a1, rFP # arg1 13840 move a2, rSELF # arg2 13841 JAL(dvmCheckBefore) 13842 jr rBIX 13843 13844 /* ------------------------------ */ 13845 .balign 128 13846 .L_ALT_OP_UNUSED_41: /* 0x41 */ 13847 /* File: mips/alt_stub.S */ 13848 /* 13849 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13850 * any interesting requests and then jump to the real instruction 13851 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13852 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13853 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13854 * bail to the real handler if breakFlags==0. 13855 */ 13856 lbu a3, offThread_breakFlags(rSELF) 13857 la rBIX, dvmAsmInstructionStart + (65 * 128) 13858 lw rIBASE, offThread_curHandlerTable(rSELF) 13859 bnez a3, 1f 13860 jr rBIX # nothing to do - jump to real handler 13861 1: 13862 EXPORT_PC() 13863 move a0, rPC # arg0 13864 move a1, rFP # arg1 13865 move a2, rSELF # arg2 13866 JAL(dvmCheckBefore) 13867 jr rBIX 13868 13869 /* ------------------------------ */ 13870 .balign 128 13871 .L_ALT_OP_UNUSED_42: /* 0x42 */ 13872 /* File: mips/alt_stub.S */ 13873 /* 13874 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13875 * any interesting requests and then jump to the real instruction 13876 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13877 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13878 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13879 * bail to the real handler if breakFlags==0. 13880 */ 13881 lbu a3, offThread_breakFlags(rSELF) 13882 la rBIX, dvmAsmInstructionStart + (66 * 128) 13883 lw rIBASE, offThread_curHandlerTable(rSELF) 13884 bnez a3, 1f 13885 jr rBIX # nothing to do - jump to real handler 13886 1: 13887 EXPORT_PC() 13888 move a0, rPC # arg0 13889 move a1, rFP # arg1 13890 move a2, rSELF # arg2 13891 JAL(dvmCheckBefore) 13892 jr rBIX 13893 13894 /* ------------------------------ */ 13895 .balign 128 13896 .L_ALT_OP_UNUSED_43: /* 0x43 */ 13897 /* File: mips/alt_stub.S */ 13898 /* 13899 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13900 * any interesting requests and then jump to the real instruction 13901 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13902 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13903 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13904 * bail to the real handler if breakFlags==0. 13905 */ 13906 lbu a3, offThread_breakFlags(rSELF) 13907 la rBIX, dvmAsmInstructionStart + (67 * 128) 13908 lw rIBASE, offThread_curHandlerTable(rSELF) 13909 bnez a3, 1f 13910 jr rBIX # nothing to do - jump to real handler 13911 1: 13912 EXPORT_PC() 13913 move a0, rPC # arg0 13914 move a1, rFP # arg1 13915 move a2, rSELF # arg2 13916 JAL(dvmCheckBefore) 13917 jr rBIX 13918 13919 /* ------------------------------ */ 13920 .balign 128 13921 .L_ALT_OP_AGET: /* 0x44 */ 13922 /* File: mips/alt_stub.S */ 13923 /* 13924 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13925 * any interesting requests and then jump to the real instruction 13926 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13927 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13928 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13929 * bail to the real handler if breakFlags==0. 13930 */ 13931 lbu a3, offThread_breakFlags(rSELF) 13932 la rBIX, dvmAsmInstructionStart + (68 * 128) 13933 lw rIBASE, offThread_curHandlerTable(rSELF) 13934 bnez a3, 1f 13935 jr rBIX # nothing to do - jump to real handler 13936 1: 13937 EXPORT_PC() 13938 move a0, rPC # arg0 13939 move a1, rFP # arg1 13940 move a2, rSELF # arg2 13941 JAL(dvmCheckBefore) 13942 jr rBIX 13943 13944 /* ------------------------------ */ 13945 .balign 128 13946 .L_ALT_OP_AGET_WIDE: /* 0x45 */ 13947 /* File: mips/alt_stub.S */ 13948 /* 13949 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13950 * any interesting requests and then jump to the real instruction 13951 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13952 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13953 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13954 * bail to the real handler if breakFlags==0. 13955 */ 13956 lbu a3, offThread_breakFlags(rSELF) 13957 la rBIX, dvmAsmInstructionStart + (69 * 128) 13958 lw rIBASE, offThread_curHandlerTable(rSELF) 13959 bnez a3, 1f 13960 jr rBIX # nothing to do - jump to real handler 13961 1: 13962 EXPORT_PC() 13963 move a0, rPC # arg0 13964 move a1, rFP # arg1 13965 move a2, rSELF # arg2 13966 JAL(dvmCheckBefore) 13967 jr rBIX 13968 13969 /* ------------------------------ */ 13970 .balign 128 13971 .L_ALT_OP_AGET_OBJECT: /* 0x46 */ 13972 /* File: mips/alt_stub.S */ 13973 /* 13974 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 13975 * any interesting requests and then jump to the real instruction 13976 * handler. Note that the call to dvmCheckBefore is done as a tail call. 13977 * rIBASE updates won't be seen until a refresh, and we can tell we have a 13978 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 13979 * bail to the real handler if breakFlags==0. 13980 */ 13981 lbu a3, offThread_breakFlags(rSELF) 13982 la rBIX, dvmAsmInstructionStart + (70 * 128) 13983 lw rIBASE, offThread_curHandlerTable(rSELF) 13984 bnez a3, 1f 13985 jr rBIX # nothing to do - jump to real handler 13986 1: 13987 EXPORT_PC() 13988 move a0, rPC # arg0 13989 move a1, rFP # arg1 13990 move a2, rSELF # arg2 13991 JAL(dvmCheckBefore) 13992 jr rBIX 13993 13994 /* ------------------------------ */ 13995 .balign 128 13996 .L_ALT_OP_AGET_BOOLEAN: /* 0x47 */ 13997 /* File: mips/alt_stub.S */ 13998 /* 13999 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14000 * any interesting requests and then jump to the real instruction 14001 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14002 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14003 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14004 * bail to the real handler if breakFlags==0. 14005 */ 14006 lbu a3, offThread_breakFlags(rSELF) 14007 la rBIX, dvmAsmInstructionStart + (71 * 128) 14008 lw rIBASE, offThread_curHandlerTable(rSELF) 14009 bnez a3, 1f 14010 jr rBIX # nothing to do - jump to real handler 14011 1: 14012 EXPORT_PC() 14013 move a0, rPC # arg0 14014 move a1, rFP # arg1 14015 move a2, rSELF # arg2 14016 JAL(dvmCheckBefore) 14017 jr rBIX 14018 14019 /* ------------------------------ */ 14020 .balign 128 14021 .L_ALT_OP_AGET_BYTE: /* 0x48 */ 14022 /* File: mips/alt_stub.S */ 14023 /* 14024 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14025 * any interesting requests and then jump to the real instruction 14026 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14027 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14028 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14029 * bail to the real handler if breakFlags==0. 14030 */ 14031 lbu a3, offThread_breakFlags(rSELF) 14032 la rBIX, dvmAsmInstructionStart + (72 * 128) 14033 lw rIBASE, offThread_curHandlerTable(rSELF) 14034 bnez a3, 1f 14035 jr rBIX # nothing to do - jump to real handler 14036 1: 14037 EXPORT_PC() 14038 move a0, rPC # arg0 14039 move a1, rFP # arg1 14040 move a2, rSELF # arg2 14041 JAL(dvmCheckBefore) 14042 jr rBIX 14043 14044 /* ------------------------------ */ 14045 .balign 128 14046 .L_ALT_OP_AGET_CHAR: /* 0x49 */ 14047 /* File: mips/alt_stub.S */ 14048 /* 14049 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14050 * any interesting requests and then jump to the real instruction 14051 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14052 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14053 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14054 * bail to the real handler if breakFlags==0. 14055 */ 14056 lbu a3, offThread_breakFlags(rSELF) 14057 la rBIX, dvmAsmInstructionStart + (73 * 128) 14058 lw rIBASE, offThread_curHandlerTable(rSELF) 14059 bnez a3, 1f 14060 jr rBIX # nothing to do - jump to real handler 14061 1: 14062 EXPORT_PC() 14063 move a0, rPC # arg0 14064 move a1, rFP # arg1 14065 move a2, rSELF # arg2 14066 JAL(dvmCheckBefore) 14067 jr rBIX 14068 14069 /* ------------------------------ */ 14070 .balign 128 14071 .L_ALT_OP_AGET_SHORT: /* 0x4a */ 14072 /* File: mips/alt_stub.S */ 14073 /* 14074 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14075 * any interesting requests and then jump to the real instruction 14076 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14077 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14078 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14079 * bail to the real handler if breakFlags==0. 14080 */ 14081 lbu a3, offThread_breakFlags(rSELF) 14082 la rBIX, dvmAsmInstructionStart + (74 * 128) 14083 lw rIBASE, offThread_curHandlerTable(rSELF) 14084 bnez a3, 1f 14085 jr rBIX # nothing to do - jump to real handler 14086 1: 14087 EXPORT_PC() 14088 move a0, rPC # arg0 14089 move a1, rFP # arg1 14090 move a2, rSELF # arg2 14091 JAL(dvmCheckBefore) 14092 jr rBIX 14093 14094 /* ------------------------------ */ 14095 .balign 128 14096 .L_ALT_OP_APUT: /* 0x4b */ 14097 /* File: mips/alt_stub.S */ 14098 /* 14099 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14100 * any interesting requests and then jump to the real instruction 14101 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14102 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14103 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14104 * bail to the real handler if breakFlags==0. 14105 */ 14106 lbu a3, offThread_breakFlags(rSELF) 14107 la rBIX, dvmAsmInstructionStart + (75 * 128) 14108 lw rIBASE, offThread_curHandlerTable(rSELF) 14109 bnez a3, 1f 14110 jr rBIX # nothing to do - jump to real handler 14111 1: 14112 EXPORT_PC() 14113 move a0, rPC # arg0 14114 move a1, rFP # arg1 14115 move a2, rSELF # arg2 14116 JAL(dvmCheckBefore) 14117 jr rBIX 14118 14119 /* ------------------------------ */ 14120 .balign 128 14121 .L_ALT_OP_APUT_WIDE: /* 0x4c */ 14122 /* File: mips/alt_stub.S */ 14123 /* 14124 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14125 * any interesting requests and then jump to the real instruction 14126 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14127 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14128 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14129 * bail to the real handler if breakFlags==0. 14130 */ 14131 lbu a3, offThread_breakFlags(rSELF) 14132 la rBIX, dvmAsmInstructionStart + (76 * 128) 14133 lw rIBASE, offThread_curHandlerTable(rSELF) 14134 bnez a3, 1f 14135 jr rBIX # nothing to do - jump to real handler 14136 1: 14137 EXPORT_PC() 14138 move a0, rPC # arg0 14139 move a1, rFP # arg1 14140 move a2, rSELF # arg2 14141 JAL(dvmCheckBefore) 14142 jr rBIX 14143 14144 /* ------------------------------ */ 14145 .balign 128 14146 .L_ALT_OP_APUT_OBJECT: /* 0x4d */ 14147 /* File: mips/alt_stub.S */ 14148 /* 14149 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14150 * any interesting requests and then jump to the real instruction 14151 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14152 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14153 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14154 * bail to the real handler if breakFlags==0. 14155 */ 14156 lbu a3, offThread_breakFlags(rSELF) 14157 la rBIX, dvmAsmInstructionStart + (77 * 128) 14158 lw rIBASE, offThread_curHandlerTable(rSELF) 14159 bnez a3, 1f 14160 jr rBIX # nothing to do - jump to real handler 14161 1: 14162 EXPORT_PC() 14163 move a0, rPC # arg0 14164 move a1, rFP # arg1 14165 move a2, rSELF # arg2 14166 JAL(dvmCheckBefore) 14167 jr rBIX 14168 14169 /* ------------------------------ */ 14170 .balign 128 14171 .L_ALT_OP_APUT_BOOLEAN: /* 0x4e */ 14172 /* File: mips/alt_stub.S */ 14173 /* 14174 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14175 * any interesting requests and then jump to the real instruction 14176 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14177 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14178 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14179 * bail to the real handler if breakFlags==0. 14180 */ 14181 lbu a3, offThread_breakFlags(rSELF) 14182 la rBIX, dvmAsmInstructionStart + (78 * 128) 14183 lw rIBASE, offThread_curHandlerTable(rSELF) 14184 bnez a3, 1f 14185 jr rBIX # nothing to do - jump to real handler 14186 1: 14187 EXPORT_PC() 14188 move a0, rPC # arg0 14189 move a1, rFP # arg1 14190 move a2, rSELF # arg2 14191 JAL(dvmCheckBefore) 14192 jr rBIX 14193 14194 /* ------------------------------ */ 14195 .balign 128 14196 .L_ALT_OP_APUT_BYTE: /* 0x4f */ 14197 /* File: mips/alt_stub.S */ 14198 /* 14199 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14200 * any interesting requests and then jump to the real instruction 14201 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14202 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14203 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14204 * bail to the real handler if breakFlags==0. 14205 */ 14206 lbu a3, offThread_breakFlags(rSELF) 14207 la rBIX, dvmAsmInstructionStart + (79 * 128) 14208 lw rIBASE, offThread_curHandlerTable(rSELF) 14209 bnez a3, 1f 14210 jr rBIX # nothing to do - jump to real handler 14211 1: 14212 EXPORT_PC() 14213 move a0, rPC # arg0 14214 move a1, rFP # arg1 14215 move a2, rSELF # arg2 14216 JAL(dvmCheckBefore) 14217 jr rBIX 14218 14219 /* ------------------------------ */ 14220 .balign 128 14221 .L_ALT_OP_APUT_CHAR: /* 0x50 */ 14222 /* File: mips/alt_stub.S */ 14223 /* 14224 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14225 * any interesting requests and then jump to the real instruction 14226 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14227 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14228 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14229 * bail to the real handler if breakFlags==0. 14230 */ 14231 lbu a3, offThread_breakFlags(rSELF) 14232 la rBIX, dvmAsmInstructionStart + (80 * 128) 14233 lw rIBASE, offThread_curHandlerTable(rSELF) 14234 bnez a3, 1f 14235 jr rBIX # nothing to do - jump to real handler 14236 1: 14237 EXPORT_PC() 14238 move a0, rPC # arg0 14239 move a1, rFP # arg1 14240 move a2, rSELF # arg2 14241 JAL(dvmCheckBefore) 14242 jr rBIX 14243 14244 /* ------------------------------ */ 14245 .balign 128 14246 .L_ALT_OP_APUT_SHORT: /* 0x51 */ 14247 /* File: mips/alt_stub.S */ 14248 /* 14249 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14250 * any interesting requests and then jump to the real instruction 14251 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14252 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14253 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14254 * bail to the real handler if breakFlags==0. 14255 */ 14256 lbu a3, offThread_breakFlags(rSELF) 14257 la rBIX, dvmAsmInstructionStart + (81 * 128) 14258 lw rIBASE, offThread_curHandlerTable(rSELF) 14259 bnez a3, 1f 14260 jr rBIX # nothing to do - jump to real handler 14261 1: 14262 EXPORT_PC() 14263 move a0, rPC # arg0 14264 move a1, rFP # arg1 14265 move a2, rSELF # arg2 14266 JAL(dvmCheckBefore) 14267 jr rBIX 14268 14269 /* ------------------------------ */ 14270 .balign 128 14271 .L_ALT_OP_IGET: /* 0x52 */ 14272 /* File: mips/alt_stub.S */ 14273 /* 14274 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14275 * any interesting requests and then jump to the real instruction 14276 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14277 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14278 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14279 * bail to the real handler if breakFlags==0. 14280 */ 14281 lbu a3, offThread_breakFlags(rSELF) 14282 la rBIX, dvmAsmInstructionStart + (82 * 128) 14283 lw rIBASE, offThread_curHandlerTable(rSELF) 14284 bnez a3, 1f 14285 jr rBIX # nothing to do - jump to real handler 14286 1: 14287 EXPORT_PC() 14288 move a0, rPC # arg0 14289 move a1, rFP # arg1 14290 move a2, rSELF # arg2 14291 JAL(dvmCheckBefore) 14292 jr rBIX 14293 14294 /* ------------------------------ */ 14295 .balign 128 14296 .L_ALT_OP_IGET_WIDE: /* 0x53 */ 14297 /* File: mips/alt_stub.S */ 14298 /* 14299 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14300 * any interesting requests and then jump to the real instruction 14301 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14302 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14303 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14304 * bail to the real handler if breakFlags==0. 14305 */ 14306 lbu a3, offThread_breakFlags(rSELF) 14307 la rBIX, dvmAsmInstructionStart + (83 * 128) 14308 lw rIBASE, offThread_curHandlerTable(rSELF) 14309 bnez a3, 1f 14310 jr rBIX # nothing to do - jump to real handler 14311 1: 14312 EXPORT_PC() 14313 move a0, rPC # arg0 14314 move a1, rFP # arg1 14315 move a2, rSELF # arg2 14316 JAL(dvmCheckBefore) 14317 jr rBIX 14318 14319 /* ------------------------------ */ 14320 .balign 128 14321 .L_ALT_OP_IGET_OBJECT: /* 0x54 */ 14322 /* File: mips/alt_stub.S */ 14323 /* 14324 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14325 * any interesting requests and then jump to the real instruction 14326 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14327 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14328 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14329 * bail to the real handler if breakFlags==0. 14330 */ 14331 lbu a3, offThread_breakFlags(rSELF) 14332 la rBIX, dvmAsmInstructionStart + (84 * 128) 14333 lw rIBASE, offThread_curHandlerTable(rSELF) 14334 bnez a3, 1f 14335 jr rBIX # nothing to do - jump to real handler 14336 1: 14337 EXPORT_PC() 14338 move a0, rPC # arg0 14339 move a1, rFP # arg1 14340 move a2, rSELF # arg2 14341 JAL(dvmCheckBefore) 14342 jr rBIX 14343 14344 /* ------------------------------ */ 14345 .balign 128 14346 .L_ALT_OP_IGET_BOOLEAN: /* 0x55 */ 14347 /* File: mips/alt_stub.S */ 14348 /* 14349 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14350 * any interesting requests and then jump to the real instruction 14351 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14352 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14353 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14354 * bail to the real handler if breakFlags==0. 14355 */ 14356 lbu a3, offThread_breakFlags(rSELF) 14357 la rBIX, dvmAsmInstructionStart + (85 * 128) 14358 lw rIBASE, offThread_curHandlerTable(rSELF) 14359 bnez a3, 1f 14360 jr rBIX # nothing to do - jump to real handler 14361 1: 14362 EXPORT_PC() 14363 move a0, rPC # arg0 14364 move a1, rFP # arg1 14365 move a2, rSELF # arg2 14366 JAL(dvmCheckBefore) 14367 jr rBIX 14368 14369 /* ------------------------------ */ 14370 .balign 128 14371 .L_ALT_OP_IGET_BYTE: /* 0x56 */ 14372 /* File: mips/alt_stub.S */ 14373 /* 14374 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14375 * any interesting requests and then jump to the real instruction 14376 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14377 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14378 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14379 * bail to the real handler if breakFlags==0. 14380 */ 14381 lbu a3, offThread_breakFlags(rSELF) 14382 la rBIX, dvmAsmInstructionStart + (86 * 128) 14383 lw rIBASE, offThread_curHandlerTable(rSELF) 14384 bnez a3, 1f 14385 jr rBIX # nothing to do - jump to real handler 14386 1: 14387 EXPORT_PC() 14388 move a0, rPC # arg0 14389 move a1, rFP # arg1 14390 move a2, rSELF # arg2 14391 JAL(dvmCheckBefore) 14392 jr rBIX 14393 14394 /* ------------------------------ */ 14395 .balign 128 14396 .L_ALT_OP_IGET_CHAR: /* 0x57 */ 14397 /* File: mips/alt_stub.S */ 14398 /* 14399 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14400 * any interesting requests and then jump to the real instruction 14401 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14402 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14403 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14404 * bail to the real handler if breakFlags==0. 14405 */ 14406 lbu a3, offThread_breakFlags(rSELF) 14407 la rBIX, dvmAsmInstructionStart + (87 * 128) 14408 lw rIBASE, offThread_curHandlerTable(rSELF) 14409 bnez a3, 1f 14410 jr rBIX # nothing to do - jump to real handler 14411 1: 14412 EXPORT_PC() 14413 move a0, rPC # arg0 14414 move a1, rFP # arg1 14415 move a2, rSELF # arg2 14416 JAL(dvmCheckBefore) 14417 jr rBIX 14418 14419 /* ------------------------------ */ 14420 .balign 128 14421 .L_ALT_OP_IGET_SHORT: /* 0x58 */ 14422 /* File: mips/alt_stub.S */ 14423 /* 14424 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14425 * any interesting requests and then jump to the real instruction 14426 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14427 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14428 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14429 * bail to the real handler if breakFlags==0. 14430 */ 14431 lbu a3, offThread_breakFlags(rSELF) 14432 la rBIX, dvmAsmInstructionStart + (88 * 128) 14433 lw rIBASE, offThread_curHandlerTable(rSELF) 14434 bnez a3, 1f 14435 jr rBIX # nothing to do - jump to real handler 14436 1: 14437 EXPORT_PC() 14438 move a0, rPC # arg0 14439 move a1, rFP # arg1 14440 move a2, rSELF # arg2 14441 JAL(dvmCheckBefore) 14442 jr rBIX 14443 14444 /* ------------------------------ */ 14445 .balign 128 14446 .L_ALT_OP_IPUT: /* 0x59 */ 14447 /* File: mips/alt_stub.S */ 14448 /* 14449 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14450 * any interesting requests and then jump to the real instruction 14451 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14452 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14453 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14454 * bail to the real handler if breakFlags==0. 14455 */ 14456 lbu a3, offThread_breakFlags(rSELF) 14457 la rBIX, dvmAsmInstructionStart + (89 * 128) 14458 lw rIBASE, offThread_curHandlerTable(rSELF) 14459 bnez a3, 1f 14460 jr rBIX # nothing to do - jump to real handler 14461 1: 14462 EXPORT_PC() 14463 move a0, rPC # arg0 14464 move a1, rFP # arg1 14465 move a2, rSELF # arg2 14466 JAL(dvmCheckBefore) 14467 jr rBIX 14468 14469 /* ------------------------------ */ 14470 .balign 128 14471 .L_ALT_OP_IPUT_WIDE: /* 0x5a */ 14472 /* File: mips/alt_stub.S */ 14473 /* 14474 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14475 * any interesting requests and then jump to the real instruction 14476 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14477 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14478 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14479 * bail to the real handler if breakFlags==0. 14480 */ 14481 lbu a3, offThread_breakFlags(rSELF) 14482 la rBIX, dvmAsmInstructionStart + (90 * 128) 14483 lw rIBASE, offThread_curHandlerTable(rSELF) 14484 bnez a3, 1f 14485 jr rBIX # nothing to do - jump to real handler 14486 1: 14487 EXPORT_PC() 14488 move a0, rPC # arg0 14489 move a1, rFP # arg1 14490 move a2, rSELF # arg2 14491 JAL(dvmCheckBefore) 14492 jr rBIX 14493 14494 /* ------------------------------ */ 14495 .balign 128 14496 .L_ALT_OP_IPUT_OBJECT: /* 0x5b */ 14497 /* File: mips/alt_stub.S */ 14498 /* 14499 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14500 * any interesting requests and then jump to the real instruction 14501 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14502 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14503 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14504 * bail to the real handler if breakFlags==0. 14505 */ 14506 lbu a3, offThread_breakFlags(rSELF) 14507 la rBIX, dvmAsmInstructionStart + (91 * 128) 14508 lw rIBASE, offThread_curHandlerTable(rSELF) 14509 bnez a3, 1f 14510 jr rBIX # nothing to do - jump to real handler 14511 1: 14512 EXPORT_PC() 14513 move a0, rPC # arg0 14514 move a1, rFP # arg1 14515 move a2, rSELF # arg2 14516 JAL(dvmCheckBefore) 14517 jr rBIX 14518 14519 /* ------------------------------ */ 14520 .balign 128 14521 .L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */ 14522 /* File: mips/alt_stub.S */ 14523 /* 14524 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14525 * any interesting requests and then jump to the real instruction 14526 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14527 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14528 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14529 * bail to the real handler if breakFlags==0. 14530 */ 14531 lbu a3, offThread_breakFlags(rSELF) 14532 la rBIX, dvmAsmInstructionStart + (92 * 128) 14533 lw rIBASE, offThread_curHandlerTable(rSELF) 14534 bnez a3, 1f 14535 jr rBIX # nothing to do - jump to real handler 14536 1: 14537 EXPORT_PC() 14538 move a0, rPC # arg0 14539 move a1, rFP # arg1 14540 move a2, rSELF # arg2 14541 JAL(dvmCheckBefore) 14542 jr rBIX 14543 14544 /* ------------------------------ */ 14545 .balign 128 14546 .L_ALT_OP_IPUT_BYTE: /* 0x5d */ 14547 /* File: mips/alt_stub.S */ 14548 /* 14549 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14550 * any interesting requests and then jump to the real instruction 14551 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14552 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14553 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14554 * bail to the real handler if breakFlags==0. 14555 */ 14556 lbu a3, offThread_breakFlags(rSELF) 14557 la rBIX, dvmAsmInstructionStart + (93 * 128) 14558 lw rIBASE, offThread_curHandlerTable(rSELF) 14559 bnez a3, 1f 14560 jr rBIX # nothing to do - jump to real handler 14561 1: 14562 EXPORT_PC() 14563 move a0, rPC # arg0 14564 move a1, rFP # arg1 14565 move a2, rSELF # arg2 14566 JAL(dvmCheckBefore) 14567 jr rBIX 14568 14569 /* ------------------------------ */ 14570 .balign 128 14571 .L_ALT_OP_IPUT_CHAR: /* 0x5e */ 14572 /* File: mips/alt_stub.S */ 14573 /* 14574 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14575 * any interesting requests and then jump to the real instruction 14576 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14577 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14578 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14579 * bail to the real handler if breakFlags==0. 14580 */ 14581 lbu a3, offThread_breakFlags(rSELF) 14582 la rBIX, dvmAsmInstructionStart + (94 * 128) 14583 lw rIBASE, offThread_curHandlerTable(rSELF) 14584 bnez a3, 1f 14585 jr rBIX # nothing to do - jump to real handler 14586 1: 14587 EXPORT_PC() 14588 move a0, rPC # arg0 14589 move a1, rFP # arg1 14590 move a2, rSELF # arg2 14591 JAL(dvmCheckBefore) 14592 jr rBIX 14593 14594 /* ------------------------------ */ 14595 .balign 128 14596 .L_ALT_OP_IPUT_SHORT: /* 0x5f */ 14597 /* File: mips/alt_stub.S */ 14598 /* 14599 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14600 * any interesting requests and then jump to the real instruction 14601 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14602 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14603 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14604 * bail to the real handler if breakFlags==0. 14605 */ 14606 lbu a3, offThread_breakFlags(rSELF) 14607 la rBIX, dvmAsmInstructionStart + (95 * 128) 14608 lw rIBASE, offThread_curHandlerTable(rSELF) 14609 bnez a3, 1f 14610 jr rBIX # nothing to do - jump to real handler 14611 1: 14612 EXPORT_PC() 14613 move a0, rPC # arg0 14614 move a1, rFP # arg1 14615 move a2, rSELF # arg2 14616 JAL(dvmCheckBefore) 14617 jr rBIX 14618 14619 /* ------------------------------ */ 14620 .balign 128 14621 .L_ALT_OP_SGET: /* 0x60 */ 14622 /* File: mips/alt_stub.S */ 14623 /* 14624 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14625 * any interesting requests and then jump to the real instruction 14626 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14627 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14628 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14629 * bail to the real handler if breakFlags==0. 14630 */ 14631 lbu a3, offThread_breakFlags(rSELF) 14632 la rBIX, dvmAsmInstructionStart + (96 * 128) 14633 lw rIBASE, offThread_curHandlerTable(rSELF) 14634 bnez a3, 1f 14635 jr rBIX # nothing to do - jump to real handler 14636 1: 14637 EXPORT_PC() 14638 move a0, rPC # arg0 14639 move a1, rFP # arg1 14640 move a2, rSELF # arg2 14641 JAL(dvmCheckBefore) 14642 jr rBIX 14643 14644 /* ------------------------------ */ 14645 .balign 128 14646 .L_ALT_OP_SGET_WIDE: /* 0x61 */ 14647 /* File: mips/alt_stub.S */ 14648 /* 14649 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14650 * any interesting requests and then jump to the real instruction 14651 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14652 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14653 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14654 * bail to the real handler if breakFlags==0. 14655 */ 14656 lbu a3, offThread_breakFlags(rSELF) 14657 la rBIX, dvmAsmInstructionStart + (97 * 128) 14658 lw rIBASE, offThread_curHandlerTable(rSELF) 14659 bnez a3, 1f 14660 jr rBIX # nothing to do - jump to real handler 14661 1: 14662 EXPORT_PC() 14663 move a0, rPC # arg0 14664 move a1, rFP # arg1 14665 move a2, rSELF # arg2 14666 JAL(dvmCheckBefore) 14667 jr rBIX 14668 14669 /* ------------------------------ */ 14670 .balign 128 14671 .L_ALT_OP_SGET_OBJECT: /* 0x62 */ 14672 /* File: mips/alt_stub.S */ 14673 /* 14674 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14675 * any interesting requests and then jump to the real instruction 14676 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14677 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14678 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14679 * bail to the real handler if breakFlags==0. 14680 */ 14681 lbu a3, offThread_breakFlags(rSELF) 14682 la rBIX, dvmAsmInstructionStart + (98 * 128) 14683 lw rIBASE, offThread_curHandlerTable(rSELF) 14684 bnez a3, 1f 14685 jr rBIX # nothing to do - jump to real handler 14686 1: 14687 EXPORT_PC() 14688 move a0, rPC # arg0 14689 move a1, rFP # arg1 14690 move a2, rSELF # arg2 14691 JAL(dvmCheckBefore) 14692 jr rBIX 14693 14694 /* ------------------------------ */ 14695 .balign 128 14696 .L_ALT_OP_SGET_BOOLEAN: /* 0x63 */ 14697 /* File: mips/alt_stub.S */ 14698 /* 14699 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14700 * any interesting requests and then jump to the real instruction 14701 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14702 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14703 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14704 * bail to the real handler if breakFlags==0. 14705 */ 14706 lbu a3, offThread_breakFlags(rSELF) 14707 la rBIX, dvmAsmInstructionStart + (99 * 128) 14708 lw rIBASE, offThread_curHandlerTable(rSELF) 14709 bnez a3, 1f 14710 jr rBIX # nothing to do - jump to real handler 14711 1: 14712 EXPORT_PC() 14713 move a0, rPC # arg0 14714 move a1, rFP # arg1 14715 move a2, rSELF # arg2 14716 JAL(dvmCheckBefore) 14717 jr rBIX 14718 14719 /* ------------------------------ */ 14720 .balign 128 14721 .L_ALT_OP_SGET_BYTE: /* 0x64 */ 14722 /* File: mips/alt_stub.S */ 14723 /* 14724 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14725 * any interesting requests and then jump to the real instruction 14726 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14727 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14728 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14729 * bail to the real handler if breakFlags==0. 14730 */ 14731 lbu a3, offThread_breakFlags(rSELF) 14732 la rBIX, dvmAsmInstructionStart + (100 * 128) 14733 lw rIBASE, offThread_curHandlerTable(rSELF) 14734 bnez a3, 1f 14735 jr rBIX # nothing to do - jump to real handler 14736 1: 14737 EXPORT_PC() 14738 move a0, rPC # arg0 14739 move a1, rFP # arg1 14740 move a2, rSELF # arg2 14741 JAL(dvmCheckBefore) 14742 jr rBIX 14743 14744 /* ------------------------------ */ 14745 .balign 128 14746 .L_ALT_OP_SGET_CHAR: /* 0x65 */ 14747 /* File: mips/alt_stub.S */ 14748 /* 14749 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14750 * any interesting requests and then jump to the real instruction 14751 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14752 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14753 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14754 * bail to the real handler if breakFlags==0. 14755 */ 14756 lbu a3, offThread_breakFlags(rSELF) 14757 la rBIX, dvmAsmInstructionStart + (101 * 128) 14758 lw rIBASE, offThread_curHandlerTable(rSELF) 14759 bnez a3, 1f 14760 jr rBIX # nothing to do - jump to real handler 14761 1: 14762 EXPORT_PC() 14763 move a0, rPC # arg0 14764 move a1, rFP # arg1 14765 move a2, rSELF # arg2 14766 JAL(dvmCheckBefore) 14767 jr rBIX 14768 14769 /* ------------------------------ */ 14770 .balign 128 14771 .L_ALT_OP_SGET_SHORT: /* 0x66 */ 14772 /* File: mips/alt_stub.S */ 14773 /* 14774 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14775 * any interesting requests and then jump to the real instruction 14776 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14777 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14778 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14779 * bail to the real handler if breakFlags==0. 14780 */ 14781 lbu a3, offThread_breakFlags(rSELF) 14782 la rBIX, dvmAsmInstructionStart + (102 * 128) 14783 lw rIBASE, offThread_curHandlerTable(rSELF) 14784 bnez a3, 1f 14785 jr rBIX # nothing to do - jump to real handler 14786 1: 14787 EXPORT_PC() 14788 move a0, rPC # arg0 14789 move a1, rFP # arg1 14790 move a2, rSELF # arg2 14791 JAL(dvmCheckBefore) 14792 jr rBIX 14793 14794 /* ------------------------------ */ 14795 .balign 128 14796 .L_ALT_OP_SPUT: /* 0x67 */ 14797 /* File: mips/alt_stub.S */ 14798 /* 14799 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14800 * any interesting requests and then jump to the real instruction 14801 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14802 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14803 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14804 * bail to the real handler if breakFlags==0. 14805 */ 14806 lbu a3, offThread_breakFlags(rSELF) 14807 la rBIX, dvmAsmInstructionStart + (103 * 128) 14808 lw rIBASE, offThread_curHandlerTable(rSELF) 14809 bnez a3, 1f 14810 jr rBIX # nothing to do - jump to real handler 14811 1: 14812 EXPORT_PC() 14813 move a0, rPC # arg0 14814 move a1, rFP # arg1 14815 move a2, rSELF # arg2 14816 JAL(dvmCheckBefore) 14817 jr rBIX 14818 14819 /* ------------------------------ */ 14820 .balign 128 14821 .L_ALT_OP_SPUT_WIDE: /* 0x68 */ 14822 /* File: mips/alt_stub.S */ 14823 /* 14824 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14825 * any interesting requests and then jump to the real instruction 14826 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14827 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14828 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14829 * bail to the real handler if breakFlags==0. 14830 */ 14831 lbu a3, offThread_breakFlags(rSELF) 14832 la rBIX, dvmAsmInstructionStart + (104 * 128) 14833 lw rIBASE, offThread_curHandlerTable(rSELF) 14834 bnez a3, 1f 14835 jr rBIX # nothing to do - jump to real handler 14836 1: 14837 EXPORT_PC() 14838 move a0, rPC # arg0 14839 move a1, rFP # arg1 14840 move a2, rSELF # arg2 14841 JAL(dvmCheckBefore) 14842 jr rBIX 14843 14844 /* ------------------------------ */ 14845 .balign 128 14846 .L_ALT_OP_SPUT_OBJECT: /* 0x69 */ 14847 /* File: mips/alt_stub.S */ 14848 /* 14849 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14850 * any interesting requests and then jump to the real instruction 14851 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14852 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14853 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14854 * bail to the real handler if breakFlags==0. 14855 */ 14856 lbu a3, offThread_breakFlags(rSELF) 14857 la rBIX, dvmAsmInstructionStart + (105 * 128) 14858 lw rIBASE, offThread_curHandlerTable(rSELF) 14859 bnez a3, 1f 14860 jr rBIX # nothing to do - jump to real handler 14861 1: 14862 EXPORT_PC() 14863 move a0, rPC # arg0 14864 move a1, rFP # arg1 14865 move a2, rSELF # arg2 14866 JAL(dvmCheckBefore) 14867 jr rBIX 14868 14869 /* ------------------------------ */ 14870 .balign 128 14871 .L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */ 14872 /* File: mips/alt_stub.S */ 14873 /* 14874 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14875 * any interesting requests and then jump to the real instruction 14876 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14877 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14878 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14879 * bail to the real handler if breakFlags==0. 14880 */ 14881 lbu a3, offThread_breakFlags(rSELF) 14882 la rBIX, dvmAsmInstructionStart + (106 * 128) 14883 lw rIBASE, offThread_curHandlerTable(rSELF) 14884 bnez a3, 1f 14885 jr rBIX # nothing to do - jump to real handler 14886 1: 14887 EXPORT_PC() 14888 move a0, rPC # arg0 14889 move a1, rFP # arg1 14890 move a2, rSELF # arg2 14891 JAL(dvmCheckBefore) 14892 jr rBIX 14893 14894 /* ------------------------------ */ 14895 .balign 128 14896 .L_ALT_OP_SPUT_BYTE: /* 0x6b */ 14897 /* File: mips/alt_stub.S */ 14898 /* 14899 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14900 * any interesting requests and then jump to the real instruction 14901 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14902 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14903 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14904 * bail to the real handler if breakFlags==0. 14905 */ 14906 lbu a3, offThread_breakFlags(rSELF) 14907 la rBIX, dvmAsmInstructionStart + (107 * 128) 14908 lw rIBASE, offThread_curHandlerTable(rSELF) 14909 bnez a3, 1f 14910 jr rBIX # nothing to do - jump to real handler 14911 1: 14912 EXPORT_PC() 14913 move a0, rPC # arg0 14914 move a1, rFP # arg1 14915 move a2, rSELF # arg2 14916 JAL(dvmCheckBefore) 14917 jr rBIX 14918 14919 /* ------------------------------ */ 14920 .balign 128 14921 .L_ALT_OP_SPUT_CHAR: /* 0x6c */ 14922 /* File: mips/alt_stub.S */ 14923 /* 14924 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14925 * any interesting requests and then jump to the real instruction 14926 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14927 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14928 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14929 * bail to the real handler if breakFlags==0. 14930 */ 14931 lbu a3, offThread_breakFlags(rSELF) 14932 la rBIX, dvmAsmInstructionStart + (108 * 128) 14933 lw rIBASE, offThread_curHandlerTable(rSELF) 14934 bnez a3, 1f 14935 jr rBIX # nothing to do - jump to real handler 14936 1: 14937 EXPORT_PC() 14938 move a0, rPC # arg0 14939 move a1, rFP # arg1 14940 move a2, rSELF # arg2 14941 JAL(dvmCheckBefore) 14942 jr rBIX 14943 14944 /* ------------------------------ */ 14945 .balign 128 14946 .L_ALT_OP_SPUT_SHORT: /* 0x6d */ 14947 /* File: mips/alt_stub.S */ 14948 /* 14949 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14950 * any interesting requests and then jump to the real instruction 14951 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14952 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14953 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14954 * bail to the real handler if breakFlags==0. 14955 */ 14956 lbu a3, offThread_breakFlags(rSELF) 14957 la rBIX, dvmAsmInstructionStart + (109 * 128) 14958 lw rIBASE, offThread_curHandlerTable(rSELF) 14959 bnez a3, 1f 14960 jr rBIX # nothing to do - jump to real handler 14961 1: 14962 EXPORT_PC() 14963 move a0, rPC # arg0 14964 move a1, rFP # arg1 14965 move a2, rSELF # arg2 14966 JAL(dvmCheckBefore) 14967 jr rBIX 14968 14969 /* ------------------------------ */ 14970 .balign 128 14971 .L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */ 14972 /* File: mips/alt_stub.S */ 14973 /* 14974 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14975 * any interesting requests and then jump to the real instruction 14976 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14977 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14978 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14979 * bail to the real handler if breakFlags==0. 14980 */ 14981 lbu a3, offThread_breakFlags(rSELF) 14982 la rBIX, dvmAsmInstructionStart + (110 * 128) 14983 lw rIBASE, offThread_curHandlerTable(rSELF) 14984 bnez a3, 1f 14985 jr rBIX # nothing to do - jump to real handler 14986 1: 14987 EXPORT_PC() 14988 move a0, rPC # arg0 14989 move a1, rFP # arg1 14990 move a2, rSELF # arg2 14991 JAL(dvmCheckBefore) 14992 jr rBIX 14993 14994 /* ------------------------------ */ 14995 .balign 128 14996 .L_ALT_OP_INVOKE_SUPER: /* 0x6f */ 14997 /* File: mips/alt_stub.S */ 14998 /* 14999 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15000 * any interesting requests and then jump to the real instruction 15001 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15002 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15003 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15004 * bail to the real handler if breakFlags==0. 15005 */ 15006 lbu a3, offThread_breakFlags(rSELF) 15007 la rBIX, dvmAsmInstructionStart + (111 * 128) 15008 lw rIBASE, offThread_curHandlerTable(rSELF) 15009 bnez a3, 1f 15010 jr rBIX # nothing to do - jump to real handler 15011 1: 15012 EXPORT_PC() 15013 move a0, rPC # arg0 15014 move a1, rFP # arg1 15015 move a2, rSELF # arg2 15016 JAL(dvmCheckBefore) 15017 jr rBIX 15018 15019 /* ------------------------------ */ 15020 .balign 128 15021 .L_ALT_OP_INVOKE_DIRECT: /* 0x70 */ 15022 /* File: mips/alt_stub.S */ 15023 /* 15024 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15025 * any interesting requests and then jump to the real instruction 15026 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15027 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15028 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15029 * bail to the real handler if breakFlags==0. 15030 */ 15031 lbu a3, offThread_breakFlags(rSELF) 15032 la rBIX, dvmAsmInstructionStart + (112 * 128) 15033 lw rIBASE, offThread_curHandlerTable(rSELF) 15034 bnez a3, 1f 15035 jr rBIX # nothing to do - jump to real handler 15036 1: 15037 EXPORT_PC() 15038 move a0, rPC # arg0 15039 move a1, rFP # arg1 15040 move a2, rSELF # arg2 15041 JAL(dvmCheckBefore) 15042 jr rBIX 15043 15044 /* ------------------------------ */ 15045 .balign 128 15046 .L_ALT_OP_INVOKE_STATIC: /* 0x71 */ 15047 /* File: mips/alt_stub.S */ 15048 /* 15049 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15050 * any interesting requests and then jump to the real instruction 15051 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15052 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15053 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15054 * bail to the real handler if breakFlags==0. 15055 */ 15056 lbu a3, offThread_breakFlags(rSELF) 15057 la rBIX, dvmAsmInstructionStart + (113 * 128) 15058 lw rIBASE, offThread_curHandlerTable(rSELF) 15059 bnez a3, 1f 15060 jr rBIX # nothing to do - jump to real handler 15061 1: 15062 EXPORT_PC() 15063 move a0, rPC # arg0 15064 move a1, rFP # arg1 15065 move a2, rSELF # arg2 15066 JAL(dvmCheckBefore) 15067 jr rBIX 15068 15069 /* ------------------------------ */ 15070 .balign 128 15071 .L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */ 15072 /* File: mips/alt_stub.S */ 15073 /* 15074 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15075 * any interesting requests and then jump to the real instruction 15076 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15077 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15078 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15079 * bail to the real handler if breakFlags==0. 15080 */ 15081 lbu a3, offThread_breakFlags(rSELF) 15082 la rBIX, dvmAsmInstructionStart + (114 * 128) 15083 lw rIBASE, offThread_curHandlerTable(rSELF) 15084 bnez a3, 1f 15085 jr rBIX # nothing to do - jump to real handler 15086 1: 15087 EXPORT_PC() 15088 move a0, rPC # arg0 15089 move a1, rFP # arg1 15090 move a2, rSELF # arg2 15091 JAL(dvmCheckBefore) 15092 jr rBIX 15093 15094 /* ------------------------------ */ 15095 .balign 128 15096 .L_ALT_OP_UNUSED_73: /* 0x73 */ 15097 /* File: mips/alt_stub.S */ 15098 /* 15099 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15100 * any interesting requests and then jump to the real instruction 15101 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15102 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15103 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15104 * bail to the real handler if breakFlags==0. 15105 */ 15106 lbu a3, offThread_breakFlags(rSELF) 15107 la rBIX, dvmAsmInstructionStart + (115 * 128) 15108 lw rIBASE, offThread_curHandlerTable(rSELF) 15109 bnez a3, 1f 15110 jr rBIX # nothing to do - jump to real handler 15111 1: 15112 EXPORT_PC() 15113 move a0, rPC # arg0 15114 move a1, rFP # arg1 15115 move a2, rSELF # arg2 15116 JAL(dvmCheckBefore) 15117 jr rBIX 15118 15119 /* ------------------------------ */ 15120 .balign 128 15121 .L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 15122 /* File: mips/alt_stub.S */ 15123 /* 15124 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15125 * any interesting requests and then jump to the real instruction 15126 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15127 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15128 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15129 * bail to the real handler if breakFlags==0. 15130 */ 15131 lbu a3, offThread_breakFlags(rSELF) 15132 la rBIX, dvmAsmInstructionStart + (116 * 128) 15133 lw rIBASE, offThread_curHandlerTable(rSELF) 15134 bnez a3, 1f 15135 jr rBIX # nothing to do - jump to real handler 15136 1: 15137 EXPORT_PC() 15138 move a0, rPC # arg0 15139 move a1, rFP # arg1 15140 move a2, rSELF # arg2 15141 JAL(dvmCheckBefore) 15142 jr rBIX 15143 15144 /* ------------------------------ */ 15145 .balign 128 15146 .L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 15147 /* File: mips/alt_stub.S */ 15148 /* 15149 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15150 * any interesting requests and then jump to the real instruction 15151 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15152 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15153 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15154 * bail to the real handler if breakFlags==0. 15155 */ 15156 lbu a3, offThread_breakFlags(rSELF) 15157 la rBIX, dvmAsmInstructionStart + (117 * 128) 15158 lw rIBASE, offThread_curHandlerTable(rSELF) 15159 bnez a3, 1f 15160 jr rBIX # nothing to do - jump to real handler 15161 1: 15162 EXPORT_PC() 15163 move a0, rPC # arg0 15164 move a1, rFP # arg1 15165 move a2, rSELF # arg2 15166 JAL(dvmCheckBefore) 15167 jr rBIX 15168 15169 /* ------------------------------ */ 15170 .balign 128 15171 .L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 15172 /* File: mips/alt_stub.S */ 15173 /* 15174 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15175 * any interesting requests and then jump to the real instruction 15176 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15177 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15178 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15179 * bail to the real handler if breakFlags==0. 15180 */ 15181 lbu a3, offThread_breakFlags(rSELF) 15182 la rBIX, dvmAsmInstructionStart + (118 * 128) 15183 lw rIBASE, offThread_curHandlerTable(rSELF) 15184 bnez a3, 1f 15185 jr rBIX # nothing to do - jump to real handler 15186 1: 15187 EXPORT_PC() 15188 move a0, rPC # arg0 15189 move a1, rFP # arg1 15190 move a2, rSELF # arg2 15191 JAL(dvmCheckBefore) 15192 jr rBIX 15193 15194 /* ------------------------------ */ 15195 .balign 128 15196 .L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 15197 /* File: mips/alt_stub.S */ 15198 /* 15199 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15200 * any interesting requests and then jump to the real instruction 15201 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15202 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15203 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15204 * bail to the real handler if breakFlags==0. 15205 */ 15206 lbu a3, offThread_breakFlags(rSELF) 15207 la rBIX, dvmAsmInstructionStart + (119 * 128) 15208 lw rIBASE, offThread_curHandlerTable(rSELF) 15209 bnez a3, 1f 15210 jr rBIX # nothing to do - jump to real handler 15211 1: 15212 EXPORT_PC() 15213 move a0, rPC # arg0 15214 move a1, rFP # arg1 15215 move a2, rSELF # arg2 15216 JAL(dvmCheckBefore) 15217 jr rBIX 15218 15219 /* ------------------------------ */ 15220 .balign 128 15221 .L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 15222 /* File: mips/alt_stub.S */ 15223 /* 15224 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15225 * any interesting requests and then jump to the real instruction 15226 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15227 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15228 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15229 * bail to the real handler if breakFlags==0. 15230 */ 15231 lbu a3, offThread_breakFlags(rSELF) 15232 la rBIX, dvmAsmInstructionStart + (120 * 128) 15233 lw rIBASE, offThread_curHandlerTable(rSELF) 15234 bnez a3, 1f 15235 jr rBIX # nothing to do - jump to real handler 15236 1: 15237 EXPORT_PC() 15238 move a0, rPC # arg0 15239 move a1, rFP # arg1 15240 move a2, rSELF # arg2 15241 JAL(dvmCheckBefore) 15242 jr rBIX 15243 15244 /* ------------------------------ */ 15245 .balign 128 15246 .L_ALT_OP_UNUSED_79: /* 0x79 */ 15247 /* File: mips/alt_stub.S */ 15248 /* 15249 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15250 * any interesting requests and then jump to the real instruction 15251 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15252 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15253 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15254 * bail to the real handler if breakFlags==0. 15255 */ 15256 lbu a3, offThread_breakFlags(rSELF) 15257 la rBIX, dvmAsmInstructionStart + (121 * 128) 15258 lw rIBASE, offThread_curHandlerTable(rSELF) 15259 bnez a3, 1f 15260 jr rBIX # nothing to do - jump to real handler 15261 1: 15262 EXPORT_PC() 15263 move a0, rPC # arg0 15264 move a1, rFP # arg1 15265 move a2, rSELF # arg2 15266 JAL(dvmCheckBefore) 15267 jr rBIX 15268 15269 /* ------------------------------ */ 15270 .balign 128 15271 .L_ALT_OP_UNUSED_7A: /* 0x7a */ 15272 /* File: mips/alt_stub.S */ 15273 /* 15274 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15275 * any interesting requests and then jump to the real instruction 15276 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15277 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15278 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15279 * bail to the real handler if breakFlags==0. 15280 */ 15281 lbu a3, offThread_breakFlags(rSELF) 15282 la rBIX, dvmAsmInstructionStart + (122 * 128) 15283 lw rIBASE, offThread_curHandlerTable(rSELF) 15284 bnez a3, 1f 15285 jr rBIX # nothing to do - jump to real handler 15286 1: 15287 EXPORT_PC() 15288 move a0, rPC # arg0 15289 move a1, rFP # arg1 15290 move a2, rSELF # arg2 15291 JAL(dvmCheckBefore) 15292 jr rBIX 15293 15294 /* ------------------------------ */ 15295 .balign 128 15296 .L_ALT_OP_NEG_INT: /* 0x7b */ 15297 /* File: mips/alt_stub.S */ 15298 /* 15299 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15300 * any interesting requests and then jump to the real instruction 15301 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15302 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15303 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15304 * bail to the real handler if breakFlags==0. 15305 */ 15306 lbu a3, offThread_breakFlags(rSELF) 15307 la rBIX, dvmAsmInstructionStart + (123 * 128) 15308 lw rIBASE, offThread_curHandlerTable(rSELF) 15309 bnez a3, 1f 15310 jr rBIX # nothing to do - jump to real handler 15311 1: 15312 EXPORT_PC() 15313 move a0, rPC # arg0 15314 move a1, rFP # arg1 15315 move a2, rSELF # arg2 15316 JAL(dvmCheckBefore) 15317 jr rBIX 15318 15319 /* ------------------------------ */ 15320 .balign 128 15321 .L_ALT_OP_NOT_INT: /* 0x7c */ 15322 /* File: mips/alt_stub.S */ 15323 /* 15324 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15325 * any interesting requests and then jump to the real instruction 15326 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15327 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15328 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15329 * bail to the real handler if breakFlags==0. 15330 */ 15331 lbu a3, offThread_breakFlags(rSELF) 15332 la rBIX, dvmAsmInstructionStart + (124 * 128) 15333 lw rIBASE, offThread_curHandlerTable(rSELF) 15334 bnez a3, 1f 15335 jr rBIX # nothing to do - jump to real handler 15336 1: 15337 EXPORT_PC() 15338 move a0, rPC # arg0 15339 move a1, rFP # arg1 15340 move a2, rSELF # arg2 15341 JAL(dvmCheckBefore) 15342 jr rBIX 15343 15344 /* ------------------------------ */ 15345 .balign 128 15346 .L_ALT_OP_NEG_LONG: /* 0x7d */ 15347 /* File: mips/alt_stub.S */ 15348 /* 15349 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15350 * any interesting requests and then jump to the real instruction 15351 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15352 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15353 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15354 * bail to the real handler if breakFlags==0. 15355 */ 15356 lbu a3, offThread_breakFlags(rSELF) 15357 la rBIX, dvmAsmInstructionStart + (125 * 128) 15358 lw rIBASE, offThread_curHandlerTable(rSELF) 15359 bnez a3, 1f 15360 jr rBIX # nothing to do - jump to real handler 15361 1: 15362 EXPORT_PC() 15363 move a0, rPC # arg0 15364 move a1, rFP # arg1 15365 move a2, rSELF # arg2 15366 JAL(dvmCheckBefore) 15367 jr rBIX 15368 15369 /* ------------------------------ */ 15370 .balign 128 15371 .L_ALT_OP_NOT_LONG: /* 0x7e */ 15372 /* File: mips/alt_stub.S */ 15373 /* 15374 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15375 * any interesting requests and then jump to the real instruction 15376 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15377 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15378 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15379 * bail to the real handler if breakFlags==0. 15380 */ 15381 lbu a3, offThread_breakFlags(rSELF) 15382 la rBIX, dvmAsmInstructionStart + (126 * 128) 15383 lw rIBASE, offThread_curHandlerTable(rSELF) 15384 bnez a3, 1f 15385 jr rBIX # nothing to do - jump to real handler 15386 1: 15387 EXPORT_PC() 15388 move a0, rPC # arg0 15389 move a1, rFP # arg1 15390 move a2, rSELF # arg2 15391 JAL(dvmCheckBefore) 15392 jr rBIX 15393 15394 /* ------------------------------ */ 15395 .balign 128 15396 .L_ALT_OP_NEG_FLOAT: /* 0x7f */ 15397 /* File: mips/alt_stub.S */ 15398 /* 15399 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15400 * any interesting requests and then jump to the real instruction 15401 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15402 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15403 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15404 * bail to the real handler if breakFlags==0. 15405 */ 15406 lbu a3, offThread_breakFlags(rSELF) 15407 la rBIX, dvmAsmInstructionStart + (127 * 128) 15408 lw rIBASE, offThread_curHandlerTable(rSELF) 15409 bnez a3, 1f 15410 jr rBIX # nothing to do - jump to real handler 15411 1: 15412 EXPORT_PC() 15413 move a0, rPC # arg0 15414 move a1, rFP # arg1 15415 move a2, rSELF # arg2 15416 JAL(dvmCheckBefore) 15417 jr rBIX 15418 15419 /* ------------------------------ */ 15420 .balign 128 15421 .L_ALT_OP_NEG_DOUBLE: /* 0x80 */ 15422 /* File: mips/alt_stub.S */ 15423 /* 15424 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15425 * any interesting requests and then jump to the real instruction 15426 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15427 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15428 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15429 * bail to the real handler if breakFlags==0. 15430 */ 15431 lbu a3, offThread_breakFlags(rSELF) 15432 la rBIX, dvmAsmInstructionStart + (128 * 128) 15433 lw rIBASE, offThread_curHandlerTable(rSELF) 15434 bnez a3, 1f 15435 jr rBIX # nothing to do - jump to real handler 15436 1: 15437 EXPORT_PC() 15438 move a0, rPC # arg0 15439 move a1, rFP # arg1 15440 move a2, rSELF # arg2 15441 JAL(dvmCheckBefore) 15442 jr rBIX 15443 15444 /* ------------------------------ */ 15445 .balign 128 15446 .L_ALT_OP_INT_TO_LONG: /* 0x81 */ 15447 /* File: mips/alt_stub.S */ 15448 /* 15449 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15450 * any interesting requests and then jump to the real instruction 15451 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15452 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15453 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15454 * bail to the real handler if breakFlags==0. 15455 */ 15456 lbu a3, offThread_breakFlags(rSELF) 15457 la rBIX, dvmAsmInstructionStart + (129 * 128) 15458 lw rIBASE, offThread_curHandlerTable(rSELF) 15459 bnez a3, 1f 15460 jr rBIX # nothing to do - jump to real handler 15461 1: 15462 EXPORT_PC() 15463 move a0, rPC # arg0 15464 move a1, rFP # arg1 15465 move a2, rSELF # arg2 15466 JAL(dvmCheckBefore) 15467 jr rBIX 15468 15469 /* ------------------------------ */ 15470 .balign 128 15471 .L_ALT_OP_INT_TO_FLOAT: /* 0x82 */ 15472 /* File: mips/alt_stub.S */ 15473 /* 15474 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15475 * any interesting requests and then jump to the real instruction 15476 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15477 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15478 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15479 * bail to the real handler if breakFlags==0. 15480 */ 15481 lbu a3, offThread_breakFlags(rSELF) 15482 la rBIX, dvmAsmInstructionStart + (130 * 128) 15483 lw rIBASE, offThread_curHandlerTable(rSELF) 15484 bnez a3, 1f 15485 jr rBIX # nothing to do - jump to real handler 15486 1: 15487 EXPORT_PC() 15488 move a0, rPC # arg0 15489 move a1, rFP # arg1 15490 move a2, rSELF # arg2 15491 JAL(dvmCheckBefore) 15492 jr rBIX 15493 15494 /* ------------------------------ */ 15495 .balign 128 15496 .L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */ 15497 /* File: mips/alt_stub.S */ 15498 /* 15499 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15500 * any interesting requests and then jump to the real instruction 15501 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15502 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15503 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15504 * bail to the real handler if breakFlags==0. 15505 */ 15506 lbu a3, offThread_breakFlags(rSELF) 15507 la rBIX, dvmAsmInstructionStart + (131 * 128) 15508 lw rIBASE, offThread_curHandlerTable(rSELF) 15509 bnez a3, 1f 15510 jr rBIX # nothing to do - jump to real handler 15511 1: 15512 EXPORT_PC() 15513 move a0, rPC # arg0 15514 move a1, rFP # arg1 15515 move a2, rSELF # arg2 15516 JAL(dvmCheckBefore) 15517 jr rBIX 15518 15519 /* ------------------------------ */ 15520 .balign 128 15521 .L_ALT_OP_LONG_TO_INT: /* 0x84 */ 15522 /* File: mips/alt_stub.S */ 15523 /* 15524 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15525 * any interesting requests and then jump to the real instruction 15526 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15527 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15528 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15529 * bail to the real handler if breakFlags==0. 15530 */ 15531 lbu a3, offThread_breakFlags(rSELF) 15532 la rBIX, dvmAsmInstructionStart + (132 * 128) 15533 lw rIBASE, offThread_curHandlerTable(rSELF) 15534 bnez a3, 1f 15535 jr rBIX # nothing to do - jump to real handler 15536 1: 15537 EXPORT_PC() 15538 move a0, rPC # arg0 15539 move a1, rFP # arg1 15540 move a2, rSELF # arg2 15541 JAL(dvmCheckBefore) 15542 jr rBIX 15543 15544 /* ------------------------------ */ 15545 .balign 128 15546 .L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */ 15547 /* File: mips/alt_stub.S */ 15548 /* 15549 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15550 * any interesting requests and then jump to the real instruction 15551 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15552 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15553 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15554 * bail to the real handler if breakFlags==0. 15555 */ 15556 lbu a3, offThread_breakFlags(rSELF) 15557 la rBIX, dvmAsmInstructionStart + (133 * 128) 15558 lw rIBASE, offThread_curHandlerTable(rSELF) 15559 bnez a3, 1f 15560 jr rBIX # nothing to do - jump to real handler 15561 1: 15562 EXPORT_PC() 15563 move a0, rPC # arg0 15564 move a1, rFP # arg1 15565 move a2, rSELF # arg2 15566 JAL(dvmCheckBefore) 15567 jr rBIX 15568 15569 /* ------------------------------ */ 15570 .balign 128 15571 .L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */ 15572 /* File: mips/alt_stub.S */ 15573 /* 15574 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15575 * any interesting requests and then jump to the real instruction 15576 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15577 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15578 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15579 * bail to the real handler if breakFlags==0. 15580 */ 15581 lbu a3, offThread_breakFlags(rSELF) 15582 la rBIX, dvmAsmInstructionStart + (134 * 128) 15583 lw rIBASE, offThread_curHandlerTable(rSELF) 15584 bnez a3, 1f 15585 jr rBIX # nothing to do - jump to real handler 15586 1: 15587 EXPORT_PC() 15588 move a0, rPC # arg0 15589 move a1, rFP # arg1 15590 move a2, rSELF # arg2 15591 JAL(dvmCheckBefore) 15592 jr rBIX 15593 15594 /* ------------------------------ */ 15595 .balign 128 15596 .L_ALT_OP_FLOAT_TO_INT: /* 0x87 */ 15597 /* File: mips/alt_stub.S */ 15598 /* 15599 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15600 * any interesting requests and then jump to the real instruction 15601 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15602 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15603 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15604 * bail to the real handler if breakFlags==0. 15605 */ 15606 lbu a3, offThread_breakFlags(rSELF) 15607 la rBIX, dvmAsmInstructionStart + (135 * 128) 15608 lw rIBASE, offThread_curHandlerTable(rSELF) 15609 bnez a3, 1f 15610 jr rBIX # nothing to do - jump to real handler 15611 1: 15612 EXPORT_PC() 15613 move a0, rPC # arg0 15614 move a1, rFP # arg1 15615 move a2, rSELF # arg2 15616 JAL(dvmCheckBefore) 15617 jr rBIX 15618 15619 /* ------------------------------ */ 15620 .balign 128 15621 .L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */ 15622 /* File: mips/alt_stub.S */ 15623 /* 15624 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15625 * any interesting requests and then jump to the real instruction 15626 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15627 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15628 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15629 * bail to the real handler if breakFlags==0. 15630 */ 15631 lbu a3, offThread_breakFlags(rSELF) 15632 la rBIX, dvmAsmInstructionStart + (136 * 128) 15633 lw rIBASE, offThread_curHandlerTable(rSELF) 15634 bnez a3, 1f 15635 jr rBIX # nothing to do - jump to real handler 15636 1: 15637 EXPORT_PC() 15638 move a0, rPC # arg0 15639 move a1, rFP # arg1 15640 move a2, rSELF # arg2 15641 JAL(dvmCheckBefore) 15642 jr rBIX 15643 15644 /* ------------------------------ */ 15645 .balign 128 15646 .L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 15647 /* File: mips/alt_stub.S */ 15648 /* 15649 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15650 * any interesting requests and then jump to the real instruction 15651 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15652 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15653 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15654 * bail to the real handler if breakFlags==0. 15655 */ 15656 lbu a3, offThread_breakFlags(rSELF) 15657 la rBIX, dvmAsmInstructionStart + (137 * 128) 15658 lw rIBASE, offThread_curHandlerTable(rSELF) 15659 bnez a3, 1f 15660 jr rBIX # nothing to do - jump to real handler 15661 1: 15662 EXPORT_PC() 15663 move a0, rPC # arg0 15664 move a1, rFP # arg1 15665 move a2, rSELF # arg2 15666 JAL(dvmCheckBefore) 15667 jr rBIX 15668 15669 /* ------------------------------ */ 15670 .balign 128 15671 .L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */ 15672 /* File: mips/alt_stub.S */ 15673 /* 15674 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15675 * any interesting requests and then jump to the real instruction 15676 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15677 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15678 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15679 * bail to the real handler if breakFlags==0. 15680 */ 15681 lbu a3, offThread_breakFlags(rSELF) 15682 la rBIX, dvmAsmInstructionStart + (138 * 128) 15683 lw rIBASE, offThread_curHandlerTable(rSELF) 15684 bnez a3, 1f 15685 jr rBIX # nothing to do - jump to real handler 15686 1: 15687 EXPORT_PC() 15688 move a0, rPC # arg0 15689 move a1, rFP # arg1 15690 move a2, rSELF # arg2 15691 JAL(dvmCheckBefore) 15692 jr rBIX 15693 15694 /* ------------------------------ */ 15695 .balign 128 15696 .L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */ 15697 /* File: mips/alt_stub.S */ 15698 /* 15699 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15700 * any interesting requests and then jump to the real instruction 15701 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15702 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15703 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15704 * bail to the real handler if breakFlags==0. 15705 */ 15706 lbu a3, offThread_breakFlags(rSELF) 15707 la rBIX, dvmAsmInstructionStart + (139 * 128) 15708 lw rIBASE, offThread_curHandlerTable(rSELF) 15709 bnez a3, 1f 15710 jr rBIX # nothing to do - jump to real handler 15711 1: 15712 EXPORT_PC() 15713 move a0, rPC # arg0 15714 move a1, rFP # arg1 15715 move a2, rSELF # arg2 15716 JAL(dvmCheckBefore) 15717 jr rBIX 15718 15719 /* ------------------------------ */ 15720 .balign 128 15721 .L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 15722 /* File: mips/alt_stub.S */ 15723 /* 15724 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15725 * any interesting requests and then jump to the real instruction 15726 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15727 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15728 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15729 * bail to the real handler if breakFlags==0. 15730 */ 15731 lbu a3, offThread_breakFlags(rSELF) 15732 la rBIX, dvmAsmInstructionStart + (140 * 128) 15733 lw rIBASE, offThread_curHandlerTable(rSELF) 15734 bnez a3, 1f 15735 jr rBIX # nothing to do - jump to real handler 15736 1: 15737 EXPORT_PC() 15738 move a0, rPC # arg0 15739 move a1, rFP # arg1 15740 move a2, rSELF # arg2 15741 JAL(dvmCheckBefore) 15742 jr rBIX 15743 15744 /* ------------------------------ */ 15745 .balign 128 15746 .L_ALT_OP_INT_TO_BYTE: /* 0x8d */ 15747 /* File: mips/alt_stub.S */ 15748 /* 15749 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15750 * any interesting requests and then jump to the real instruction 15751 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15752 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15753 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15754 * bail to the real handler if breakFlags==0. 15755 */ 15756 lbu a3, offThread_breakFlags(rSELF) 15757 la rBIX, dvmAsmInstructionStart + (141 * 128) 15758 lw rIBASE, offThread_curHandlerTable(rSELF) 15759 bnez a3, 1f 15760 jr rBIX # nothing to do - jump to real handler 15761 1: 15762 EXPORT_PC() 15763 move a0, rPC # arg0 15764 move a1, rFP # arg1 15765 move a2, rSELF # arg2 15766 JAL(dvmCheckBefore) 15767 jr rBIX 15768 15769 /* ------------------------------ */ 15770 .balign 128 15771 .L_ALT_OP_INT_TO_CHAR: /* 0x8e */ 15772 /* File: mips/alt_stub.S */ 15773 /* 15774 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15775 * any interesting requests and then jump to the real instruction 15776 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15777 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15778 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15779 * bail to the real handler if breakFlags==0. 15780 */ 15781 lbu a3, offThread_breakFlags(rSELF) 15782 la rBIX, dvmAsmInstructionStart + (142 * 128) 15783 lw rIBASE, offThread_curHandlerTable(rSELF) 15784 bnez a3, 1f 15785 jr rBIX # nothing to do - jump to real handler 15786 1: 15787 EXPORT_PC() 15788 move a0, rPC # arg0 15789 move a1, rFP # arg1 15790 move a2, rSELF # arg2 15791 JAL(dvmCheckBefore) 15792 jr rBIX 15793 15794 /* ------------------------------ */ 15795 .balign 128 15796 .L_ALT_OP_INT_TO_SHORT: /* 0x8f */ 15797 /* File: mips/alt_stub.S */ 15798 /* 15799 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15800 * any interesting requests and then jump to the real instruction 15801 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15802 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15803 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15804 * bail to the real handler if breakFlags==0. 15805 */ 15806 lbu a3, offThread_breakFlags(rSELF) 15807 la rBIX, dvmAsmInstructionStart + (143 * 128) 15808 lw rIBASE, offThread_curHandlerTable(rSELF) 15809 bnez a3, 1f 15810 jr rBIX # nothing to do - jump to real handler 15811 1: 15812 EXPORT_PC() 15813 move a0, rPC # arg0 15814 move a1, rFP # arg1 15815 move a2, rSELF # arg2 15816 JAL(dvmCheckBefore) 15817 jr rBIX 15818 15819 /* ------------------------------ */ 15820 .balign 128 15821 .L_ALT_OP_ADD_INT: /* 0x90 */ 15822 /* File: mips/alt_stub.S */ 15823 /* 15824 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15825 * any interesting requests and then jump to the real instruction 15826 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15827 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15828 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15829 * bail to the real handler if breakFlags==0. 15830 */ 15831 lbu a3, offThread_breakFlags(rSELF) 15832 la rBIX, dvmAsmInstructionStart + (144 * 128) 15833 lw rIBASE, offThread_curHandlerTable(rSELF) 15834 bnez a3, 1f 15835 jr rBIX # nothing to do - jump to real handler 15836 1: 15837 EXPORT_PC() 15838 move a0, rPC # arg0 15839 move a1, rFP # arg1 15840 move a2, rSELF # arg2 15841 JAL(dvmCheckBefore) 15842 jr rBIX 15843 15844 /* ------------------------------ */ 15845 .balign 128 15846 .L_ALT_OP_SUB_INT: /* 0x91 */ 15847 /* File: mips/alt_stub.S */ 15848 /* 15849 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15850 * any interesting requests and then jump to the real instruction 15851 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15852 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15853 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15854 * bail to the real handler if breakFlags==0. 15855 */ 15856 lbu a3, offThread_breakFlags(rSELF) 15857 la rBIX, dvmAsmInstructionStart + (145 * 128) 15858 lw rIBASE, offThread_curHandlerTable(rSELF) 15859 bnez a3, 1f 15860 jr rBIX # nothing to do - jump to real handler 15861 1: 15862 EXPORT_PC() 15863 move a0, rPC # arg0 15864 move a1, rFP # arg1 15865 move a2, rSELF # arg2 15866 JAL(dvmCheckBefore) 15867 jr rBIX 15868 15869 /* ------------------------------ */ 15870 .balign 128 15871 .L_ALT_OP_MUL_INT: /* 0x92 */ 15872 /* File: mips/alt_stub.S */ 15873 /* 15874 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15875 * any interesting requests and then jump to the real instruction 15876 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15877 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15878 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15879 * bail to the real handler if breakFlags==0. 15880 */ 15881 lbu a3, offThread_breakFlags(rSELF) 15882 la rBIX, dvmAsmInstructionStart + (146 * 128) 15883 lw rIBASE, offThread_curHandlerTable(rSELF) 15884 bnez a3, 1f 15885 jr rBIX # nothing to do - jump to real handler 15886 1: 15887 EXPORT_PC() 15888 move a0, rPC # arg0 15889 move a1, rFP # arg1 15890 move a2, rSELF # arg2 15891 JAL(dvmCheckBefore) 15892 jr rBIX 15893 15894 /* ------------------------------ */ 15895 .balign 128 15896 .L_ALT_OP_DIV_INT: /* 0x93 */ 15897 /* File: mips/alt_stub.S */ 15898 /* 15899 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15900 * any interesting requests and then jump to the real instruction 15901 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15902 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15903 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15904 * bail to the real handler if breakFlags==0. 15905 */ 15906 lbu a3, offThread_breakFlags(rSELF) 15907 la rBIX, dvmAsmInstructionStart + (147 * 128) 15908 lw rIBASE, offThread_curHandlerTable(rSELF) 15909 bnez a3, 1f 15910 jr rBIX # nothing to do - jump to real handler 15911 1: 15912 EXPORT_PC() 15913 move a0, rPC # arg0 15914 move a1, rFP # arg1 15915 move a2, rSELF # arg2 15916 JAL(dvmCheckBefore) 15917 jr rBIX 15918 15919 /* ------------------------------ */ 15920 .balign 128 15921 .L_ALT_OP_REM_INT: /* 0x94 */ 15922 /* File: mips/alt_stub.S */ 15923 /* 15924 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15925 * any interesting requests and then jump to the real instruction 15926 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15927 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15928 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15929 * bail to the real handler if breakFlags==0. 15930 */ 15931 lbu a3, offThread_breakFlags(rSELF) 15932 la rBIX, dvmAsmInstructionStart + (148 * 128) 15933 lw rIBASE, offThread_curHandlerTable(rSELF) 15934 bnez a3, 1f 15935 jr rBIX # nothing to do - jump to real handler 15936 1: 15937 EXPORT_PC() 15938 move a0, rPC # arg0 15939 move a1, rFP # arg1 15940 move a2, rSELF # arg2 15941 JAL(dvmCheckBefore) 15942 jr rBIX 15943 15944 /* ------------------------------ */ 15945 .balign 128 15946 .L_ALT_OP_AND_INT: /* 0x95 */ 15947 /* File: mips/alt_stub.S */ 15948 /* 15949 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15950 * any interesting requests and then jump to the real instruction 15951 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15952 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15953 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15954 * bail to the real handler if breakFlags==0. 15955 */ 15956 lbu a3, offThread_breakFlags(rSELF) 15957 la rBIX, dvmAsmInstructionStart + (149 * 128) 15958 lw rIBASE, offThread_curHandlerTable(rSELF) 15959 bnez a3, 1f 15960 jr rBIX # nothing to do - jump to real handler 15961 1: 15962 EXPORT_PC() 15963 move a0, rPC # arg0 15964 move a1, rFP # arg1 15965 move a2, rSELF # arg2 15966 JAL(dvmCheckBefore) 15967 jr rBIX 15968 15969 /* ------------------------------ */ 15970 .balign 128 15971 .L_ALT_OP_OR_INT: /* 0x96 */ 15972 /* File: mips/alt_stub.S */ 15973 /* 15974 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15975 * any interesting requests and then jump to the real instruction 15976 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15977 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15978 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15979 * bail to the real handler if breakFlags==0. 15980 */ 15981 lbu a3, offThread_breakFlags(rSELF) 15982 la rBIX, dvmAsmInstructionStart + (150 * 128) 15983 lw rIBASE, offThread_curHandlerTable(rSELF) 15984 bnez a3, 1f 15985 jr rBIX # nothing to do - jump to real handler 15986 1: 15987 EXPORT_PC() 15988 move a0, rPC # arg0 15989 move a1, rFP # arg1 15990 move a2, rSELF # arg2 15991 JAL(dvmCheckBefore) 15992 jr rBIX 15993 15994 /* ------------------------------ */ 15995 .balign 128 15996 .L_ALT_OP_XOR_INT: /* 0x97 */ 15997 /* File: mips/alt_stub.S */ 15998 /* 15999 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16000 * any interesting requests and then jump to the real instruction 16001 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16002 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16003 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16004 * bail to the real handler if breakFlags==0. 16005 */ 16006 lbu a3, offThread_breakFlags(rSELF) 16007 la rBIX, dvmAsmInstructionStart + (151 * 128) 16008 lw rIBASE, offThread_curHandlerTable(rSELF) 16009 bnez a3, 1f 16010 jr rBIX # nothing to do - jump to real handler 16011 1: 16012 EXPORT_PC() 16013 move a0, rPC # arg0 16014 move a1, rFP # arg1 16015 move a2, rSELF # arg2 16016 JAL(dvmCheckBefore) 16017 jr rBIX 16018 16019 /* ------------------------------ */ 16020 .balign 128 16021 .L_ALT_OP_SHL_INT: /* 0x98 */ 16022 /* File: mips/alt_stub.S */ 16023 /* 16024 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16025 * any interesting requests and then jump to the real instruction 16026 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16027 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16028 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16029 * bail to the real handler if breakFlags==0. 16030 */ 16031 lbu a3, offThread_breakFlags(rSELF) 16032 la rBIX, dvmAsmInstructionStart + (152 * 128) 16033 lw rIBASE, offThread_curHandlerTable(rSELF) 16034 bnez a3, 1f 16035 jr rBIX # nothing to do - jump to real handler 16036 1: 16037 EXPORT_PC() 16038 move a0, rPC # arg0 16039 move a1, rFP # arg1 16040 move a2, rSELF # arg2 16041 JAL(dvmCheckBefore) 16042 jr rBIX 16043 16044 /* ------------------------------ */ 16045 .balign 128 16046 .L_ALT_OP_SHR_INT: /* 0x99 */ 16047 /* File: mips/alt_stub.S */ 16048 /* 16049 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16050 * any interesting requests and then jump to the real instruction 16051 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16052 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16053 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16054 * bail to the real handler if breakFlags==0. 16055 */ 16056 lbu a3, offThread_breakFlags(rSELF) 16057 la rBIX, dvmAsmInstructionStart + (153 * 128) 16058 lw rIBASE, offThread_curHandlerTable(rSELF) 16059 bnez a3, 1f 16060 jr rBIX # nothing to do - jump to real handler 16061 1: 16062 EXPORT_PC() 16063 move a0, rPC # arg0 16064 move a1, rFP # arg1 16065 move a2, rSELF # arg2 16066 JAL(dvmCheckBefore) 16067 jr rBIX 16068 16069 /* ------------------------------ */ 16070 .balign 128 16071 .L_ALT_OP_USHR_INT: /* 0x9a */ 16072 /* File: mips/alt_stub.S */ 16073 /* 16074 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16075 * any interesting requests and then jump to the real instruction 16076 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16077 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16078 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16079 * bail to the real handler if breakFlags==0. 16080 */ 16081 lbu a3, offThread_breakFlags(rSELF) 16082 la rBIX, dvmAsmInstructionStart + (154 * 128) 16083 lw rIBASE, offThread_curHandlerTable(rSELF) 16084 bnez a3, 1f 16085 jr rBIX # nothing to do - jump to real handler 16086 1: 16087 EXPORT_PC() 16088 move a0, rPC # arg0 16089 move a1, rFP # arg1 16090 move a2, rSELF # arg2 16091 JAL(dvmCheckBefore) 16092 jr rBIX 16093 16094 /* ------------------------------ */ 16095 .balign 128 16096 .L_ALT_OP_ADD_LONG: /* 0x9b */ 16097 /* File: mips/alt_stub.S */ 16098 /* 16099 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16100 * any interesting requests and then jump to the real instruction 16101 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16102 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16103 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16104 * bail to the real handler if breakFlags==0. 16105 */ 16106 lbu a3, offThread_breakFlags(rSELF) 16107 la rBIX, dvmAsmInstructionStart + (155 * 128) 16108 lw rIBASE, offThread_curHandlerTable(rSELF) 16109 bnez a3, 1f 16110 jr rBIX # nothing to do - jump to real handler 16111 1: 16112 EXPORT_PC() 16113 move a0, rPC # arg0 16114 move a1, rFP # arg1 16115 move a2, rSELF # arg2 16116 JAL(dvmCheckBefore) 16117 jr rBIX 16118 16119 /* ------------------------------ */ 16120 .balign 128 16121 .L_ALT_OP_SUB_LONG: /* 0x9c */ 16122 /* File: mips/alt_stub.S */ 16123 /* 16124 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16125 * any interesting requests and then jump to the real instruction 16126 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16127 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16128 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16129 * bail to the real handler if breakFlags==0. 16130 */ 16131 lbu a3, offThread_breakFlags(rSELF) 16132 la rBIX, dvmAsmInstructionStart + (156 * 128) 16133 lw rIBASE, offThread_curHandlerTable(rSELF) 16134 bnez a3, 1f 16135 jr rBIX # nothing to do - jump to real handler 16136 1: 16137 EXPORT_PC() 16138 move a0, rPC # arg0 16139 move a1, rFP # arg1 16140 move a2, rSELF # arg2 16141 JAL(dvmCheckBefore) 16142 jr rBIX 16143 16144 /* ------------------------------ */ 16145 .balign 128 16146 .L_ALT_OP_MUL_LONG: /* 0x9d */ 16147 /* File: mips/alt_stub.S */ 16148 /* 16149 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16150 * any interesting requests and then jump to the real instruction 16151 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16152 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16153 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16154 * bail to the real handler if breakFlags==0. 16155 */ 16156 lbu a3, offThread_breakFlags(rSELF) 16157 la rBIX, dvmAsmInstructionStart + (157 * 128) 16158 lw rIBASE, offThread_curHandlerTable(rSELF) 16159 bnez a3, 1f 16160 jr rBIX # nothing to do - jump to real handler 16161 1: 16162 EXPORT_PC() 16163 move a0, rPC # arg0 16164 move a1, rFP # arg1 16165 move a2, rSELF # arg2 16166 JAL(dvmCheckBefore) 16167 jr rBIX 16168 16169 /* ------------------------------ */ 16170 .balign 128 16171 .L_ALT_OP_DIV_LONG: /* 0x9e */ 16172 /* File: mips/alt_stub.S */ 16173 /* 16174 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16175 * any interesting requests and then jump to the real instruction 16176 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16177 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16178 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16179 * bail to the real handler if breakFlags==0. 16180 */ 16181 lbu a3, offThread_breakFlags(rSELF) 16182 la rBIX, dvmAsmInstructionStart + (158 * 128) 16183 lw rIBASE, offThread_curHandlerTable(rSELF) 16184 bnez a3, 1f 16185 jr rBIX # nothing to do - jump to real handler 16186 1: 16187 EXPORT_PC() 16188 move a0, rPC # arg0 16189 move a1, rFP # arg1 16190 move a2, rSELF # arg2 16191 JAL(dvmCheckBefore) 16192 jr rBIX 16193 16194 /* ------------------------------ */ 16195 .balign 128 16196 .L_ALT_OP_REM_LONG: /* 0x9f */ 16197 /* File: mips/alt_stub.S */ 16198 /* 16199 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16200 * any interesting requests and then jump to the real instruction 16201 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16202 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16203 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16204 * bail to the real handler if breakFlags==0. 16205 */ 16206 lbu a3, offThread_breakFlags(rSELF) 16207 la rBIX, dvmAsmInstructionStart + (159 * 128) 16208 lw rIBASE, offThread_curHandlerTable(rSELF) 16209 bnez a3, 1f 16210 jr rBIX # nothing to do - jump to real handler 16211 1: 16212 EXPORT_PC() 16213 move a0, rPC # arg0 16214 move a1, rFP # arg1 16215 move a2, rSELF # arg2 16216 JAL(dvmCheckBefore) 16217 jr rBIX 16218 16219 /* ------------------------------ */ 16220 .balign 128 16221 .L_ALT_OP_AND_LONG: /* 0xa0 */ 16222 /* File: mips/alt_stub.S */ 16223 /* 16224 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16225 * any interesting requests and then jump to the real instruction 16226 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16227 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16228 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16229 * bail to the real handler if breakFlags==0. 16230 */ 16231 lbu a3, offThread_breakFlags(rSELF) 16232 la rBIX, dvmAsmInstructionStart + (160 * 128) 16233 lw rIBASE, offThread_curHandlerTable(rSELF) 16234 bnez a3, 1f 16235 jr rBIX # nothing to do - jump to real handler 16236 1: 16237 EXPORT_PC() 16238 move a0, rPC # arg0 16239 move a1, rFP # arg1 16240 move a2, rSELF # arg2 16241 JAL(dvmCheckBefore) 16242 jr rBIX 16243 16244 /* ------------------------------ */ 16245 .balign 128 16246 .L_ALT_OP_OR_LONG: /* 0xa1 */ 16247 /* File: mips/alt_stub.S */ 16248 /* 16249 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16250 * any interesting requests and then jump to the real instruction 16251 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16252 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16253 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16254 * bail to the real handler if breakFlags==0. 16255 */ 16256 lbu a3, offThread_breakFlags(rSELF) 16257 la rBIX, dvmAsmInstructionStart + (161 * 128) 16258 lw rIBASE, offThread_curHandlerTable(rSELF) 16259 bnez a3, 1f 16260 jr rBIX # nothing to do - jump to real handler 16261 1: 16262 EXPORT_PC() 16263 move a0, rPC # arg0 16264 move a1, rFP # arg1 16265 move a2, rSELF # arg2 16266 JAL(dvmCheckBefore) 16267 jr rBIX 16268 16269 /* ------------------------------ */ 16270 .balign 128 16271 .L_ALT_OP_XOR_LONG: /* 0xa2 */ 16272 /* File: mips/alt_stub.S */ 16273 /* 16274 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16275 * any interesting requests and then jump to the real instruction 16276 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16277 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16278 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16279 * bail to the real handler if breakFlags==0. 16280 */ 16281 lbu a3, offThread_breakFlags(rSELF) 16282 la rBIX, dvmAsmInstructionStart + (162 * 128) 16283 lw rIBASE, offThread_curHandlerTable(rSELF) 16284 bnez a3, 1f 16285 jr rBIX # nothing to do - jump to real handler 16286 1: 16287 EXPORT_PC() 16288 move a0, rPC # arg0 16289 move a1, rFP # arg1 16290 move a2, rSELF # arg2 16291 JAL(dvmCheckBefore) 16292 jr rBIX 16293 16294 /* ------------------------------ */ 16295 .balign 128 16296 .L_ALT_OP_SHL_LONG: /* 0xa3 */ 16297 /* File: mips/alt_stub.S */ 16298 /* 16299 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16300 * any interesting requests and then jump to the real instruction 16301 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16302 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16303 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16304 * bail to the real handler if breakFlags==0. 16305 */ 16306 lbu a3, offThread_breakFlags(rSELF) 16307 la rBIX, dvmAsmInstructionStart + (163 * 128) 16308 lw rIBASE, offThread_curHandlerTable(rSELF) 16309 bnez a3, 1f 16310 jr rBIX # nothing to do - jump to real handler 16311 1: 16312 EXPORT_PC() 16313 move a0, rPC # arg0 16314 move a1, rFP # arg1 16315 move a2, rSELF # arg2 16316 JAL(dvmCheckBefore) 16317 jr rBIX 16318 16319 /* ------------------------------ */ 16320 .balign 128 16321 .L_ALT_OP_SHR_LONG: /* 0xa4 */ 16322 /* File: mips/alt_stub.S */ 16323 /* 16324 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16325 * any interesting requests and then jump to the real instruction 16326 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16327 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16328 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16329 * bail to the real handler if breakFlags==0. 16330 */ 16331 lbu a3, offThread_breakFlags(rSELF) 16332 la rBIX, dvmAsmInstructionStart + (164 * 128) 16333 lw rIBASE, offThread_curHandlerTable(rSELF) 16334 bnez a3, 1f 16335 jr rBIX # nothing to do - jump to real handler 16336 1: 16337 EXPORT_PC() 16338 move a0, rPC # arg0 16339 move a1, rFP # arg1 16340 move a2, rSELF # arg2 16341 JAL(dvmCheckBefore) 16342 jr rBIX 16343 16344 /* ------------------------------ */ 16345 .balign 128 16346 .L_ALT_OP_USHR_LONG: /* 0xa5 */ 16347 /* File: mips/alt_stub.S */ 16348 /* 16349 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16350 * any interesting requests and then jump to the real instruction 16351 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16352 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16353 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16354 * bail to the real handler if breakFlags==0. 16355 */ 16356 lbu a3, offThread_breakFlags(rSELF) 16357 la rBIX, dvmAsmInstructionStart + (165 * 128) 16358 lw rIBASE, offThread_curHandlerTable(rSELF) 16359 bnez a3, 1f 16360 jr rBIX # nothing to do - jump to real handler 16361 1: 16362 EXPORT_PC() 16363 move a0, rPC # arg0 16364 move a1, rFP # arg1 16365 move a2, rSELF # arg2 16366 JAL(dvmCheckBefore) 16367 jr rBIX 16368 16369 /* ------------------------------ */ 16370 .balign 128 16371 .L_ALT_OP_ADD_FLOAT: /* 0xa6 */ 16372 /* File: mips/alt_stub.S */ 16373 /* 16374 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16375 * any interesting requests and then jump to the real instruction 16376 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16377 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16378 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16379 * bail to the real handler if breakFlags==0. 16380 */ 16381 lbu a3, offThread_breakFlags(rSELF) 16382 la rBIX, dvmAsmInstructionStart + (166 * 128) 16383 lw rIBASE, offThread_curHandlerTable(rSELF) 16384 bnez a3, 1f 16385 jr rBIX # nothing to do - jump to real handler 16386 1: 16387 EXPORT_PC() 16388 move a0, rPC # arg0 16389 move a1, rFP # arg1 16390 move a2, rSELF # arg2 16391 JAL(dvmCheckBefore) 16392 jr rBIX 16393 16394 /* ------------------------------ */ 16395 .balign 128 16396 .L_ALT_OP_SUB_FLOAT: /* 0xa7 */ 16397 /* File: mips/alt_stub.S */ 16398 /* 16399 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16400 * any interesting requests and then jump to the real instruction 16401 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16402 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16403 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16404 * bail to the real handler if breakFlags==0. 16405 */ 16406 lbu a3, offThread_breakFlags(rSELF) 16407 la rBIX, dvmAsmInstructionStart + (167 * 128) 16408 lw rIBASE, offThread_curHandlerTable(rSELF) 16409 bnez a3, 1f 16410 jr rBIX # nothing to do - jump to real handler 16411 1: 16412 EXPORT_PC() 16413 move a0, rPC # arg0 16414 move a1, rFP # arg1 16415 move a2, rSELF # arg2 16416 JAL(dvmCheckBefore) 16417 jr rBIX 16418 16419 /* ------------------------------ */ 16420 .balign 128 16421 .L_ALT_OP_MUL_FLOAT: /* 0xa8 */ 16422 /* File: mips/alt_stub.S */ 16423 /* 16424 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16425 * any interesting requests and then jump to the real instruction 16426 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16427 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16428 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16429 * bail to the real handler if breakFlags==0. 16430 */ 16431 lbu a3, offThread_breakFlags(rSELF) 16432 la rBIX, dvmAsmInstructionStart + (168 * 128) 16433 lw rIBASE, offThread_curHandlerTable(rSELF) 16434 bnez a3, 1f 16435 jr rBIX # nothing to do - jump to real handler 16436 1: 16437 EXPORT_PC() 16438 move a0, rPC # arg0 16439 move a1, rFP # arg1 16440 move a2, rSELF # arg2 16441 JAL(dvmCheckBefore) 16442 jr rBIX 16443 16444 /* ------------------------------ */ 16445 .balign 128 16446 .L_ALT_OP_DIV_FLOAT: /* 0xa9 */ 16447 /* File: mips/alt_stub.S */ 16448 /* 16449 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16450 * any interesting requests and then jump to the real instruction 16451 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16452 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16453 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16454 * bail to the real handler if breakFlags==0. 16455 */ 16456 lbu a3, offThread_breakFlags(rSELF) 16457 la rBIX, dvmAsmInstructionStart + (169 * 128) 16458 lw rIBASE, offThread_curHandlerTable(rSELF) 16459 bnez a3, 1f 16460 jr rBIX # nothing to do - jump to real handler 16461 1: 16462 EXPORT_PC() 16463 move a0, rPC # arg0 16464 move a1, rFP # arg1 16465 move a2, rSELF # arg2 16466 JAL(dvmCheckBefore) 16467 jr rBIX 16468 16469 /* ------------------------------ */ 16470 .balign 128 16471 .L_ALT_OP_REM_FLOAT: /* 0xaa */ 16472 /* File: mips/alt_stub.S */ 16473 /* 16474 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16475 * any interesting requests and then jump to the real instruction 16476 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16477 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16478 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16479 * bail to the real handler if breakFlags==0. 16480 */ 16481 lbu a3, offThread_breakFlags(rSELF) 16482 la rBIX, dvmAsmInstructionStart + (170 * 128) 16483 lw rIBASE, offThread_curHandlerTable(rSELF) 16484 bnez a3, 1f 16485 jr rBIX # nothing to do - jump to real handler 16486 1: 16487 EXPORT_PC() 16488 move a0, rPC # arg0 16489 move a1, rFP # arg1 16490 move a2, rSELF # arg2 16491 JAL(dvmCheckBefore) 16492 jr rBIX 16493 16494 /* ------------------------------ */ 16495 .balign 128 16496 .L_ALT_OP_ADD_DOUBLE: /* 0xab */ 16497 /* File: mips/alt_stub.S */ 16498 /* 16499 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16500 * any interesting requests and then jump to the real instruction 16501 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16502 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16503 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16504 * bail to the real handler if breakFlags==0. 16505 */ 16506 lbu a3, offThread_breakFlags(rSELF) 16507 la rBIX, dvmAsmInstructionStart + (171 * 128) 16508 lw rIBASE, offThread_curHandlerTable(rSELF) 16509 bnez a3, 1f 16510 jr rBIX # nothing to do - jump to real handler 16511 1: 16512 EXPORT_PC() 16513 move a0, rPC # arg0 16514 move a1, rFP # arg1 16515 move a2, rSELF # arg2 16516 JAL(dvmCheckBefore) 16517 jr rBIX 16518 16519 /* ------------------------------ */ 16520 .balign 128 16521 .L_ALT_OP_SUB_DOUBLE: /* 0xac */ 16522 /* File: mips/alt_stub.S */ 16523 /* 16524 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16525 * any interesting requests and then jump to the real instruction 16526 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16527 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16528 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16529 * bail to the real handler if breakFlags==0. 16530 */ 16531 lbu a3, offThread_breakFlags(rSELF) 16532 la rBIX, dvmAsmInstructionStart + (172 * 128) 16533 lw rIBASE, offThread_curHandlerTable(rSELF) 16534 bnez a3, 1f 16535 jr rBIX # nothing to do - jump to real handler 16536 1: 16537 EXPORT_PC() 16538 move a0, rPC # arg0 16539 move a1, rFP # arg1 16540 move a2, rSELF # arg2 16541 JAL(dvmCheckBefore) 16542 jr rBIX 16543 16544 /* ------------------------------ */ 16545 .balign 128 16546 .L_ALT_OP_MUL_DOUBLE: /* 0xad */ 16547 /* File: mips/alt_stub.S */ 16548 /* 16549 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16550 * any interesting requests and then jump to the real instruction 16551 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16552 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16553 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16554 * bail to the real handler if breakFlags==0. 16555 */ 16556 lbu a3, offThread_breakFlags(rSELF) 16557 la rBIX, dvmAsmInstructionStart + (173 * 128) 16558 lw rIBASE, offThread_curHandlerTable(rSELF) 16559 bnez a3, 1f 16560 jr rBIX # nothing to do - jump to real handler 16561 1: 16562 EXPORT_PC() 16563 move a0, rPC # arg0 16564 move a1, rFP # arg1 16565 move a2, rSELF # arg2 16566 JAL(dvmCheckBefore) 16567 jr rBIX 16568 16569 /* ------------------------------ */ 16570 .balign 128 16571 .L_ALT_OP_DIV_DOUBLE: /* 0xae */ 16572 /* File: mips/alt_stub.S */ 16573 /* 16574 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16575 * any interesting requests and then jump to the real instruction 16576 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16577 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16578 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16579 * bail to the real handler if breakFlags==0. 16580 */ 16581 lbu a3, offThread_breakFlags(rSELF) 16582 la rBIX, dvmAsmInstructionStart + (174 * 128) 16583 lw rIBASE, offThread_curHandlerTable(rSELF) 16584 bnez a3, 1f 16585 jr rBIX # nothing to do - jump to real handler 16586 1: 16587 EXPORT_PC() 16588 move a0, rPC # arg0 16589 move a1, rFP # arg1 16590 move a2, rSELF # arg2 16591 JAL(dvmCheckBefore) 16592 jr rBIX 16593 16594 /* ------------------------------ */ 16595 .balign 128 16596 .L_ALT_OP_REM_DOUBLE: /* 0xaf */ 16597 /* File: mips/alt_stub.S */ 16598 /* 16599 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16600 * any interesting requests and then jump to the real instruction 16601 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16602 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16603 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16604 * bail to the real handler if breakFlags==0. 16605 */ 16606 lbu a3, offThread_breakFlags(rSELF) 16607 la rBIX, dvmAsmInstructionStart + (175 * 128) 16608 lw rIBASE, offThread_curHandlerTable(rSELF) 16609 bnez a3, 1f 16610 jr rBIX # nothing to do - jump to real handler 16611 1: 16612 EXPORT_PC() 16613 move a0, rPC # arg0 16614 move a1, rFP # arg1 16615 move a2, rSELF # arg2 16616 JAL(dvmCheckBefore) 16617 jr rBIX 16618 16619 /* ------------------------------ */ 16620 .balign 128 16621 .L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */ 16622 /* File: mips/alt_stub.S */ 16623 /* 16624 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16625 * any interesting requests and then jump to the real instruction 16626 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16627 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16628 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16629 * bail to the real handler if breakFlags==0. 16630 */ 16631 lbu a3, offThread_breakFlags(rSELF) 16632 la rBIX, dvmAsmInstructionStart + (176 * 128) 16633 lw rIBASE, offThread_curHandlerTable(rSELF) 16634 bnez a3, 1f 16635 jr rBIX # nothing to do - jump to real handler 16636 1: 16637 EXPORT_PC() 16638 move a0, rPC # arg0 16639 move a1, rFP # arg1 16640 move a2, rSELF # arg2 16641 JAL(dvmCheckBefore) 16642 jr rBIX 16643 16644 /* ------------------------------ */ 16645 .balign 128 16646 .L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */ 16647 /* File: mips/alt_stub.S */ 16648 /* 16649 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16650 * any interesting requests and then jump to the real instruction 16651 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16652 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16653 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16654 * bail to the real handler if breakFlags==0. 16655 */ 16656 lbu a3, offThread_breakFlags(rSELF) 16657 la rBIX, dvmAsmInstructionStart + (177 * 128) 16658 lw rIBASE, offThread_curHandlerTable(rSELF) 16659 bnez a3, 1f 16660 jr rBIX # nothing to do - jump to real handler 16661 1: 16662 EXPORT_PC() 16663 move a0, rPC # arg0 16664 move a1, rFP # arg1 16665 move a2, rSELF # arg2 16666 JAL(dvmCheckBefore) 16667 jr rBIX 16668 16669 /* ------------------------------ */ 16670 .balign 128 16671 .L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */ 16672 /* File: mips/alt_stub.S */ 16673 /* 16674 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16675 * any interesting requests and then jump to the real instruction 16676 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16677 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16678 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16679 * bail to the real handler if breakFlags==0. 16680 */ 16681 lbu a3, offThread_breakFlags(rSELF) 16682 la rBIX, dvmAsmInstructionStart + (178 * 128) 16683 lw rIBASE, offThread_curHandlerTable(rSELF) 16684 bnez a3, 1f 16685 jr rBIX # nothing to do - jump to real handler 16686 1: 16687 EXPORT_PC() 16688 move a0, rPC # arg0 16689 move a1, rFP # arg1 16690 move a2, rSELF # arg2 16691 JAL(dvmCheckBefore) 16692 jr rBIX 16693 16694 /* ------------------------------ */ 16695 .balign 128 16696 .L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */ 16697 /* File: mips/alt_stub.S */ 16698 /* 16699 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16700 * any interesting requests and then jump to the real instruction 16701 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16702 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16703 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16704 * bail to the real handler if breakFlags==0. 16705 */ 16706 lbu a3, offThread_breakFlags(rSELF) 16707 la rBIX, dvmAsmInstructionStart + (179 * 128) 16708 lw rIBASE, offThread_curHandlerTable(rSELF) 16709 bnez a3, 1f 16710 jr rBIX # nothing to do - jump to real handler 16711 1: 16712 EXPORT_PC() 16713 move a0, rPC # arg0 16714 move a1, rFP # arg1 16715 move a2, rSELF # arg2 16716 JAL(dvmCheckBefore) 16717 jr rBIX 16718 16719 /* ------------------------------ */ 16720 .balign 128 16721 .L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */ 16722 /* File: mips/alt_stub.S */ 16723 /* 16724 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16725 * any interesting requests and then jump to the real instruction 16726 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16727 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16728 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16729 * bail to the real handler if breakFlags==0. 16730 */ 16731 lbu a3, offThread_breakFlags(rSELF) 16732 la rBIX, dvmAsmInstructionStart + (180 * 128) 16733 lw rIBASE, offThread_curHandlerTable(rSELF) 16734 bnez a3, 1f 16735 jr rBIX # nothing to do - jump to real handler 16736 1: 16737 EXPORT_PC() 16738 move a0, rPC # arg0 16739 move a1, rFP # arg1 16740 move a2, rSELF # arg2 16741 JAL(dvmCheckBefore) 16742 jr rBIX 16743 16744 /* ------------------------------ */ 16745 .balign 128 16746 .L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */ 16747 /* File: mips/alt_stub.S */ 16748 /* 16749 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16750 * any interesting requests and then jump to the real instruction 16751 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16752 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16753 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16754 * bail to the real handler if breakFlags==0. 16755 */ 16756 lbu a3, offThread_breakFlags(rSELF) 16757 la rBIX, dvmAsmInstructionStart + (181 * 128) 16758 lw rIBASE, offThread_curHandlerTable(rSELF) 16759 bnez a3, 1f 16760 jr rBIX # nothing to do - jump to real handler 16761 1: 16762 EXPORT_PC() 16763 move a0, rPC # arg0 16764 move a1, rFP # arg1 16765 move a2, rSELF # arg2 16766 JAL(dvmCheckBefore) 16767 jr rBIX 16768 16769 /* ------------------------------ */ 16770 .balign 128 16771 .L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */ 16772 /* File: mips/alt_stub.S */ 16773 /* 16774 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16775 * any interesting requests and then jump to the real instruction 16776 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16777 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16778 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16779 * bail to the real handler if breakFlags==0. 16780 */ 16781 lbu a3, offThread_breakFlags(rSELF) 16782 la rBIX, dvmAsmInstructionStart + (182 * 128) 16783 lw rIBASE, offThread_curHandlerTable(rSELF) 16784 bnez a3, 1f 16785 jr rBIX # nothing to do - jump to real handler 16786 1: 16787 EXPORT_PC() 16788 move a0, rPC # arg0 16789 move a1, rFP # arg1 16790 move a2, rSELF # arg2 16791 JAL(dvmCheckBefore) 16792 jr rBIX 16793 16794 /* ------------------------------ */ 16795 .balign 128 16796 .L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */ 16797 /* File: mips/alt_stub.S */ 16798 /* 16799 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16800 * any interesting requests and then jump to the real instruction 16801 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16802 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16803 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16804 * bail to the real handler if breakFlags==0. 16805 */ 16806 lbu a3, offThread_breakFlags(rSELF) 16807 la rBIX, dvmAsmInstructionStart + (183 * 128) 16808 lw rIBASE, offThread_curHandlerTable(rSELF) 16809 bnez a3, 1f 16810 jr rBIX # nothing to do - jump to real handler 16811 1: 16812 EXPORT_PC() 16813 move a0, rPC # arg0 16814 move a1, rFP # arg1 16815 move a2, rSELF # arg2 16816 JAL(dvmCheckBefore) 16817 jr rBIX 16818 16819 /* ------------------------------ */ 16820 .balign 128 16821 .L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */ 16822 /* File: mips/alt_stub.S */ 16823 /* 16824 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16825 * any interesting requests and then jump to the real instruction 16826 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16827 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16828 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16829 * bail to the real handler if breakFlags==0. 16830 */ 16831 lbu a3, offThread_breakFlags(rSELF) 16832 la rBIX, dvmAsmInstructionStart + (184 * 128) 16833 lw rIBASE, offThread_curHandlerTable(rSELF) 16834 bnez a3, 1f 16835 jr rBIX # nothing to do - jump to real handler 16836 1: 16837 EXPORT_PC() 16838 move a0, rPC # arg0 16839 move a1, rFP # arg1 16840 move a2, rSELF # arg2 16841 JAL(dvmCheckBefore) 16842 jr rBIX 16843 16844 /* ------------------------------ */ 16845 .balign 128 16846 .L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */ 16847 /* File: mips/alt_stub.S */ 16848 /* 16849 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16850 * any interesting requests and then jump to the real instruction 16851 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16852 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16853 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16854 * bail to the real handler if breakFlags==0. 16855 */ 16856 lbu a3, offThread_breakFlags(rSELF) 16857 la rBIX, dvmAsmInstructionStart + (185 * 128) 16858 lw rIBASE, offThread_curHandlerTable(rSELF) 16859 bnez a3, 1f 16860 jr rBIX # nothing to do - jump to real handler 16861 1: 16862 EXPORT_PC() 16863 move a0, rPC # arg0 16864 move a1, rFP # arg1 16865 move a2, rSELF # arg2 16866 JAL(dvmCheckBefore) 16867 jr rBIX 16868 16869 /* ------------------------------ */ 16870 .balign 128 16871 .L_ALT_OP_USHR_INT_2ADDR: /* 0xba */ 16872 /* File: mips/alt_stub.S */ 16873 /* 16874 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16875 * any interesting requests and then jump to the real instruction 16876 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16877 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16878 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16879 * bail to the real handler if breakFlags==0. 16880 */ 16881 lbu a3, offThread_breakFlags(rSELF) 16882 la rBIX, dvmAsmInstructionStart + (186 * 128) 16883 lw rIBASE, offThread_curHandlerTable(rSELF) 16884 bnez a3, 1f 16885 jr rBIX # nothing to do - jump to real handler 16886 1: 16887 EXPORT_PC() 16888 move a0, rPC # arg0 16889 move a1, rFP # arg1 16890 move a2, rSELF # arg2 16891 JAL(dvmCheckBefore) 16892 jr rBIX 16893 16894 /* ------------------------------ */ 16895 .balign 128 16896 .L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */ 16897 /* File: mips/alt_stub.S */ 16898 /* 16899 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16900 * any interesting requests and then jump to the real instruction 16901 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16902 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16903 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16904 * bail to the real handler if breakFlags==0. 16905 */ 16906 lbu a3, offThread_breakFlags(rSELF) 16907 la rBIX, dvmAsmInstructionStart + (187 * 128) 16908 lw rIBASE, offThread_curHandlerTable(rSELF) 16909 bnez a3, 1f 16910 jr rBIX # nothing to do - jump to real handler 16911 1: 16912 EXPORT_PC() 16913 move a0, rPC # arg0 16914 move a1, rFP # arg1 16915 move a2, rSELF # arg2 16916 JAL(dvmCheckBefore) 16917 jr rBIX 16918 16919 /* ------------------------------ */ 16920 .balign 128 16921 .L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */ 16922 /* File: mips/alt_stub.S */ 16923 /* 16924 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16925 * any interesting requests and then jump to the real instruction 16926 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16927 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16928 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16929 * bail to the real handler if breakFlags==0. 16930 */ 16931 lbu a3, offThread_breakFlags(rSELF) 16932 la rBIX, dvmAsmInstructionStart + (188 * 128) 16933 lw rIBASE, offThread_curHandlerTable(rSELF) 16934 bnez a3, 1f 16935 jr rBIX # nothing to do - jump to real handler 16936 1: 16937 EXPORT_PC() 16938 move a0, rPC # arg0 16939 move a1, rFP # arg1 16940 move a2, rSELF # arg2 16941 JAL(dvmCheckBefore) 16942 jr rBIX 16943 16944 /* ------------------------------ */ 16945 .balign 128 16946 .L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */ 16947 /* File: mips/alt_stub.S */ 16948 /* 16949 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16950 * any interesting requests and then jump to the real instruction 16951 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16952 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16953 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16954 * bail to the real handler if breakFlags==0. 16955 */ 16956 lbu a3, offThread_breakFlags(rSELF) 16957 la rBIX, dvmAsmInstructionStart + (189 * 128) 16958 lw rIBASE, offThread_curHandlerTable(rSELF) 16959 bnez a3, 1f 16960 jr rBIX # nothing to do - jump to real handler 16961 1: 16962 EXPORT_PC() 16963 move a0, rPC # arg0 16964 move a1, rFP # arg1 16965 move a2, rSELF # arg2 16966 JAL(dvmCheckBefore) 16967 jr rBIX 16968 16969 /* ------------------------------ */ 16970 .balign 128 16971 .L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */ 16972 /* File: mips/alt_stub.S */ 16973 /* 16974 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16975 * any interesting requests and then jump to the real instruction 16976 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16977 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16978 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16979 * bail to the real handler if breakFlags==0. 16980 */ 16981 lbu a3, offThread_breakFlags(rSELF) 16982 la rBIX, dvmAsmInstructionStart + (190 * 128) 16983 lw rIBASE, offThread_curHandlerTable(rSELF) 16984 bnez a3, 1f 16985 jr rBIX # nothing to do - jump to real handler 16986 1: 16987 EXPORT_PC() 16988 move a0, rPC # arg0 16989 move a1, rFP # arg1 16990 move a2, rSELF # arg2 16991 JAL(dvmCheckBefore) 16992 jr rBIX 16993 16994 /* ------------------------------ */ 16995 .balign 128 16996 .L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */ 16997 /* File: mips/alt_stub.S */ 16998 /* 16999 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17000 * any interesting requests and then jump to the real instruction 17001 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17002 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17003 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17004 * bail to the real handler if breakFlags==0. 17005 */ 17006 lbu a3, offThread_breakFlags(rSELF) 17007 la rBIX, dvmAsmInstructionStart + (191 * 128) 17008 lw rIBASE, offThread_curHandlerTable(rSELF) 17009 bnez a3, 1f 17010 jr rBIX # nothing to do - jump to real handler 17011 1: 17012 EXPORT_PC() 17013 move a0, rPC # arg0 17014 move a1, rFP # arg1 17015 move a2, rSELF # arg2 17016 JAL(dvmCheckBefore) 17017 jr rBIX 17018 17019 /* ------------------------------ */ 17020 .balign 128 17021 .L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */ 17022 /* File: mips/alt_stub.S */ 17023 /* 17024 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17025 * any interesting requests and then jump to the real instruction 17026 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17027 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17028 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17029 * bail to the real handler if breakFlags==0. 17030 */ 17031 lbu a3, offThread_breakFlags(rSELF) 17032 la rBIX, dvmAsmInstructionStart + (192 * 128) 17033 lw rIBASE, offThread_curHandlerTable(rSELF) 17034 bnez a3, 1f 17035 jr rBIX # nothing to do - jump to real handler 17036 1: 17037 EXPORT_PC() 17038 move a0, rPC # arg0 17039 move a1, rFP # arg1 17040 move a2, rSELF # arg2 17041 JAL(dvmCheckBefore) 17042 jr rBIX 17043 17044 /* ------------------------------ */ 17045 .balign 128 17046 .L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */ 17047 /* File: mips/alt_stub.S */ 17048 /* 17049 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17050 * any interesting requests and then jump to the real instruction 17051 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17052 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17053 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17054 * bail to the real handler if breakFlags==0. 17055 */ 17056 lbu a3, offThread_breakFlags(rSELF) 17057 la rBIX, dvmAsmInstructionStart + (193 * 128) 17058 lw rIBASE, offThread_curHandlerTable(rSELF) 17059 bnez a3, 1f 17060 jr rBIX # nothing to do - jump to real handler 17061 1: 17062 EXPORT_PC() 17063 move a0, rPC # arg0 17064 move a1, rFP # arg1 17065 move a2, rSELF # arg2 17066 JAL(dvmCheckBefore) 17067 jr rBIX 17068 17069 /* ------------------------------ */ 17070 .balign 128 17071 .L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */ 17072 /* File: mips/alt_stub.S */ 17073 /* 17074 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17075 * any interesting requests and then jump to the real instruction 17076 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17077 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17078 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17079 * bail to the real handler if breakFlags==0. 17080 */ 17081 lbu a3, offThread_breakFlags(rSELF) 17082 la rBIX, dvmAsmInstructionStart + (194 * 128) 17083 lw rIBASE, offThread_curHandlerTable(rSELF) 17084 bnez a3, 1f 17085 jr rBIX # nothing to do - jump to real handler 17086 1: 17087 EXPORT_PC() 17088 move a0, rPC # arg0 17089 move a1, rFP # arg1 17090 move a2, rSELF # arg2 17091 JAL(dvmCheckBefore) 17092 jr rBIX 17093 17094 /* ------------------------------ */ 17095 .balign 128 17096 .L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */ 17097 /* File: mips/alt_stub.S */ 17098 /* 17099 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17100 * any interesting requests and then jump to the real instruction 17101 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17102 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17103 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17104 * bail to the real handler if breakFlags==0. 17105 */ 17106 lbu a3, offThread_breakFlags(rSELF) 17107 la rBIX, dvmAsmInstructionStart + (195 * 128) 17108 lw rIBASE, offThread_curHandlerTable(rSELF) 17109 bnez a3, 1f 17110 jr rBIX # nothing to do - jump to real handler 17111 1: 17112 EXPORT_PC() 17113 move a0, rPC # arg0 17114 move a1, rFP # arg1 17115 move a2, rSELF # arg2 17116 JAL(dvmCheckBefore) 17117 jr rBIX 17118 17119 /* ------------------------------ */ 17120 .balign 128 17121 .L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */ 17122 /* File: mips/alt_stub.S */ 17123 /* 17124 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17125 * any interesting requests and then jump to the real instruction 17126 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17127 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17128 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17129 * bail to the real handler if breakFlags==0. 17130 */ 17131 lbu a3, offThread_breakFlags(rSELF) 17132 la rBIX, dvmAsmInstructionStart + (196 * 128) 17133 lw rIBASE, offThread_curHandlerTable(rSELF) 17134 bnez a3, 1f 17135 jr rBIX # nothing to do - jump to real handler 17136 1: 17137 EXPORT_PC() 17138 move a0, rPC # arg0 17139 move a1, rFP # arg1 17140 move a2, rSELF # arg2 17141 JAL(dvmCheckBefore) 17142 jr rBIX 17143 17144 /* ------------------------------ */ 17145 .balign 128 17146 .L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */ 17147 /* File: mips/alt_stub.S */ 17148 /* 17149 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17150 * any interesting requests and then jump to the real instruction 17151 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17152 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17153 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17154 * bail to the real handler if breakFlags==0. 17155 */ 17156 lbu a3, offThread_breakFlags(rSELF) 17157 la rBIX, dvmAsmInstructionStart + (197 * 128) 17158 lw rIBASE, offThread_curHandlerTable(rSELF) 17159 bnez a3, 1f 17160 jr rBIX # nothing to do - jump to real handler 17161 1: 17162 EXPORT_PC() 17163 move a0, rPC # arg0 17164 move a1, rFP # arg1 17165 move a2, rSELF # arg2 17166 JAL(dvmCheckBefore) 17167 jr rBIX 17168 17169 /* ------------------------------ */ 17170 .balign 128 17171 .L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 17172 /* File: mips/alt_stub.S */ 17173 /* 17174 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17175 * any interesting requests and then jump to the real instruction 17176 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17177 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17178 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17179 * bail to the real handler if breakFlags==0. 17180 */ 17181 lbu a3, offThread_breakFlags(rSELF) 17182 la rBIX, dvmAsmInstructionStart + (198 * 128) 17183 lw rIBASE, offThread_curHandlerTable(rSELF) 17184 bnez a3, 1f 17185 jr rBIX # nothing to do - jump to real handler 17186 1: 17187 EXPORT_PC() 17188 move a0, rPC # arg0 17189 move a1, rFP # arg1 17190 move a2, rSELF # arg2 17191 JAL(dvmCheckBefore) 17192 jr rBIX 17193 17194 /* ------------------------------ */ 17195 .balign 128 17196 .L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 17197 /* File: mips/alt_stub.S */ 17198 /* 17199 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17200 * any interesting requests and then jump to the real instruction 17201 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17202 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17203 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17204 * bail to the real handler if breakFlags==0. 17205 */ 17206 lbu a3, offThread_breakFlags(rSELF) 17207 la rBIX, dvmAsmInstructionStart + (199 * 128) 17208 lw rIBASE, offThread_curHandlerTable(rSELF) 17209 bnez a3, 1f 17210 jr rBIX # nothing to do - jump to real handler 17211 1: 17212 EXPORT_PC() 17213 move a0, rPC # arg0 17214 move a1, rFP # arg1 17215 move a2, rSELF # arg2 17216 JAL(dvmCheckBefore) 17217 jr rBIX 17218 17219 /* ------------------------------ */ 17220 .balign 128 17221 .L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 17222 /* File: mips/alt_stub.S */ 17223 /* 17224 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17225 * any interesting requests and then jump to the real instruction 17226 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17227 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17228 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17229 * bail to the real handler if breakFlags==0. 17230 */ 17231 lbu a3, offThread_breakFlags(rSELF) 17232 la rBIX, dvmAsmInstructionStart + (200 * 128) 17233 lw rIBASE, offThread_curHandlerTable(rSELF) 17234 bnez a3, 1f 17235 jr rBIX # nothing to do - jump to real handler 17236 1: 17237 EXPORT_PC() 17238 move a0, rPC # arg0 17239 move a1, rFP # arg1 17240 move a2, rSELF # arg2 17241 JAL(dvmCheckBefore) 17242 jr rBIX 17243 17244 /* ------------------------------ */ 17245 .balign 128 17246 .L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 17247 /* File: mips/alt_stub.S */ 17248 /* 17249 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17250 * any interesting requests and then jump to the real instruction 17251 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17252 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17253 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17254 * bail to the real handler if breakFlags==0. 17255 */ 17256 lbu a3, offThread_breakFlags(rSELF) 17257 la rBIX, dvmAsmInstructionStart + (201 * 128) 17258 lw rIBASE, offThread_curHandlerTable(rSELF) 17259 bnez a3, 1f 17260 jr rBIX # nothing to do - jump to real handler 17261 1: 17262 EXPORT_PC() 17263 move a0, rPC # arg0 17264 move a1, rFP # arg1 17265 move a2, rSELF # arg2 17266 JAL(dvmCheckBefore) 17267 jr rBIX 17268 17269 /* ------------------------------ */ 17270 .balign 128 17271 .L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */ 17272 /* File: mips/alt_stub.S */ 17273 /* 17274 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17275 * any interesting requests and then jump to the real instruction 17276 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17277 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17278 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17279 * bail to the real handler if breakFlags==0. 17280 */ 17281 lbu a3, offThread_breakFlags(rSELF) 17282 la rBIX, dvmAsmInstructionStart + (202 * 128) 17283 lw rIBASE, offThread_curHandlerTable(rSELF) 17284 bnez a3, 1f 17285 jr rBIX # nothing to do - jump to real handler 17286 1: 17287 EXPORT_PC() 17288 move a0, rPC # arg0 17289 move a1, rFP # arg1 17290 move a2, rSELF # arg2 17291 JAL(dvmCheckBefore) 17292 jr rBIX 17293 17294 /* ------------------------------ */ 17295 .balign 128 17296 .L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 17297 /* File: mips/alt_stub.S */ 17298 /* 17299 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17300 * any interesting requests and then jump to the real instruction 17301 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17302 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17303 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17304 * bail to the real handler if breakFlags==0. 17305 */ 17306 lbu a3, offThread_breakFlags(rSELF) 17307 la rBIX, dvmAsmInstructionStart + (203 * 128) 17308 lw rIBASE, offThread_curHandlerTable(rSELF) 17309 bnez a3, 1f 17310 jr rBIX # nothing to do - jump to real handler 17311 1: 17312 EXPORT_PC() 17313 move a0, rPC # arg0 17314 move a1, rFP # arg1 17315 move a2, rSELF # arg2 17316 JAL(dvmCheckBefore) 17317 jr rBIX 17318 17319 /* ------------------------------ */ 17320 .balign 128 17321 .L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 17322 /* File: mips/alt_stub.S */ 17323 /* 17324 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17325 * any interesting requests and then jump to the real instruction 17326 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17327 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17328 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17329 * bail to the real handler if breakFlags==0. 17330 */ 17331 lbu a3, offThread_breakFlags(rSELF) 17332 la rBIX, dvmAsmInstructionStart + (204 * 128) 17333 lw rIBASE, offThread_curHandlerTable(rSELF) 17334 bnez a3, 1f 17335 jr rBIX # nothing to do - jump to real handler 17336 1: 17337 EXPORT_PC() 17338 move a0, rPC # arg0 17339 move a1, rFP # arg1 17340 move a2, rSELF # arg2 17341 JAL(dvmCheckBefore) 17342 jr rBIX 17343 17344 /* ------------------------------ */ 17345 .balign 128 17346 .L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 17347 /* File: mips/alt_stub.S */ 17348 /* 17349 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17350 * any interesting requests and then jump to the real instruction 17351 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17352 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17353 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17354 * bail to the real handler if breakFlags==0. 17355 */ 17356 lbu a3, offThread_breakFlags(rSELF) 17357 la rBIX, dvmAsmInstructionStart + (205 * 128) 17358 lw rIBASE, offThread_curHandlerTable(rSELF) 17359 bnez a3, 1f 17360 jr rBIX # nothing to do - jump to real handler 17361 1: 17362 EXPORT_PC() 17363 move a0, rPC # arg0 17364 move a1, rFP # arg1 17365 move a2, rSELF # arg2 17366 JAL(dvmCheckBefore) 17367 jr rBIX 17368 17369 /* ------------------------------ */ 17370 .balign 128 17371 .L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 17372 /* File: mips/alt_stub.S */ 17373 /* 17374 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17375 * any interesting requests and then jump to the real instruction 17376 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17377 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17378 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17379 * bail to the real handler if breakFlags==0. 17380 */ 17381 lbu a3, offThread_breakFlags(rSELF) 17382 la rBIX, dvmAsmInstructionStart + (206 * 128) 17383 lw rIBASE, offThread_curHandlerTable(rSELF) 17384 bnez a3, 1f 17385 jr rBIX # nothing to do - jump to real handler 17386 1: 17387 EXPORT_PC() 17388 move a0, rPC # arg0 17389 move a1, rFP # arg1 17390 move a2, rSELF # arg2 17391 JAL(dvmCheckBefore) 17392 jr rBIX 17393 17394 /* ------------------------------ */ 17395 .balign 128 17396 .L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 17397 /* File: mips/alt_stub.S */ 17398 /* 17399 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17400 * any interesting requests and then jump to the real instruction 17401 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17402 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17403 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17404 * bail to the real handler if breakFlags==0. 17405 */ 17406 lbu a3, offThread_breakFlags(rSELF) 17407 la rBIX, dvmAsmInstructionStart + (207 * 128) 17408 lw rIBASE, offThread_curHandlerTable(rSELF) 17409 bnez a3, 1f 17410 jr rBIX # nothing to do - jump to real handler 17411 1: 17412 EXPORT_PC() 17413 move a0, rPC # arg0 17414 move a1, rFP # arg1 17415 move a2, rSELF # arg2 17416 JAL(dvmCheckBefore) 17417 jr rBIX 17418 17419 /* ------------------------------ */ 17420 .balign 128 17421 .L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */ 17422 /* File: mips/alt_stub.S */ 17423 /* 17424 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17425 * any interesting requests and then jump to the real instruction 17426 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17427 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17428 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17429 * bail to the real handler if breakFlags==0. 17430 */ 17431 lbu a3, offThread_breakFlags(rSELF) 17432 la rBIX, dvmAsmInstructionStart + (208 * 128) 17433 lw rIBASE, offThread_curHandlerTable(rSELF) 17434 bnez a3, 1f 17435 jr rBIX # nothing to do - jump to real handler 17436 1: 17437 EXPORT_PC() 17438 move a0, rPC # arg0 17439 move a1, rFP # arg1 17440 move a2, rSELF # arg2 17441 JAL(dvmCheckBefore) 17442 jr rBIX 17443 17444 /* ------------------------------ */ 17445 .balign 128 17446 .L_ALT_OP_RSUB_INT: /* 0xd1 */ 17447 /* File: mips/alt_stub.S */ 17448 /* 17449 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17450 * any interesting requests and then jump to the real instruction 17451 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17452 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17453 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17454 * bail to the real handler if breakFlags==0. 17455 */ 17456 lbu a3, offThread_breakFlags(rSELF) 17457 la rBIX, dvmAsmInstructionStart + (209 * 128) 17458 lw rIBASE, offThread_curHandlerTable(rSELF) 17459 bnez a3, 1f 17460 jr rBIX # nothing to do - jump to real handler 17461 1: 17462 EXPORT_PC() 17463 move a0, rPC # arg0 17464 move a1, rFP # arg1 17465 move a2, rSELF # arg2 17466 JAL(dvmCheckBefore) 17467 jr rBIX 17468 17469 /* ------------------------------ */ 17470 .balign 128 17471 .L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */ 17472 /* File: mips/alt_stub.S */ 17473 /* 17474 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17475 * any interesting requests and then jump to the real instruction 17476 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17477 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17478 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17479 * bail to the real handler if breakFlags==0. 17480 */ 17481 lbu a3, offThread_breakFlags(rSELF) 17482 la rBIX, dvmAsmInstructionStart + (210 * 128) 17483 lw rIBASE, offThread_curHandlerTable(rSELF) 17484 bnez a3, 1f 17485 jr rBIX # nothing to do - jump to real handler 17486 1: 17487 EXPORT_PC() 17488 move a0, rPC # arg0 17489 move a1, rFP # arg1 17490 move a2, rSELF # arg2 17491 JAL(dvmCheckBefore) 17492 jr rBIX 17493 17494 /* ------------------------------ */ 17495 .balign 128 17496 .L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */ 17497 /* File: mips/alt_stub.S */ 17498 /* 17499 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17500 * any interesting requests and then jump to the real instruction 17501 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17502 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17503 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17504 * bail to the real handler if breakFlags==0. 17505 */ 17506 lbu a3, offThread_breakFlags(rSELF) 17507 la rBIX, dvmAsmInstructionStart + (211 * 128) 17508 lw rIBASE, offThread_curHandlerTable(rSELF) 17509 bnez a3, 1f 17510 jr rBIX # nothing to do - jump to real handler 17511 1: 17512 EXPORT_PC() 17513 move a0, rPC # arg0 17514 move a1, rFP # arg1 17515 move a2, rSELF # arg2 17516 JAL(dvmCheckBefore) 17517 jr rBIX 17518 17519 /* ------------------------------ */ 17520 .balign 128 17521 .L_ALT_OP_REM_INT_LIT16: /* 0xd4 */ 17522 /* File: mips/alt_stub.S */ 17523 /* 17524 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17525 * any interesting requests and then jump to the real instruction 17526 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17527 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17528 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17529 * bail to the real handler if breakFlags==0. 17530 */ 17531 lbu a3, offThread_breakFlags(rSELF) 17532 la rBIX, dvmAsmInstructionStart + (212 * 128) 17533 lw rIBASE, offThread_curHandlerTable(rSELF) 17534 bnez a3, 1f 17535 jr rBIX # nothing to do - jump to real handler 17536 1: 17537 EXPORT_PC() 17538 move a0, rPC # arg0 17539 move a1, rFP # arg1 17540 move a2, rSELF # arg2 17541 JAL(dvmCheckBefore) 17542 jr rBIX 17543 17544 /* ------------------------------ */ 17545 .balign 128 17546 .L_ALT_OP_AND_INT_LIT16: /* 0xd5 */ 17547 /* File: mips/alt_stub.S */ 17548 /* 17549 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17550 * any interesting requests and then jump to the real instruction 17551 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17552 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17553 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17554 * bail to the real handler if breakFlags==0. 17555 */ 17556 lbu a3, offThread_breakFlags(rSELF) 17557 la rBIX, dvmAsmInstructionStart + (213 * 128) 17558 lw rIBASE, offThread_curHandlerTable(rSELF) 17559 bnez a3, 1f 17560 jr rBIX # nothing to do - jump to real handler 17561 1: 17562 EXPORT_PC() 17563 move a0, rPC # arg0 17564 move a1, rFP # arg1 17565 move a2, rSELF # arg2 17566 JAL(dvmCheckBefore) 17567 jr rBIX 17568 17569 /* ------------------------------ */ 17570 .balign 128 17571 .L_ALT_OP_OR_INT_LIT16: /* 0xd6 */ 17572 /* File: mips/alt_stub.S */ 17573 /* 17574 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17575 * any interesting requests and then jump to the real instruction 17576 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17577 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17578 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17579 * bail to the real handler if breakFlags==0. 17580 */ 17581 lbu a3, offThread_breakFlags(rSELF) 17582 la rBIX, dvmAsmInstructionStart + (214 * 128) 17583 lw rIBASE, offThread_curHandlerTable(rSELF) 17584 bnez a3, 1f 17585 jr rBIX # nothing to do - jump to real handler 17586 1: 17587 EXPORT_PC() 17588 move a0, rPC # arg0 17589 move a1, rFP # arg1 17590 move a2, rSELF # arg2 17591 JAL(dvmCheckBefore) 17592 jr rBIX 17593 17594 /* ------------------------------ */ 17595 .balign 128 17596 .L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */ 17597 /* File: mips/alt_stub.S */ 17598 /* 17599 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17600 * any interesting requests and then jump to the real instruction 17601 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17602 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17603 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17604 * bail to the real handler if breakFlags==0. 17605 */ 17606 lbu a3, offThread_breakFlags(rSELF) 17607 la rBIX, dvmAsmInstructionStart + (215 * 128) 17608 lw rIBASE, offThread_curHandlerTable(rSELF) 17609 bnez a3, 1f 17610 jr rBIX # nothing to do - jump to real handler 17611 1: 17612 EXPORT_PC() 17613 move a0, rPC # arg0 17614 move a1, rFP # arg1 17615 move a2, rSELF # arg2 17616 JAL(dvmCheckBefore) 17617 jr rBIX 17618 17619 /* ------------------------------ */ 17620 .balign 128 17621 .L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */ 17622 /* File: mips/alt_stub.S */ 17623 /* 17624 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17625 * any interesting requests and then jump to the real instruction 17626 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17627 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17628 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17629 * bail to the real handler if breakFlags==0. 17630 */ 17631 lbu a3, offThread_breakFlags(rSELF) 17632 la rBIX, dvmAsmInstructionStart + (216 * 128) 17633 lw rIBASE, offThread_curHandlerTable(rSELF) 17634 bnez a3, 1f 17635 jr rBIX # nothing to do - jump to real handler 17636 1: 17637 EXPORT_PC() 17638 move a0, rPC # arg0 17639 move a1, rFP # arg1 17640 move a2, rSELF # arg2 17641 JAL(dvmCheckBefore) 17642 jr rBIX 17643 17644 /* ------------------------------ */ 17645 .balign 128 17646 .L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */ 17647 /* File: mips/alt_stub.S */ 17648 /* 17649 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17650 * any interesting requests and then jump to the real instruction 17651 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17652 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17653 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17654 * bail to the real handler if breakFlags==0. 17655 */ 17656 lbu a3, offThread_breakFlags(rSELF) 17657 la rBIX, dvmAsmInstructionStart + (217 * 128) 17658 lw rIBASE, offThread_curHandlerTable(rSELF) 17659 bnez a3, 1f 17660 jr rBIX # nothing to do - jump to real handler 17661 1: 17662 EXPORT_PC() 17663 move a0, rPC # arg0 17664 move a1, rFP # arg1 17665 move a2, rSELF # arg2 17666 JAL(dvmCheckBefore) 17667 jr rBIX 17668 17669 /* ------------------------------ */ 17670 .balign 128 17671 .L_ALT_OP_MUL_INT_LIT8: /* 0xda */ 17672 /* File: mips/alt_stub.S */ 17673 /* 17674 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17675 * any interesting requests and then jump to the real instruction 17676 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17677 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17678 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17679 * bail to the real handler if breakFlags==0. 17680 */ 17681 lbu a3, offThread_breakFlags(rSELF) 17682 la rBIX, dvmAsmInstructionStart + (218 * 128) 17683 lw rIBASE, offThread_curHandlerTable(rSELF) 17684 bnez a3, 1f 17685 jr rBIX # nothing to do - jump to real handler 17686 1: 17687 EXPORT_PC() 17688 move a0, rPC # arg0 17689 move a1, rFP # arg1 17690 move a2, rSELF # arg2 17691 JAL(dvmCheckBefore) 17692 jr rBIX 17693 17694 /* ------------------------------ */ 17695 .balign 128 17696 .L_ALT_OP_DIV_INT_LIT8: /* 0xdb */ 17697 /* File: mips/alt_stub.S */ 17698 /* 17699 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17700 * any interesting requests and then jump to the real instruction 17701 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17702 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17703 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17704 * bail to the real handler if breakFlags==0. 17705 */ 17706 lbu a3, offThread_breakFlags(rSELF) 17707 la rBIX, dvmAsmInstructionStart + (219 * 128) 17708 lw rIBASE, offThread_curHandlerTable(rSELF) 17709 bnez a3, 1f 17710 jr rBIX # nothing to do - jump to real handler 17711 1: 17712 EXPORT_PC() 17713 move a0, rPC # arg0 17714 move a1, rFP # arg1 17715 move a2, rSELF # arg2 17716 JAL(dvmCheckBefore) 17717 jr rBIX 17718 17719 /* ------------------------------ */ 17720 .balign 128 17721 .L_ALT_OP_REM_INT_LIT8: /* 0xdc */ 17722 /* File: mips/alt_stub.S */ 17723 /* 17724 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17725 * any interesting requests and then jump to the real instruction 17726 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17727 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17728 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17729 * bail to the real handler if breakFlags==0. 17730 */ 17731 lbu a3, offThread_breakFlags(rSELF) 17732 la rBIX, dvmAsmInstructionStart + (220 * 128) 17733 lw rIBASE, offThread_curHandlerTable(rSELF) 17734 bnez a3, 1f 17735 jr rBIX # nothing to do - jump to real handler 17736 1: 17737 EXPORT_PC() 17738 move a0, rPC # arg0 17739 move a1, rFP # arg1 17740 move a2, rSELF # arg2 17741 JAL(dvmCheckBefore) 17742 jr rBIX 17743 17744 /* ------------------------------ */ 17745 .balign 128 17746 .L_ALT_OP_AND_INT_LIT8: /* 0xdd */ 17747 /* File: mips/alt_stub.S */ 17748 /* 17749 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17750 * any interesting requests and then jump to the real instruction 17751 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17752 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17753 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17754 * bail to the real handler if breakFlags==0. 17755 */ 17756 lbu a3, offThread_breakFlags(rSELF) 17757 la rBIX, dvmAsmInstructionStart + (221 * 128) 17758 lw rIBASE, offThread_curHandlerTable(rSELF) 17759 bnez a3, 1f 17760 jr rBIX # nothing to do - jump to real handler 17761 1: 17762 EXPORT_PC() 17763 move a0, rPC # arg0 17764 move a1, rFP # arg1 17765 move a2, rSELF # arg2 17766 JAL(dvmCheckBefore) 17767 jr rBIX 17768 17769 /* ------------------------------ */ 17770 .balign 128 17771 .L_ALT_OP_OR_INT_LIT8: /* 0xde */ 17772 /* File: mips/alt_stub.S */ 17773 /* 17774 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17775 * any interesting requests and then jump to the real instruction 17776 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17777 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17778 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17779 * bail to the real handler if breakFlags==0. 17780 */ 17781 lbu a3, offThread_breakFlags(rSELF) 17782 la rBIX, dvmAsmInstructionStart + (222 * 128) 17783 lw rIBASE, offThread_curHandlerTable(rSELF) 17784 bnez a3, 1f 17785 jr rBIX # nothing to do - jump to real handler 17786 1: 17787 EXPORT_PC() 17788 move a0, rPC # arg0 17789 move a1, rFP # arg1 17790 move a2, rSELF # arg2 17791 JAL(dvmCheckBefore) 17792 jr rBIX 17793 17794 /* ------------------------------ */ 17795 .balign 128 17796 .L_ALT_OP_XOR_INT_LIT8: /* 0xdf */ 17797 /* File: mips/alt_stub.S */ 17798 /* 17799 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17800 * any interesting requests and then jump to the real instruction 17801 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17802 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17803 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17804 * bail to the real handler if breakFlags==0. 17805 */ 17806 lbu a3, offThread_breakFlags(rSELF) 17807 la rBIX, dvmAsmInstructionStart + (223 * 128) 17808 lw rIBASE, offThread_curHandlerTable(rSELF) 17809 bnez a3, 1f 17810 jr rBIX # nothing to do - jump to real handler 17811 1: 17812 EXPORT_PC() 17813 move a0, rPC # arg0 17814 move a1, rFP # arg1 17815 move a2, rSELF # arg2 17816 JAL(dvmCheckBefore) 17817 jr rBIX 17818 17819 /* ------------------------------ */ 17820 .balign 128 17821 .L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */ 17822 /* File: mips/alt_stub.S */ 17823 /* 17824 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17825 * any interesting requests and then jump to the real instruction 17826 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17827 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17828 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17829 * bail to the real handler if breakFlags==0. 17830 */ 17831 lbu a3, offThread_breakFlags(rSELF) 17832 la rBIX, dvmAsmInstructionStart + (224 * 128) 17833 lw rIBASE, offThread_curHandlerTable(rSELF) 17834 bnez a3, 1f 17835 jr rBIX # nothing to do - jump to real handler 17836 1: 17837 EXPORT_PC() 17838 move a0, rPC # arg0 17839 move a1, rFP # arg1 17840 move a2, rSELF # arg2 17841 JAL(dvmCheckBefore) 17842 jr rBIX 17843 17844 /* ------------------------------ */ 17845 .balign 128 17846 .L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */ 17847 /* File: mips/alt_stub.S */ 17848 /* 17849 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17850 * any interesting requests and then jump to the real instruction 17851 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17852 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17853 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17854 * bail to the real handler if breakFlags==0. 17855 */ 17856 lbu a3, offThread_breakFlags(rSELF) 17857 la rBIX, dvmAsmInstructionStart + (225 * 128) 17858 lw rIBASE, offThread_curHandlerTable(rSELF) 17859 bnez a3, 1f 17860 jr rBIX # nothing to do - jump to real handler 17861 1: 17862 EXPORT_PC() 17863 move a0, rPC # arg0 17864 move a1, rFP # arg1 17865 move a2, rSELF # arg2 17866 JAL(dvmCheckBefore) 17867 jr rBIX 17868 17869 /* ------------------------------ */ 17870 .balign 128 17871 .L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */ 17872 /* File: mips/alt_stub.S */ 17873 /* 17874 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17875 * any interesting requests and then jump to the real instruction 17876 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17877 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17878 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17879 * bail to the real handler if breakFlags==0. 17880 */ 17881 lbu a3, offThread_breakFlags(rSELF) 17882 la rBIX, dvmAsmInstructionStart + (226 * 128) 17883 lw rIBASE, offThread_curHandlerTable(rSELF) 17884 bnez a3, 1f 17885 jr rBIX # nothing to do - jump to real handler 17886 1: 17887 EXPORT_PC() 17888 move a0, rPC # arg0 17889 move a1, rFP # arg1 17890 move a2, rSELF # arg2 17891 JAL(dvmCheckBefore) 17892 jr rBIX 17893 17894 /* ------------------------------ */ 17895 .balign 128 17896 .L_ALT_OP_IGET_VOLATILE: /* 0xe3 */ 17897 /* File: mips/alt_stub.S */ 17898 /* 17899 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17900 * any interesting requests and then jump to the real instruction 17901 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17902 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17903 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17904 * bail to the real handler if breakFlags==0. 17905 */ 17906 lbu a3, offThread_breakFlags(rSELF) 17907 la rBIX, dvmAsmInstructionStart + (227 * 128) 17908 lw rIBASE, offThread_curHandlerTable(rSELF) 17909 bnez a3, 1f 17910 jr rBIX # nothing to do - jump to real handler 17911 1: 17912 EXPORT_PC() 17913 move a0, rPC # arg0 17914 move a1, rFP # arg1 17915 move a2, rSELF # arg2 17916 JAL(dvmCheckBefore) 17917 jr rBIX 17918 17919 /* ------------------------------ */ 17920 .balign 128 17921 .L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */ 17922 /* File: mips/alt_stub.S */ 17923 /* 17924 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17925 * any interesting requests and then jump to the real instruction 17926 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17927 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17928 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17929 * bail to the real handler if breakFlags==0. 17930 */ 17931 lbu a3, offThread_breakFlags(rSELF) 17932 la rBIX, dvmAsmInstructionStart + (228 * 128) 17933 lw rIBASE, offThread_curHandlerTable(rSELF) 17934 bnez a3, 1f 17935 jr rBIX # nothing to do - jump to real handler 17936 1: 17937 EXPORT_PC() 17938 move a0, rPC # arg0 17939 move a1, rFP # arg1 17940 move a2, rSELF # arg2 17941 JAL(dvmCheckBefore) 17942 jr rBIX 17943 17944 /* ------------------------------ */ 17945 .balign 128 17946 .L_ALT_OP_SGET_VOLATILE: /* 0xe5 */ 17947 /* File: mips/alt_stub.S */ 17948 /* 17949 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17950 * any interesting requests and then jump to the real instruction 17951 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17952 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17953 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17954 * bail to the real handler if breakFlags==0. 17955 */ 17956 lbu a3, offThread_breakFlags(rSELF) 17957 la rBIX, dvmAsmInstructionStart + (229 * 128) 17958 lw rIBASE, offThread_curHandlerTable(rSELF) 17959 bnez a3, 1f 17960 jr rBIX # nothing to do - jump to real handler 17961 1: 17962 EXPORT_PC() 17963 move a0, rPC # arg0 17964 move a1, rFP # arg1 17965 move a2, rSELF # arg2 17966 JAL(dvmCheckBefore) 17967 jr rBIX 17968 17969 /* ------------------------------ */ 17970 .balign 128 17971 .L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */ 17972 /* File: mips/alt_stub.S */ 17973 /* 17974 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17975 * any interesting requests and then jump to the real instruction 17976 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17977 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17978 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17979 * bail to the real handler if breakFlags==0. 17980 */ 17981 lbu a3, offThread_breakFlags(rSELF) 17982 la rBIX, dvmAsmInstructionStart + (230 * 128) 17983 lw rIBASE, offThread_curHandlerTable(rSELF) 17984 bnez a3, 1f 17985 jr rBIX # nothing to do - jump to real handler 17986 1: 17987 EXPORT_PC() 17988 move a0, rPC # arg0 17989 move a1, rFP # arg1 17990 move a2, rSELF # arg2 17991 JAL(dvmCheckBefore) 17992 jr rBIX 17993 17994 /* ------------------------------ */ 17995 .balign 128 17996 .L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 17997 /* File: mips/alt_stub.S */ 17998 /* 17999 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18000 * any interesting requests and then jump to the real instruction 18001 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18002 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18003 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18004 * bail to the real handler if breakFlags==0. 18005 */ 18006 lbu a3, offThread_breakFlags(rSELF) 18007 la rBIX, dvmAsmInstructionStart + (231 * 128) 18008 lw rIBASE, offThread_curHandlerTable(rSELF) 18009 bnez a3, 1f 18010 jr rBIX # nothing to do - jump to real handler 18011 1: 18012 EXPORT_PC() 18013 move a0, rPC # arg0 18014 move a1, rFP # arg1 18015 move a2, rSELF # arg2 18016 JAL(dvmCheckBefore) 18017 jr rBIX 18018 18019 /* ------------------------------ */ 18020 .balign 128 18021 .L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 18022 /* File: mips/alt_stub.S */ 18023 /* 18024 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18025 * any interesting requests and then jump to the real instruction 18026 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18027 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18028 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18029 * bail to the real handler if breakFlags==0. 18030 */ 18031 lbu a3, offThread_breakFlags(rSELF) 18032 la rBIX, dvmAsmInstructionStart + (232 * 128) 18033 lw rIBASE, offThread_curHandlerTable(rSELF) 18034 bnez a3, 1f 18035 jr rBIX # nothing to do - jump to real handler 18036 1: 18037 EXPORT_PC() 18038 move a0, rPC # arg0 18039 move a1, rFP # arg1 18040 move a2, rSELF # arg2 18041 JAL(dvmCheckBefore) 18042 jr rBIX 18043 18044 /* ------------------------------ */ 18045 .balign 128 18046 .L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 18047 /* File: mips/alt_stub.S */ 18048 /* 18049 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18050 * any interesting requests and then jump to the real instruction 18051 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18052 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18053 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18054 * bail to the real handler if breakFlags==0. 18055 */ 18056 lbu a3, offThread_breakFlags(rSELF) 18057 la rBIX, dvmAsmInstructionStart + (233 * 128) 18058 lw rIBASE, offThread_curHandlerTable(rSELF) 18059 bnez a3, 1f 18060 jr rBIX # nothing to do - jump to real handler 18061 1: 18062 EXPORT_PC() 18063 move a0, rPC # arg0 18064 move a1, rFP # arg1 18065 move a2, rSELF # arg2 18066 JAL(dvmCheckBefore) 18067 jr rBIX 18068 18069 /* ------------------------------ */ 18070 .balign 128 18071 .L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */ 18072 /* File: mips/alt_stub.S */ 18073 /* 18074 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18075 * any interesting requests and then jump to the real instruction 18076 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18077 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18078 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18079 * bail to the real handler if breakFlags==0. 18080 */ 18081 lbu a3, offThread_breakFlags(rSELF) 18082 la rBIX, dvmAsmInstructionStart + (234 * 128) 18083 lw rIBASE, offThread_curHandlerTable(rSELF) 18084 bnez a3, 1f 18085 jr rBIX # nothing to do - jump to real handler 18086 1: 18087 EXPORT_PC() 18088 move a0, rPC # arg0 18089 move a1, rFP # arg1 18090 move a2, rSELF # arg2 18091 JAL(dvmCheckBefore) 18092 jr rBIX 18093 18094 /* ------------------------------ */ 18095 .balign 128 18096 .L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 18097 /* File: mips/alt_stub.S */ 18098 /* 18099 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18100 * any interesting requests and then jump to the real instruction 18101 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18102 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18103 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18104 * bail to the real handler if breakFlags==0. 18105 */ 18106 lbu a3, offThread_breakFlags(rSELF) 18107 la rBIX, dvmAsmInstructionStart + (235 * 128) 18108 lw rIBASE, offThread_curHandlerTable(rSELF) 18109 bnez a3, 1f 18110 jr rBIX # nothing to do - jump to real handler 18111 1: 18112 EXPORT_PC() 18113 move a0, rPC # arg0 18114 move a1, rFP # arg1 18115 move a2, rSELF # arg2 18116 JAL(dvmCheckBefore) 18117 jr rBIX 18118 18119 /* ------------------------------ */ 18120 .balign 128 18121 .L_ALT_OP_BREAKPOINT: /* 0xec */ 18122 /* File: mips/alt_stub.S */ 18123 /* 18124 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18125 * any interesting requests and then jump to the real instruction 18126 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18127 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18128 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18129 * bail to the real handler if breakFlags==0. 18130 */ 18131 lbu a3, offThread_breakFlags(rSELF) 18132 la rBIX, dvmAsmInstructionStart + (236 * 128) 18133 lw rIBASE, offThread_curHandlerTable(rSELF) 18134 bnez a3, 1f 18135 jr rBIX # nothing to do - jump to real handler 18136 1: 18137 EXPORT_PC() 18138 move a0, rPC # arg0 18139 move a1, rFP # arg1 18140 move a2, rSELF # arg2 18141 JAL(dvmCheckBefore) 18142 jr rBIX 18143 18144 /* ------------------------------ */ 18145 .balign 128 18146 .L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 18147 /* File: mips/alt_stub.S */ 18148 /* 18149 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18150 * any interesting requests and then jump to the real instruction 18151 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18152 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18153 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18154 * bail to the real handler if breakFlags==0. 18155 */ 18156 lbu a3, offThread_breakFlags(rSELF) 18157 la rBIX, dvmAsmInstructionStart + (237 * 128) 18158 lw rIBASE, offThread_curHandlerTable(rSELF) 18159 bnez a3, 1f 18160 jr rBIX # nothing to do - jump to real handler 18161 1: 18162 EXPORT_PC() 18163 move a0, rPC # arg0 18164 move a1, rFP # arg1 18165 move a2, rSELF # arg2 18166 JAL(dvmCheckBefore) 18167 jr rBIX 18168 18169 /* ------------------------------ */ 18170 .balign 128 18171 .L_ALT_OP_EXECUTE_INLINE: /* 0xee */ 18172 /* File: mips/alt_stub.S */ 18173 /* 18174 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18175 * any interesting requests and then jump to the real instruction 18176 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18177 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18178 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18179 * bail to the real handler if breakFlags==0. 18180 */ 18181 lbu a3, offThread_breakFlags(rSELF) 18182 la rBIX, dvmAsmInstructionStart + (238 * 128) 18183 lw rIBASE, offThread_curHandlerTable(rSELF) 18184 bnez a3, 1f 18185 jr rBIX # nothing to do - jump to real handler 18186 1: 18187 EXPORT_PC() 18188 move a0, rPC # arg0 18189 move a1, rFP # arg1 18190 move a2, rSELF # arg2 18191 JAL(dvmCheckBefore) 18192 jr rBIX 18193 18194 /* ------------------------------ */ 18195 .balign 128 18196 .L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 18197 /* File: mips/alt_stub.S */ 18198 /* 18199 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18200 * any interesting requests and then jump to the real instruction 18201 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18202 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18203 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18204 * bail to the real handler if breakFlags==0. 18205 */ 18206 lbu a3, offThread_breakFlags(rSELF) 18207 la rBIX, dvmAsmInstructionStart + (239 * 128) 18208 lw rIBASE, offThread_curHandlerTable(rSELF) 18209 bnez a3, 1f 18210 jr rBIX # nothing to do - jump to real handler 18211 1: 18212 EXPORT_PC() 18213 move a0, rPC # arg0 18214 move a1, rFP # arg1 18215 move a2, rSELF # arg2 18216 JAL(dvmCheckBefore) 18217 jr rBIX 18218 18219 /* ------------------------------ */ 18220 .balign 128 18221 .L_ALT_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */ 18222 /* File: mips/alt_stub.S */ 18223 /* 18224 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18225 * any interesting requests and then jump to the real instruction 18226 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18227 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18228 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18229 * bail to the real handler if breakFlags==0. 18230 */ 18231 lbu a3, offThread_breakFlags(rSELF) 18232 la rBIX, dvmAsmInstructionStart + (240 * 128) 18233 lw rIBASE, offThread_curHandlerTable(rSELF) 18234 bnez a3, 1f 18235 jr rBIX # nothing to do - jump to real handler 18236 1: 18237 EXPORT_PC() 18238 move a0, rPC # arg0 18239 move a1, rFP # arg1 18240 move a2, rSELF # arg2 18241 JAL(dvmCheckBefore) 18242 jr rBIX 18243 18244 /* ------------------------------ */ 18245 .balign 128 18246 .L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 18247 /* File: mips/alt_stub.S */ 18248 /* 18249 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18250 * any interesting requests and then jump to the real instruction 18251 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18252 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18253 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18254 * bail to the real handler if breakFlags==0. 18255 */ 18256 lbu a3, offThread_breakFlags(rSELF) 18257 la rBIX, dvmAsmInstructionStart + (241 * 128) 18258 lw rIBASE, offThread_curHandlerTable(rSELF) 18259 bnez a3, 1f 18260 jr rBIX # nothing to do - jump to real handler 18261 1: 18262 EXPORT_PC() 18263 move a0, rPC # arg0 18264 move a1, rFP # arg1 18265 move a2, rSELF # arg2 18266 JAL(dvmCheckBefore) 18267 jr rBIX 18268 18269 /* ------------------------------ */ 18270 .balign 128 18271 .L_ALT_OP_IGET_QUICK: /* 0xf2 */ 18272 /* File: mips/alt_stub.S */ 18273 /* 18274 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18275 * any interesting requests and then jump to the real instruction 18276 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18277 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18278 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18279 * bail to the real handler if breakFlags==0. 18280 */ 18281 lbu a3, offThread_breakFlags(rSELF) 18282 la rBIX, dvmAsmInstructionStart + (242 * 128) 18283 lw rIBASE, offThread_curHandlerTable(rSELF) 18284 bnez a3, 1f 18285 jr rBIX # nothing to do - jump to real handler 18286 1: 18287 EXPORT_PC() 18288 move a0, rPC # arg0 18289 move a1, rFP # arg1 18290 move a2, rSELF # arg2 18291 JAL(dvmCheckBefore) 18292 jr rBIX 18293 18294 /* ------------------------------ */ 18295 .balign 128 18296 .L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */ 18297 /* File: mips/alt_stub.S */ 18298 /* 18299 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18300 * any interesting requests and then jump to the real instruction 18301 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18302 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18303 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18304 * bail to the real handler if breakFlags==0. 18305 */ 18306 lbu a3, offThread_breakFlags(rSELF) 18307 la rBIX, dvmAsmInstructionStart + (243 * 128) 18308 lw rIBASE, offThread_curHandlerTable(rSELF) 18309 bnez a3, 1f 18310 jr rBIX # nothing to do - jump to real handler 18311 1: 18312 EXPORT_PC() 18313 move a0, rPC # arg0 18314 move a1, rFP # arg1 18315 move a2, rSELF # arg2 18316 JAL(dvmCheckBefore) 18317 jr rBIX 18318 18319 /* ------------------------------ */ 18320 .balign 128 18321 .L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 18322 /* File: mips/alt_stub.S */ 18323 /* 18324 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18325 * any interesting requests and then jump to the real instruction 18326 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18327 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18328 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18329 * bail to the real handler if breakFlags==0. 18330 */ 18331 lbu a3, offThread_breakFlags(rSELF) 18332 la rBIX, dvmAsmInstructionStart + (244 * 128) 18333 lw rIBASE, offThread_curHandlerTable(rSELF) 18334 bnez a3, 1f 18335 jr rBIX # nothing to do - jump to real handler 18336 1: 18337 EXPORT_PC() 18338 move a0, rPC # arg0 18339 move a1, rFP # arg1 18340 move a2, rSELF # arg2 18341 JAL(dvmCheckBefore) 18342 jr rBIX 18343 18344 /* ------------------------------ */ 18345 .balign 128 18346 .L_ALT_OP_IPUT_QUICK: /* 0xf5 */ 18347 /* File: mips/alt_stub.S */ 18348 /* 18349 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18350 * any interesting requests and then jump to the real instruction 18351 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18352 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18353 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18354 * bail to the real handler if breakFlags==0. 18355 */ 18356 lbu a3, offThread_breakFlags(rSELF) 18357 la rBIX, dvmAsmInstructionStart + (245 * 128) 18358 lw rIBASE, offThread_curHandlerTable(rSELF) 18359 bnez a3, 1f 18360 jr rBIX # nothing to do - jump to real handler 18361 1: 18362 EXPORT_PC() 18363 move a0, rPC # arg0 18364 move a1, rFP # arg1 18365 move a2, rSELF # arg2 18366 JAL(dvmCheckBefore) 18367 jr rBIX 18368 18369 /* ------------------------------ */ 18370 .balign 128 18371 .L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 18372 /* File: mips/alt_stub.S */ 18373 /* 18374 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18375 * any interesting requests and then jump to the real instruction 18376 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18377 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18378 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18379 * bail to the real handler if breakFlags==0. 18380 */ 18381 lbu a3, offThread_breakFlags(rSELF) 18382 la rBIX, dvmAsmInstructionStart + (246 * 128) 18383 lw rIBASE, offThread_curHandlerTable(rSELF) 18384 bnez a3, 1f 18385 jr rBIX # nothing to do - jump to real handler 18386 1: 18387 EXPORT_PC() 18388 move a0, rPC # arg0 18389 move a1, rFP # arg1 18390 move a2, rSELF # arg2 18391 JAL(dvmCheckBefore) 18392 jr rBIX 18393 18394 /* ------------------------------ */ 18395 .balign 128 18396 .L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 18397 /* File: mips/alt_stub.S */ 18398 /* 18399 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18400 * any interesting requests and then jump to the real instruction 18401 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18402 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18403 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18404 * bail to the real handler if breakFlags==0. 18405 */ 18406 lbu a3, offThread_breakFlags(rSELF) 18407 la rBIX, dvmAsmInstructionStart + (247 * 128) 18408 lw rIBASE, offThread_curHandlerTable(rSELF) 18409 bnez a3, 1f 18410 jr rBIX # nothing to do - jump to real handler 18411 1: 18412 EXPORT_PC() 18413 move a0, rPC # arg0 18414 move a1, rFP # arg1 18415 move a2, rSELF # arg2 18416 JAL(dvmCheckBefore) 18417 jr rBIX 18418 18419 /* ------------------------------ */ 18420 .balign 128 18421 .L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 18422 /* File: mips/alt_stub.S */ 18423 /* 18424 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18425 * any interesting requests and then jump to the real instruction 18426 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18427 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18428 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18429 * bail to the real handler if breakFlags==0. 18430 */ 18431 lbu a3, offThread_breakFlags(rSELF) 18432 la rBIX, dvmAsmInstructionStart + (248 * 128) 18433 lw rIBASE, offThread_curHandlerTable(rSELF) 18434 bnez a3, 1f 18435 jr rBIX # nothing to do - jump to real handler 18436 1: 18437 EXPORT_PC() 18438 move a0, rPC # arg0 18439 move a1, rFP # arg1 18440 move a2, rSELF # arg2 18441 JAL(dvmCheckBefore) 18442 jr rBIX 18443 18444 /* ------------------------------ */ 18445 .balign 128 18446 .L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 18447 /* File: mips/alt_stub.S */ 18448 /* 18449 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18450 * any interesting requests and then jump to the real instruction 18451 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18452 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18453 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18454 * bail to the real handler if breakFlags==0. 18455 */ 18456 lbu a3, offThread_breakFlags(rSELF) 18457 la rBIX, dvmAsmInstructionStart + (249 * 128) 18458 lw rIBASE, offThread_curHandlerTable(rSELF) 18459 bnez a3, 1f 18460 jr rBIX # nothing to do - jump to real handler 18461 1: 18462 EXPORT_PC() 18463 move a0, rPC # arg0 18464 move a1, rFP # arg1 18465 move a2, rSELF # arg2 18466 JAL(dvmCheckBefore) 18467 jr rBIX 18468 18469 /* ------------------------------ */ 18470 .balign 128 18471 .L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 18472 /* File: mips/alt_stub.S */ 18473 /* 18474 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18475 * any interesting requests and then jump to the real instruction 18476 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18477 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18478 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18479 * bail to the real handler if breakFlags==0. 18480 */ 18481 lbu a3, offThread_breakFlags(rSELF) 18482 la rBIX, dvmAsmInstructionStart + (250 * 128) 18483 lw rIBASE, offThread_curHandlerTable(rSELF) 18484 bnez a3, 1f 18485 jr rBIX # nothing to do - jump to real handler 18486 1: 18487 EXPORT_PC() 18488 move a0, rPC # arg0 18489 move a1, rFP # arg1 18490 move a2, rSELF # arg2 18491 JAL(dvmCheckBefore) 18492 jr rBIX 18493 18494 /* ------------------------------ */ 18495 .balign 128 18496 .L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 18497 /* File: mips/alt_stub.S */ 18498 /* 18499 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18500 * any interesting requests and then jump to the real instruction 18501 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18502 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18503 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18504 * bail to the real handler if breakFlags==0. 18505 */ 18506 lbu a3, offThread_breakFlags(rSELF) 18507 la rBIX, dvmAsmInstructionStart + (251 * 128) 18508 lw rIBASE, offThread_curHandlerTable(rSELF) 18509 bnez a3, 1f 18510 jr rBIX # nothing to do - jump to real handler 18511 1: 18512 EXPORT_PC() 18513 move a0, rPC # arg0 18514 move a1, rFP # arg1 18515 move a2, rSELF # arg2 18516 JAL(dvmCheckBefore) 18517 jr rBIX 18518 18519 /* ------------------------------ */ 18520 .balign 128 18521 .L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 18522 /* File: mips/alt_stub.S */ 18523 /* 18524 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18525 * any interesting requests and then jump to the real instruction 18526 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18527 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18528 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18529 * bail to the real handler if breakFlags==0. 18530 */ 18531 lbu a3, offThread_breakFlags(rSELF) 18532 la rBIX, dvmAsmInstructionStart + (252 * 128) 18533 lw rIBASE, offThread_curHandlerTable(rSELF) 18534 bnez a3, 1f 18535 jr rBIX # nothing to do - jump to real handler 18536 1: 18537 EXPORT_PC() 18538 move a0, rPC # arg0 18539 move a1, rFP # arg1 18540 move a2, rSELF # arg2 18541 JAL(dvmCheckBefore) 18542 jr rBIX 18543 18544 /* ------------------------------ */ 18545 .balign 128 18546 .L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 18547 /* File: mips/alt_stub.S */ 18548 /* 18549 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18550 * any interesting requests and then jump to the real instruction 18551 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18552 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18553 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18554 * bail to the real handler if breakFlags==0. 18555 */ 18556 lbu a3, offThread_breakFlags(rSELF) 18557 la rBIX, dvmAsmInstructionStart + (253 * 128) 18558 lw rIBASE, offThread_curHandlerTable(rSELF) 18559 bnez a3, 1f 18560 jr rBIX # nothing to do - jump to real handler 18561 1: 18562 EXPORT_PC() 18563 move a0, rPC # arg0 18564 move a1, rFP # arg1 18565 move a2, rSELF # arg2 18566 JAL(dvmCheckBefore) 18567 jr rBIX 18568 18569 /* ------------------------------ */ 18570 .balign 128 18571 .L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 18572 /* File: mips/alt_stub.S */ 18573 /* 18574 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18575 * any interesting requests and then jump to the real instruction 18576 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18577 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18578 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18579 * bail to the real handler if breakFlags==0. 18580 */ 18581 lbu a3, offThread_breakFlags(rSELF) 18582 la rBIX, dvmAsmInstructionStart + (254 * 128) 18583 lw rIBASE, offThread_curHandlerTable(rSELF) 18584 bnez a3, 1f 18585 jr rBIX # nothing to do - jump to real handler 18586 1: 18587 EXPORT_PC() 18588 move a0, rPC # arg0 18589 move a1, rFP # arg1 18590 move a2, rSELF # arg2 18591 JAL(dvmCheckBefore) 18592 jr rBIX 18593 18594 /* ------------------------------ */ 18595 .balign 128 18596 .L_ALT_OP_UNUSED_FF: /* 0xff */ 18597 /* File: mips/alt_stub.S */ 18598 /* 18599 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18600 * any interesting requests and then jump to the real instruction 18601 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18602 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18603 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18604 * bail to the real handler if breakFlags==0. 18605 */ 18606 lbu a3, offThread_breakFlags(rSELF) 18607 la rBIX, dvmAsmInstructionStart + (255 * 128) 18608 lw rIBASE, offThread_curHandlerTable(rSELF) 18609 bnez a3, 1f 18610 jr rBIX # nothing to do - jump to real handler 18611 1: 18612 EXPORT_PC() 18613 move a0, rPC # arg0 18614 move a1, rFP # arg1 18615 move a2, rSELF # arg2 18616 JAL(dvmCheckBefore) 18617 jr rBIX 18618 18619 .balign 128 18620 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart 18621 .global dvmAsmAltInstructionEnd 18622 dvmAsmAltInstructionEnd: 18623