1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __ASM_MSR_INDEX_H 20 #define __ASM_MSR_INDEX_H 21 #define MSR_EFER 0xc0000080 22 #define MSR_STAR 0xc0000081 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define MSR_LSTAR 0xc0000082 25 #define MSR_CSTAR 0xc0000083 26 #define MSR_SYSCALL_MASK 0xc0000084 27 #define MSR_FS_BASE 0xc0000100 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define MSR_GS_BASE 0xc0000101 30 #define MSR_KERNEL_GS_BASE 0xc0000102 31 #define _EFER_SCE 0 32 #define _EFER_LME 8 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define _EFER_LMA 10 35 #define _EFER_NX 11 36 #define EFER_SCE (1<<_EFER_SCE) 37 #define EFER_LME (1<<_EFER_LME) 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define EFER_LMA (1<<_EFER_LMA) 40 #define EFER_NX (1<<_EFER_NX) 41 #define MSR_IA32_PERFCTR0 0x000000c1 42 #define MSR_IA32_PERFCTR1 0x000000c2 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define MSR_FSB_FREQ 0x000000cd 45 #define MSR_MTRRcap 0x000000fe 46 #define MSR_IA32_BBL_CR_CTL 0x00000119 47 #define MSR_IA32_SYSENTER_CS 0x00000174 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define MSR_IA32_SYSENTER_ESP 0x00000175 50 #define MSR_IA32_SYSENTER_EIP 0x00000176 51 #define MSR_IA32_MCG_CAP 0x00000179 52 #define MSR_IA32_MCG_STATUS 0x0000017a 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define MSR_IA32_MCG_CTL 0x0000017b 55 #define MSR_IA32_PEBS_ENABLE 0x000003f1 56 #define MSR_IA32_DS_AREA 0x00000600 57 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define MSR_MTRRfix64K_00000 0x00000250 60 #define MSR_MTRRfix16K_80000 0x00000258 61 #define MSR_MTRRfix16K_A0000 0x00000259 62 #define MSR_MTRRfix4K_C0000 0x00000268 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define MSR_MTRRfix4K_C8000 0x00000269 65 #define MSR_MTRRfix4K_D0000 0x0000026a 66 #define MSR_MTRRfix4K_D8000 0x0000026b 67 #define MSR_MTRRfix4K_E0000 0x0000026c 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define MSR_MTRRfix4K_E8000 0x0000026d 70 #define MSR_MTRRfix4K_F0000 0x0000026e 71 #define MSR_MTRRfix4K_F8000 0x0000026f 72 #define MSR_MTRRdefType 0x000002ff 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 75 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 76 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 77 #define MSR_IA32_LASTINTFROMIP 0x000001dd 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define MSR_IA32_LASTINTTOIP 0x000001de 80 #define MSR_IA32_MC0_CTL 0x00000400 81 #define MSR_IA32_MC0_STATUS 0x00000401 82 #define MSR_IA32_MC0_ADDR 0x00000402 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define MSR_IA32_MC0_MISC 0x00000403 85 #define MSR_P6_PERFCTR0 0x000000c1 86 #define MSR_P6_PERFCTR1 0x000000c2 87 #define MSR_P6_EVNTSEL0 0x00000186 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define MSR_P6_EVNTSEL1 0x00000187 90 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 91 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 92 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define MSR_AMD64_IBSOPCTL 0xc0011033 95 #define MSR_AMD64_IBSOPRIP 0xc0011034 96 #define MSR_AMD64_IBSOPDATA 0xc0011035 97 #define MSR_AMD64_IBSOPDATA2 0xc0011036 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 #define MSR_AMD64_IBSOPDATA3 0xc0011037 100 #define MSR_AMD64_IBSDCLINAD 0xc0011038 101 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 102 #define MSR_AMD64_IBSCTL 0xc001103a 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define MSR_K8_TOP_MEM1 0xc001001a 105 #define MSR_K8_TOP_MEM2 0xc001001d 106 #define MSR_K8_SYSCFG 0xc0010010 107 #define MSR_K8_HWCR 0xc0010015 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 #define MSR_K8_ENABLE_C1E 0xc0010055 110 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 111 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 112 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 #define MSR_K7_EVNTSEL0 0xc0010000 115 #define MSR_K7_PERFCTR0 0xc0010004 116 #define MSR_K7_EVNTSEL1 0xc0010001 117 #define MSR_K7_PERFCTR1 0xc0010005 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define MSR_K7_EVNTSEL2 0xc0010002 120 #define MSR_K7_PERFCTR2 0xc0010006 121 #define MSR_K7_EVNTSEL3 0xc0010003 122 #define MSR_K7_PERFCTR3 0xc0010007 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define MSR_K7_CLK_CTL 0xc001001b 125 #define MSR_K7_HWCR 0xc0010015 126 #define MSR_K7_FID_VID_CTL 0xc0010041 127 #define MSR_K7_FID_VID_STATUS 0xc0010042 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define MSR_K6_EFER 0xc0000080 130 #define MSR_K6_STAR 0xc0000081 131 #define MSR_K6_WHCR 0xc0000082 132 #define MSR_K6_UWCCR 0xc0000085 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define MSR_K6_EPMR 0xc0000086 135 #define MSR_K6_PSOR 0xc0000087 136 #define MSR_K6_PFIR 0xc0000088 137 #define MSR_IDT_FCR1 0x00000107 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 #define MSR_IDT_FCR2 0x00000108 140 #define MSR_IDT_FCR3 0x00000109 141 #define MSR_IDT_FCR4 0x0000010a 142 #define MSR_IDT_MCR0 0x00000110 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 #define MSR_IDT_MCR1 0x00000111 145 #define MSR_IDT_MCR2 0x00000112 146 #define MSR_IDT_MCR3 0x00000113 147 #define MSR_IDT_MCR4 0x00000114 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 #define MSR_IDT_MCR5 0x00000115 150 #define MSR_IDT_MCR6 0x00000116 151 #define MSR_IDT_MCR7 0x00000117 152 #define MSR_IDT_MCR_CTRL 0x00000120 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define MSR_VIA_FCR 0x00001107 155 #define MSR_VIA_LONGHAUL 0x0000110a 156 #define MSR_VIA_RNG 0x0000110b 157 #define MSR_VIA_BCR2 0x00001147 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 160 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 161 #define MSR_TMTA_LRTI_READOUT 0x80868018 162 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 #define MSR_IA32_P5_MC_ADDR 0x00000000 165 #define MSR_IA32_P5_MC_TYPE 0x00000001 166 #define MSR_IA32_TSC 0x00000010 167 #define MSR_IA32_PLATFORM_ID 0x00000017 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 170 #define MSR_IA32_APICBASE 0x0000001b 171 #define MSR_IA32_APICBASE_BSP (1<<8) 172 #define MSR_IA32_APICBASE_ENABLE (1<<11) 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 175 #define MSR_IA32_UCODE_WRITE 0x00000079 176 #define MSR_IA32_UCODE_REV 0x0000008b 177 #define MSR_IA32_PERF_STATUS 0x00000198 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 #define MSR_IA32_PERF_CTL 0x00000199 180 #define MSR_IA32_MPERF 0x000000e7 181 #define MSR_IA32_APERF 0x000000e8 182 #define MSR_IA32_THERM_CONTROL 0x0000019a 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 185 #define MSR_IA32_THERM_STATUS 0x0000019c 186 #define MSR_IA32_MISC_ENABLE 0x000001a0 187 #define MSR_P6_EVNTSEL0 0x00000186 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 #define MSR_P6_EVNTSEL1 0x00000187 190 #define MSR_IA32_MCG_EAX 0x00000180 191 #define MSR_IA32_MCG_EBX 0x00000181 192 #define MSR_IA32_MCG_ECX 0x00000182 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 #define MSR_IA32_MCG_EDX 0x00000183 195 #define MSR_IA32_MCG_ESI 0x00000184 196 #define MSR_IA32_MCG_EDI 0x00000185 197 #define MSR_IA32_MCG_EBP 0x00000186 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 #define MSR_IA32_MCG_ESP 0x00000187 200 #define MSR_IA32_MCG_EFLAGS 0x00000188 201 #define MSR_IA32_MCG_EIP 0x00000189 202 #define MSR_IA32_MCG_RESERVED 0x0000018a 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 #define MSR_P4_BPU_PERFCTR0 0x00000300 205 #define MSR_P4_BPU_PERFCTR1 0x00000301 206 #define MSR_P4_BPU_PERFCTR2 0x00000302 207 #define MSR_P4_BPU_PERFCTR3 0x00000303 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 #define MSR_P4_MS_PERFCTR0 0x00000304 210 #define MSR_P4_MS_PERFCTR1 0x00000305 211 #define MSR_P4_MS_PERFCTR2 0x00000306 212 #define MSR_P4_MS_PERFCTR3 0x00000307 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 #define MSR_P4_FLAME_PERFCTR0 0x00000308 215 #define MSR_P4_FLAME_PERFCTR1 0x00000309 216 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 217 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 #define MSR_P4_IQ_PERFCTR0 0x0000030c 220 #define MSR_P4_IQ_PERFCTR1 0x0000030d 221 #define MSR_P4_IQ_PERFCTR2 0x0000030e 222 #define MSR_P4_IQ_PERFCTR3 0x0000030f 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define MSR_P4_IQ_PERFCTR4 0x00000310 225 #define MSR_P4_IQ_PERFCTR5 0x00000311 226 #define MSR_P4_BPU_CCCR0 0x00000360 227 #define MSR_P4_BPU_CCCR1 0x00000361 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define MSR_P4_BPU_CCCR2 0x00000362 230 #define MSR_P4_BPU_CCCR3 0x00000363 231 #define MSR_P4_MS_CCCR0 0x00000364 232 #define MSR_P4_MS_CCCR1 0x00000365 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define MSR_P4_MS_CCCR2 0x00000366 235 #define MSR_P4_MS_CCCR3 0x00000367 236 #define MSR_P4_FLAME_CCCR0 0x00000368 237 #define MSR_P4_FLAME_CCCR1 0x00000369 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 #define MSR_P4_FLAME_CCCR2 0x0000036a 240 #define MSR_P4_FLAME_CCCR3 0x0000036b 241 #define MSR_P4_IQ_CCCR0 0x0000036c 242 #define MSR_P4_IQ_CCCR1 0x0000036d 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 #define MSR_P4_IQ_CCCR2 0x0000036e 245 #define MSR_P4_IQ_CCCR3 0x0000036f 246 #define MSR_P4_IQ_CCCR4 0x00000370 247 #define MSR_P4_IQ_CCCR5 0x00000371 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 #define MSR_P4_ALF_ESCR0 0x000003ca 250 #define MSR_P4_ALF_ESCR1 0x000003cb 251 #define MSR_P4_BPU_ESCR0 0x000003b2 252 #define MSR_P4_BPU_ESCR1 0x000003b3 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 #define MSR_P4_BSU_ESCR0 0x000003a0 255 #define MSR_P4_BSU_ESCR1 0x000003a1 256 #define MSR_P4_CRU_ESCR0 0x000003b8 257 #define MSR_P4_CRU_ESCR1 0x000003b9 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 #define MSR_P4_CRU_ESCR2 0x000003cc 260 #define MSR_P4_CRU_ESCR3 0x000003cd 261 #define MSR_P4_CRU_ESCR4 0x000003e0 262 #define MSR_P4_CRU_ESCR5 0x000003e1 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 #define MSR_P4_DAC_ESCR0 0x000003a8 265 #define MSR_P4_DAC_ESCR1 0x000003a9 266 #define MSR_P4_FIRM_ESCR0 0x000003a4 267 #define MSR_P4_FIRM_ESCR1 0x000003a5 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 #define MSR_P4_FLAME_ESCR0 0x000003a6 270 #define MSR_P4_FLAME_ESCR1 0x000003a7 271 #define MSR_P4_FSB_ESCR0 0x000003a2 272 #define MSR_P4_FSB_ESCR1 0x000003a3 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 #define MSR_P4_IQ_ESCR0 0x000003ba 275 #define MSR_P4_IQ_ESCR1 0x000003bb 276 #define MSR_P4_IS_ESCR0 0x000003b4 277 #define MSR_P4_IS_ESCR1 0x000003b5 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 #define MSR_P4_ITLB_ESCR0 0x000003b6 280 #define MSR_P4_ITLB_ESCR1 0x000003b7 281 #define MSR_P4_IX_ESCR0 0x000003c8 282 #define MSR_P4_IX_ESCR1 0x000003c9 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 #define MSR_P4_MOB_ESCR0 0x000003aa 285 #define MSR_P4_MOB_ESCR1 0x000003ab 286 #define MSR_P4_MS_ESCR0 0x000003c0 287 #define MSR_P4_MS_ESCR1 0x000003c1 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define MSR_P4_PMH_ESCR0 0x000003ac 290 #define MSR_P4_PMH_ESCR1 0x000003ad 291 #define MSR_P4_RAT_ESCR0 0x000003bc 292 #define MSR_P4_RAT_ESCR1 0x000003bd 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 #define MSR_P4_SAAT_ESCR0 0x000003ae 295 #define MSR_P4_SAAT_ESCR1 0x000003af 296 #define MSR_P4_SSU_ESCR0 0x000003be 297 #define MSR_P4_SSU_ESCR1 0x000003bf 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 #define MSR_P4_TBPU_ESCR0 0x000003c2 300 #define MSR_P4_TBPU_ESCR1 0x000003c3 301 #define MSR_P4_TC_ESCR0 0x000003c4 302 #define MSR_P4_TC_ESCR1 0x000003c5 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 #define MSR_P4_U2L_ESCR0 0x000003b0 305 #define MSR_P4_U2L_ESCR1 0x000003b1 306 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 307 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 310 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 311 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 312 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 315 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 316 #endif 317
