1 // RUN: %clang -target mipsel-unknown-linux -ccc-clang-archs mipsel -S -o - -emit-llvm %s \ 2 // RUN: | FileCheck %s 3 4 // This checks that the frontend will accept inline asm constraints 5 // c', 'l' and 'x'. Semantic checking will happen in the 6 // llvm backend. Any bad constraint letters will cause the frontend to 7 // error out. 8 9 int main() 10 { 11 // 'c': 16 bit address register for Mips16, GPR for all others 12 // I am using 'c' to constrain both the target and one of the source 13 // registers. We are looking for syntactical correctness. 14 // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "addi $0,$1,$2 \0A\09\09", "=c,c,I"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) nounwind, !srcloc !{{[0-9]+}} 15 int __s, __v = 17; 16 int __t; 17 __asm__ __volatile__( 18 "addi %0,%1,%2 \n\t\t" 19 : "=c" (__t) 20 : "c" (__s), "I" (__v)); 21 22 // 'l': lo register 23 // We are making it clear that destination register is lo with the 24 // use of the 'l' constraint ("=l"). 25 // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "mtlo $1 \0A\09\09", "=l,r,~{lo}"(i32 %{{[0-9]+}}) nounwind, !srcloc !{{[0-9]+}} 26 int i_temp = 44; 27 int i_result; 28 __asm__ __volatile__( 29 "mtlo %1 \n\t\t" 30 : "=l" (i_result) 31 : "r" (i_temp) 32 : "lo"); 33 34 // 'x': Combined lo/hi registers 35 // We are specifying that destination registers are the hi/lo pair with the 36 // use of the 'x' constraint ("=x"). 37 // CHECK: %{{[0-9]+}} = call i64 asm sideeffect "mthi $1 \0A\09\09mtlo $2 \0A\09\09", "=x,r,r"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) nounwind, !srcloc !{{[0-9]+}} 38 int i_hi = 3; 39 int i_lo = 2; 40 long long ll_result = 0; 41 __asm__ __volatile__( 42 "mthi %1 \n\t\t" 43 "mtlo %2 \n\t\t" 44 : "=x" (ll_result) 45 : "r" (i_hi), "r" (i_lo) 46 : ); 47 48 return 0; 49 } 50
