1 %mask {s} 1 2 %mask {w} 1 3 %mask {w1} 1 4 %mask {W1} 1 5 %mask {W2} 1 6 dnl floating point reg suffix 7 %mask {D} 1 8 %mask {imm8} 8 9 %mask {imms8} 8 10 %mask {imm16} 16 11 %mask {reg} 3 12 %mask {oreg} 3 13 %mask {reg16} 3 14 %mask {reg64} 3 15 %mask {tttn} 4 16 %mask {mod} 2 17 %mask {moda} 2 18 %mask {MOD} 2 19 %mask {r_m} 3 20 dnl like {r_m} but referencing byte register 21 %mask {8r_m} 3 22 dnl like {r_m} but referencing 16-bit register 23 %mask {16r_m} 3 24 dnl like {r_m} but referencing 32- or 64-bit register 25 %mask {64r_m} 3 26 %mask {disp8} 8 27 dnl imm really is 8/16/32 bit depending on the situation. 28 %mask {imm} 8 29 %mask {imm64} 8 30 %mask {imms} 8 31 %mask {rel} 32 32 %mask {abs} 32 33 %mask {absval} 32 34 %mask {sel} 16 35 %mask {imm32} 32 36 %mask {ccc} 3 37 %mask {ddd} 3 38 %mask {sreg3} 3 39 %mask {sreg2} 2 40 %mask {mmxreg} 3 41 %mask {R_M} 3 42 %mask {Mod} 2 43 %mask {xmmreg} 3 44 %mask {R_m} 3 45 %mask {xmmreg1} 3 46 %mask {xmmreg2} 3 47 %mask {mmxreg1} 3 48 %mask {mmxreg2} 3 49 %mask {predps} 8 50 %mask {freg} 3 51 %mask {fmod} 2 52 %mask {fr_m} 3 53 %prefix {R} 54 %prefix {RE} 55 %suffix {W} 56 %suffix {w0} 57 %synonym {xmmreg1} {xmmreg} 58 %synonym {xmmreg2} {xmmreg} 59 %synonym {mmxreg1} {mmxreg} 60 %synonym {mmxreg2} {mmxreg} 61 ifdef(`i386', 62 `%synonym {oreg} {reg} 63 %synonym {imm64} {imm} 64 ')dnl 65 66 %% 67 ifdef(`i386', 68 `00110111:aaa 69 11010101,00001010:aad 70 11010100,00001010:aam 71 00111111:aas 72 ')dnl 73 0001010{w},{imm}:adc {imm}{w},{ax}{w} 74 1000000{w},{mod}010{r_m},{imm}:adc{w} {imm}{w},{mod}{r_m}{w} 75 1000001{w},{mod}010{r_m},{imms8}:adc{w} {imms8},{mod}{r_m} 76 0001000{w},{mod}{reg}{r_m}:adc {reg}{w},{mod}{r_m}{w} 77 0001001{w},{mod}{reg}{r_m}:adc {mod}{r_m}{w},{reg}{w} 78 0000010{w},{imm}:add {imm}{w},{ax}{w} 79 1000000{w},{mod}000{r_m},{imm}:add{w} {imm}{w},{mod}{r_m}{w} 80 10000011,{mod}000{r_m},{imms8}:add{w} {imms8},{mod}{r_m} 81 0000000{w},{mod}{reg}{r_m}:add {reg}{w},{mod}{r_m}{w} 82 0000001{w},{mod}{reg}{r_m}:add {mod}{r_m}{w},{reg}{w} 83 01100110,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubpd {Mod}{R_m},{xmmreg} 84 11110010,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubps {Mod}{R_m},{xmmreg} 85 0010010{w},{imm}:and {imm}{w},{ax}{w} 86 1000000{w},{mod}100{r_m},{imm}:and{w} {imm}{w},{mod}{r_m}{w} 87 1000001{w},{mod}100{r_m},{imms8}:and{w} {imms8},{mod}{r_m} 88 0010000{w},{mod}{reg}{r_m}:and {reg}{w},{mod}{r_m}{w} 89 0010001{w},{mod}{reg}{r_m}:and {mod}{r_m}{w},{reg}{w} 90 01100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg} 91 00001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg} 92 01100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg} 93 00001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg} 94 ifdef(`i386', 95 `01100011,{mod}{reg16}{r_m}:arpl {reg16},{mod}{r_m} 96 01100010,{moda}{reg}{r_m}:bound {reg},{moda}{r_m} 97 ', 98 `01100011,{mod}{reg64}{r_m}:movslq {mod}{r_m},{reg64} 99 ')dnl 100 00001111,10111100,{mod}{reg}{r_m}:bsf {mod}{r_m},{reg} 101 00001111,10111101,{mod}{reg}{r_m}:bsr {mod}{r_m},{reg} 102 00001111,11001{reg}:bswap {reg} 103 00001111,10100011,{mod}{reg}{r_m}:bt {reg},{mod}{r_m} 104 00001111,10111010,{mod}100{r_m},{imm8}:bt{w} {imm8},{mod}{r_m} 105 00001111,10111011,{mod}{reg}{r_m}:btc {reg},{mod}{r_m} 106 00001111,10111010,{mod}111{r_m},{imm8}:btc{w} {imm8},{mod}{r_m} 107 00001111,10110011,{mod}{reg}{r_m}:btr {reg},{mod}{r_m} 108 00001111,10111010,{mod}110{r_m},{imm8}:btr{w} {imm8},{mod}{r_m} 109 00001111,10101011,{mod}{reg}{r_m}:bts {reg},{mod}{r_m} 110 00001111,10111010,{mod}101{r_m},{imm8}:bts{w} {imm8},{mod}{r_m} 111 11101000,{rel}:call{W} {rel} 112 11111111,{mod}010{64r_m}:call{W} *{mod}{64r_m} 113 ifdef(`i386', 114 `10011010,{absval},{sel}:lcall {sel},{absval} 115 ')dnl 116 11111111,{mod}011{64r_m}:lcall{W} *{mod}{64r_m} 117 # SPECIAL 10011000:[{rex.w}?cltq:{dpfx}?cbtw:cwtl] 118 10011000:INVALID 119 # SPECIAL 10011001:[{rex.w}?cqto:{dpfx}?cltd:cwtd] 120 10011001:INVALID 121 11111000:clc 122 11111100:cld 123 11111010:cli 124 00001111,00000101:syscall 125 00001111,00000110:clts 126 00001111,00000111:sysret 127 00001111,00110100:sysenter 128 00001111,00110101:sysexit 129 11110101:cmc 130 00001111,0100{tttn},{mod}{reg}{r_m}:cmov{tttn} {mod}{r_m},{reg} 131 0011110{w},{imm}:cmp {imm}{w},{ax}{w} 132 1000000{w},{mod}111{r_m},{imm}:cmp{w} {imm}{w},{mod}{r_m}{w} 133 10000011,{mod}111{r_m},{imms8}:cmp{w} {imms8},{mod}{r_m} 134 0011100{w},{mod}{reg}{r_m}:cmp {reg}{w},{mod}{r_m}{w} 135 0011101{w},{mod}{reg}{r_m}:cmp {mod}{r_m}{w},{reg}{w} 136 ifdef(`ASSEMBLER', 137 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg} 138 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg} 139 01100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg} 140 00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg} 141 ', 142 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg} 143 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg} 144 01100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg} 145 00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg} 146 ')dnl 147 1010011{w}:{RE}cmps{w} {es_di},{ds_si} 148 00001111,1011000{w},{mod}{reg}{r_m}:cmpxchg {reg}{w},{mod}{r_m}{w} 149 ifdef(`i386', 150 `00001111,11000111,{mod}001{r_m}:cmpxchg8b {mod}{r_m} 151 ', 152 `# SPECIAL 00001111,11000111,{mod}001{r_m}:[{rex.w}?cmpxchg16b:cmpxchg8b] {reg},{mod}{r_m} 153 00001111,11000111,{mod}001{r_m}:INVALID {mod}{r_m} 154 ')dnl 155 00001111,10100010:cpuid 156 11110011,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtdq2pd {Mod}{R_m},{xmmreg} 157 11110010,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtpd2dq {Mod}{R_m},{xmmreg} 158 01100110,00001111,11100110,{Mod}{xmmreg}{R_m}:cvttpd2dq {Mod}{R_m},{xmmreg} 159 ifdef(`i386', 160 `00100111:daa 161 00101111:das 162 ')dnl 163 1111111{w},{mod}001{r_m}:dec{w} {mod}{r_m}{w} 164 ifdef(`i386', 165 `01001{reg}:dec {reg} 166 ')dnl 167 1111011{w},{mod}110{r_m}:div{w} {mod}{r_m}{w} 168 00001111,01110111:emms 169 11001000,{imm16},{imm8}:enter{W} {imm16},{imm8} 170 11011001,11010000:fnop 171 11011001,11100000:fchs 172 11011001,11100001:fabs 173 11011001,11100100:ftst 174 11011001,11100101:fxam 175 11011001,11101000:fld1 176 11011001,11101001:fldl2t 177 11011001,11101010:fldl2e 178 11011001,11101011:fldpi 179 11011001,11101100:fldlg2 180 11011001,11101101:fldln2 181 11011001,11101110:fldz 182 11011001,11110000:f2xm1 183 11011001,11110001:fyl2x 184 11011001,11110010:fptan 185 11011001,11110011:fpatan 186 11011001,11110100:fxtract 187 11011001,11110101:fprem1 188 11011001,11110110:fdecstp 189 11011001,11110111:fincstp 190 11011001,11111000:fprem 191 11011001,11111001:fyl2xp1 192 11011001,11111010:fsqrt 193 11011001,11111011:fsincos 194 11011001,11111100:frndint 195 11011001,11111101:fscale 196 11011001,11111110:fsin 197 11011001,11111111:fcos 198 # ORDER 199 11011000,11000{freg}:fadd {freg},%st 200 11011100,11000{freg}:fadd %st,{freg} 201 11011{D}00,{mod}000{r_m}:fadd{D} {mod}{r_m} 202 # ORDER END 203 # ORDER 204 11011000,11001{freg}:fmul {freg},%st 205 11011100,11001{freg}:fmul %st,{freg} 206 11011{D}00,{mod}001{r_m}:fmul{D} {mod}{r_m} 207 # ORDER END 208 # ORDER 209 11011000,11100{freg}:fsub {freg},%st 210 11011100,11100{freg}:fsub %st,{freg} 211 11011{D}00,{mod}100{r_m}:fsub{D} {mod}{r_m} 212 # ORDER END 213 # ORDER 214 11011000,11101{freg}:fsubr {freg},%st 215 11011100,11101{freg}:fsubr %st,{freg} 216 11011{D}00,{mod}101{r_m}:fsubr{D} {mod}{r_m} 217 # ORDER END 218 # ORDER 219 11011101,11010{freg}:fst {freg} 220 11011{D}01,{mod}010{r_m}:fst{D} {mod}{r_m} 221 # ORDER END 222 # ORDER 223 11011101,11011{freg}:fstp {freg} 224 11011{D}01,{mod}011{r_m}:fstp{D} {mod}{r_m} 225 # ORDER END 226 11011001,{mod}100{r_m}:fldenv {mod}{r_m} 227 11011001,{mod}101{r_m}:fldcw {mod}{r_m} 228 11011001,{mod}110{r_m}:fnstenv {mod}{r_m} 229 11011001,{mod}111{r_m}:fnstcw {mod}{r_m} 230 11011001,11001{freg}:fxch {freg} 231 # ORDER 232 11011110,11000{freg}:faddp %st,{freg} 233 ifdef(`ASSEMBLER', 234 `11011110,11000001:faddp 235 ')dnl 236 # ORDER 237 11011010,11000{freg}:fcmovb {freg},%st 238 11011{w1}10,{mod}000{r_m}:fiadd{w1} {mod}{r_m} 239 # ORDER END 240 # ORDER 241 11011010,11001{freg}:fcmove {freg},%st 242 11011110,11001{freg}:fmulp %st,{freg} 243 11011{w1}10,{mod}001{r_m}:fimul{w1} {mod}{r_m} 244 # ORDER END 245 # ORDER 246 11011110,11100{freg}:fsubp %st,{freg} 247 11011{w1}10,{mod}100{r_m}:fisub{w1} {mod}{r_m} 248 # ORDER END 249 # ORDER 250 11011110,11101{freg}:fsubrp %st,{freg} 251 11011{w1}10,{mod}101{r_m}:fisubr{w1} {mod}{r_m} 252 # ORDER END 253 # ORDER 254 11011111,11100000:fnstsw %ax 255 11011111,{mod}100{r_m}:fbld {mod}{r_m} 256 # ORDER END 257 # ORDER 258 11011111,11110{freg}:fcomip {freg},%st 259 11011111,{mod}110{r_m}:fbstp {mod}{r_m} 260 # ORDER END 261 11011001,11100000:fchs 262 # ORDER 263 10011011,11011011,11100010:fclex 264 10011011,11011011,11100011:finit 265 10011011:fwait 266 # END ORDER 267 11011011,11100010:fnclex 268 11011010,11000{freg}:fcmovb {freg},%st 269 11011010,11001{freg}:fcmove {freg},%st 270 11011010,11010{freg}:fcmovbe {freg},%st 271 11011010,11011{freg}:fcmovu {freg},%st 272 11011011,11000{freg}:fcmovnb {freg},%st 273 11011011,11001{freg}:fcmovne {freg},%st 274 11011011,11010{freg}:fcmovnbe {freg},%st 275 11011011,11011{freg}:fcmovnu {freg},%st 276 # ORDER 277 11011000,11010{freg}:fcom {freg} 278 ifdef(`ASSEMBLER', 279 `11011000,11010001:fcom 280 ')dnl 281 11011{D}00,{mod}010{r_m}:fcom{D} {mod}{r_m} 282 # END ORDER 283 # ORDER 284 11011000,11011{freg}:fcomp {freg} 285 ifdef(`ASSEMBLER', 286 `11011000,11011001:fcomp 287 ')dnl 288 11011{D}00,{mod}011{r_m}:fcomp{D} {mod}{r_m} 289 # END ORDER 290 11011110,11011001:fcompp 291 11011011,11110{freg}:fcomi {freg},%st 292 11011111,11110{freg}:fcomip {freg},%st 293 11011011,11101{freg}:fucomi {freg},%st 294 11011111,11101{freg}:fucomip {freg},%st 295 11011001,11111111:fcos 296 11011001,11110110:fdecstp 297 # ORDER 298 11011000,11110{freg}:fdiv {freg},%st 299 11011100,11110{freg}:fdiv %st,{freg} 300 11011{D}00,{mod}110{r_m}:fdiv{D} {mod}{r_m} 301 # END ORDER 302 11011010,{mod}110{r_m}:fidivl {mod}{r_m} 303 # ORDER 304 11011110,11110{freg}:fdivp %st,{freg} 305 11011110,{mod}110{r_m}:fidiv {mod}{r_m} 306 # END ORDER 307 11011110,11111{freg}:fdivrp %st,{freg} 308 ifdef(`ASSEMBLER', 309 `11011110,11111001:fdivp 310 ')dnl 311 # ORDER 312 11011000,11111{freg}:fdivr {freg},%st 313 11011100,11111{freg}:fdivr %st,{freg} 314 11011{D}00,{mod}111{r_m}:fdivr{D} {mod}{r_m} 315 # END ORDER 316 11011010,{mod}111{r_m}:fidivrl {mod}{r_m} 317 11011110,{mod}111{r_m}:fidivr {mod}{r_m} 318 11011110,11110{freg}:fdivrp %st,{freg} 319 ifdef(`ASSEMBLER', 320 `11011110,11110001:fdivrp 321 ')dnl 322 11011101,11000{freg}:ffree {freg} 323 11011010,11010{freg}:fcmovbe {freg} 324 11011{w1}10,{mod}010{r_m}:ficom{w1} {mod}{r_m} 325 11011010,11011{freg}:fcmovu {freg} 326 11011{w1}10,{mod}011{r_m}:ficomp{w1} {mod}{r_m} 327 11011111,{mod}000{r_m}:fild {mod}{r_m} 328 11011011,{mod}000{r_m}:fildl {mod}{r_m} 329 11011111,{mod}101{r_m}:fildll {mod}{r_m} 330 11011001,11110111:fincstp 331 11011011,11100011:fninit 332 11011{w1}11,{mod}010{r_m}:fist{w1} {mod}{r_m} 333 11011{w1}11,{mod}011{r_m}:fistp{w1} {mod}{r_m} 334 11011111,{mod}111{r_m}:fistpll {mod}{r_m} 335 11011{w1}11,{mod}001{r_m}:fisttp{w1} {mod}{r_m} 336 11011101,{mod}001{r_m}:fisttpll {mod}{r_m} 337 11011011,{mod}101{r_m}:fldt {mod}{r_m} 338 11011011,{mod}111{r_m}:fstpt {mod}{r_m} 339 # ORDER 340 11011001,11000{freg}:fld {freg} 341 11011{D}01,{mod}000{r_m}:fld{D} {mod}{r_m} 342 # ORDER END 343 # ORDER 344 11011101,11100{freg}:fucom {freg} 345 11011101,{mod}100{r_m}:frstor {mod}{r_m} 346 # ORDER END 347 11011101,11101{freg}:fucomp {freg} 348 11011101,{mod}110{r_m}:fnsave {mod}{r_m} 349 11011101,{mod}111{r_m}:fnstsw {mod}{r_m} 350 # 351 # 352 # 353 11110100:hlt 354 1111011{w},{mod}111{r_m}:idiv{w} {mod}{r_m}{w} 355 1111011{w},{mod}101{r_m}:imul{w} {mod}{r_m}{w} 356 00001111,10101111,{mod}{reg}{r_m}:imul {mod}{r_m},{reg} 357 011010{s}1,{mod}{reg}{r_m},{imm}:imul {imm}{s},{mod}{r_m},{reg} 358 1110010{w},{imm8}:in {imm8},{ax}{w} 359 1110110{w}:in {dx},{ax}{w} 360 1111111{w},{mod}000{r_m}:inc{w} {mod}{r_m}{w} 361 ifdef(`i386', 362 `01000{reg}:inc {reg} 363 ')dnl 364 0110110{w}:{R}ins{w} {dx},{es_di} 365 11001101,{imm8}:int {imm8} 366 11001100:int3 367 ifdef(`i386', 368 `11001110:into 369 ')dnl 370 00001111,00001000:invd 371 # ORDER 372 00001111,00000001,11111000:swapgs 373 00001111,00000001,{mod}111{r_m}:invlpg {mod}{r_m} 374 # ORDER END 375 11001111:iret{W1} 376 0111{tttn},{disp8}:j{tttn} {disp8} 377 00001111,1000{tttn},{rel}:j{tttn} {rel} 378 00001111,1001{tttn},{mod}000{8r_m}:set{tttn} {mod}{8r_m} 379 # SPECIAL 11100011,{disp8}:[{dpfx}?jcxz:jecxz] {disp8} 380 11100011,{disp8}:INVALID {disp8} 381 11101011,{disp8}:jmp {disp8} 382 11101001,{rel}:jmp{W} {rel} 383 11111111,{mod}100{64r_m}:jmp{W} *{mod}{64r_m} 384 11101010,{absval},{sel}:ljmp {sel},{absval} 385 11111111,{mod}101{64r_m}:ljmp{W} *{mod}{64r_m} 386 10011111:lahf 387 00001111,00000010,{mod}{reg}{16r_m}:lar {mod}{16r_m},{reg} 388 ifdef(`i386', 389 `11000101,{mod}{reg}{r_m}:lds {mod}{r_m},{reg} 390 ')dnl 391 10001101,{mod}{reg}{r_m}:lea {mod}{r_m},{reg} 392 11001001:leave{W} 393 ifdef(`i386', 394 `11000100,{mod}{reg}{r_m}:les {mod}{r_m},{reg} 395 ')dnl 396 00001111,10110100,{mod}{reg}{r_m}:lfs {mod}{r_m},{reg} 397 00001111,10110101,{mod}{reg}{r_m}:lgs {mod}{r_m},{reg} 398 ifdef(`i386', 399 `00001111,00000001,{mod}010{r_m}:lgdt{w0} {mod}{r_m} 400 00001111,00000001,{mod}011{r_m}:lidt{w0} {mod}{r_m} 401 ', 402 `00001111,00000001,{mod}010{r_m}:lgdt {mod}{r_m} 403 00001111,00000001,{mod}011{r_m}:lidt {mod}{r_m} 404 ')dnl 405 00001111,00000000,{mod}010{16r_m}:lldt {mod}{16r_m} 406 00001111,00000001,{mod}110{16r_m}:lmsw {mod}{16r_m} 407 11110000:lock 408 1010110{w}:{R}lods {ds_si},{ax}{w} 409 11100010,{disp8}:loop {disp8} 410 11100001,{disp8}:loope {disp8} 411 11100000,{disp8}:loopne {disp8} 412 00001111,00000011,{mod}{reg}{16r_m}:lsl {mod}{16r_m},{reg} 413 00001111,10110010,{mod}{reg}{r_m}:lss {mod}{r_m},{reg} 414 00001111,00000000,{mod}011{16r_m}:ltr {mod}{16r_m} 415 1000100{w},{mod}{reg}{r_m}:mov {reg}{w},{mod}{r_m}{w} 416 1000101{w},{mod}{reg}{r_m}:mov {mod}{r_m}{w},{reg}{w} 417 1100011{w},{mod}000{r_m},{imm}:mov{w} {imm}{w},{mod}{r_m}{w} 418 1011{w}{oreg},{imm64}:mov {imm64}{w},{oreg}{w} 419 1010000{w},{abs}:mov {abs},{ax}{w} 420 1010001{w},{abs}:mov {ax}{w},{abs} 421 00001111,00100000,11{ccc}{reg64}:mov {ccc},{reg64} 422 00001111,00100010,11{ccc}{reg64}:mov {reg64},{ccc} 423 00001111,00100001,11{ddd}{reg64}:mov {ddd},{reg64} 424 00001111,00100011,11{ddd}{reg64}:mov {reg64},{ddd} 425 10001100,{mod}{sreg3}{r_m}:mov {sreg3},{mod}{r_m} 426 10001110,{mod}{sreg3}{r_m}:mov {mod}{r_m},{sreg3} 427 1010010{w}:{R}movs{w} {ds_si},{es_di} 428 00001111,10111110,{mod}{reg}{8r_m}:movsbl {mod}{8r_m},{reg} 429 00001111,10111111,{mod}{reg}{16r_m}:movswl {mod}{16r_m},{reg} 430 00001111,10110110,{mod}{reg}{8r_m}:movzbl {mod}{8r_m},{reg} 431 00001111,10110111,{mod}{reg}{16r_m}:movzwl {mod}{16r_m},{reg} 432 1111011{w},{mod}100{r_m}:mul{w} {mod}{r_m}{w} 433 1111011{w},{mod}011{r_m}:neg{w} {mod}{r_m}{w} 434 11110011,10010000:pause 435 ifdef(`i386', 436 `10010000:nop 437 ', 438 `10010000:INVALID 439 ')dnl 440 1111011{w},{mod}010{r_m}:not{w} {mod}{r_m}{w} 441 0000100{w},{mod}{reg}{r_m}:or {reg}{w},{mod}{r_m}{w} 442 0000101{w},{mod}{reg}{r_m}:or {mod}{r_m}{w},{reg}{w} 443 1000000{w},{mod}001{r_m},{imm}:or{w} {imm}{w},{mod}{r_m}{w} 444 1000001{w},{mod}001{r_m},{imms8}:or{w} {imms8},{mod}{r_m}{w} 445 0000110{w},{imm}:or {imm}{w},{ax}{w} 446 1110011{w},{imm8}:out {ax}{w},{imm8} 447 1110111{w}:out {ax}{w},{dx} 448 0110111{w}:{R}outs{w} {ds_si},{dx} 449 ifdef(`i386', 450 `10001111,{mod}000{r_m}:pop{w} {mod}{r_m} 451 ', 452 # XXX This is not the cleanest way... 453 `10001111,11000{reg64}:pop {reg64} 454 10001111,{mod}000{r_m}:pop{W} {mod}{r_m} 455 ')dnl 456 00001111,10{sreg3}001:pop{W} {sreg3} 457 10011101:popf{W} 458 # XXX This is not the cleanest way... 459 ifdef(`i386', 460 `11111111,{mod}110{r_m}:push{w} {mod}{r_m} 461 ', 462 `11111111,11110{reg64}:push {reg64} 463 11111111,{mod}110{r_m}:pushq {mod}{r_m} 464 ')dnl 465 ifdef(`i386', 466 `01010{reg}:push {reg} 467 01011{reg}:pop {reg} 468 ', 469 `01010{reg64}:push {reg64} 470 01011{reg64}:pop {reg64} 471 ')dnl 472 011010{s}0,{imm}:push{W} {imm}{s} 473 000{sreg2}110:push {sreg2} 474 00001111,10{sreg3}000:push{W} {sreg3} 475 ifdef(`i386', 476 `01100000:pusha{W} 477 01100001:popa{W} 478 ')dnl 479 10011100:pushf{W} 480 1101000{w},{mod}010{r_m}:rcl{w} {mod}{r_m}{w} 481 1101001{w},{mod}010{r_m}:rcl{w} %cl,{mod}{r_m}{w} 482 1100000{w},{mod}010{r_m},{imm8}:rcl{w} {imm8},{mod}{r_m}{w} 483 1101000{w},{mod}011{r_m}:rcr{w} {mod}{r_m}{w} 484 1101001{w},{mod}011{r_m}:rcr{w} %cl,{mod}{r_m}{w} 485 1100000{w},{mod}011{r_m},{imm8}:rcr{w} {imm8},{mod}{r_m}{w} 486 00001111,00110010:rdmsr 487 00001111,00110011:rdpmc 488 00001111,00110001:rdtsc 489 11000011:ret{W} 490 11000010,{imm16}:ret{W} {imm16} 491 11001011:lret 492 11001010,{imm16}:lret {imm16} 493 1101000{w},{mod}000{r_m}:rol{w} {mod}{r_m}{w} 494 1101001{w},{mod}000{r_m}:rol{w} %cl,{mod}{r_m}{w} 495 1100000{w},{mod}000{r_m},{imm8}:rol{w} {imm8},{mod}{r_m}{w} 496 1101000{w},{mod}001{r_m}:ror{w} {mod}{r_m}{w} 497 1101001{w},{mod}001{r_m}:ror{w} %cl,{mod}{r_m}{w} 498 1100000{w},{mod}001{r_m},{imm8}:ror{w} {imm8},{mod}{r_m}{w} 499 00001111,10101010:rsm 500 10011110:sahf 501 1101000{w},{mod}111{r_m}:sar{w} {mod}{r_m}{w} 502 1101001{w},{mod}111{r_m}:sar{w} %cl,{mod}{r_m}{w} 503 1100000{w},{mod}111{r_m},{imm8}:sar{w} {imm8},{mod}{r_m}{w} 504 0001100{w},{mod}{reg}{r_m}:sbb {reg}{w},{mod}{r_m}{w} 505 0001101{w},{mod}{reg}{r_m}:sbb {mod}{r_m}{w},{reg}{w} 506 0001110{w},{imm}:sbb {imm}{w},{ax}{w} 507 1000000{w},{mod}011{r_m},{imm}:sbb{w} {imm}{w},{mod}{r_m}{w} 508 1000001{w},{mod}011{r_m},{imms8}:sbb{w} {imms8},{mod}{r_m} 509 1010111{w}:{RE}scas {es_di},{ax}{w} 510 00001111,1001{tttn},{mod}000{r_m}:set{tttn} {mod}{r_m} 511 1101000{w},{mod}100{r_m}:shl{w} {mod}{r_m}{w} 512 1101001{w},{mod}100{r_m}:shl{w} %cl,{mod}{r_m}{w} 513 1100000{w},{mod}100{r_m},{imm8}:shl{w} {imm8},{mod}{r_m}{w} 514 1101000{w},{mod}101{r_m}:shr{w} {mod}{r_m}{w} 515 00001111,10100100,{mod}{reg}{r_m},{imm8}:shld {imm8},{reg},{mod}{r_m} 516 00001111,10100101,{mod}{reg}{r_m}:shld %cl,{reg},{mod}{r_m} 517 1101001{w},{mod}101{r_m}:shr{w} %cl,{mod}{r_m}{w} 518 1100000{w},{mod}101{r_m},{imm8}:shr{w} {imm8},{mod}{r_m}{w} 519 00001111,10101100,{mod}{reg}{r_m},{imm8}:shrd {imm8},{reg},{mod}{r_m} 520 00001111,10101101,{mod}{reg}{r_m}:shrd %cl,{reg},{mod}{r_m} 521 # ORDER 522 00001111,00000001,11000001:vmcall 523 00001111,00000001,11000010:vmlaunch 524 00001111,00000001,11000011:vmresume 525 00001111,00000001,11000100:vmxoff 526 00001111,01111000,{mod}{reg64}{64r_m}:vmread {reg64},{mod}{64r_m} 527 00001111,01111001,{mod}{reg64}{64r_m}:vmwrite {mod}{64r_m},{reg64} 528 ifdef(`i386', 529 `00001111,00000001,{mod}000{r_m}:sgdtl {mod}{r_m} 530 ', 531 `00001111,00000001,{mod}000{r_m}:sgdt {mod}{r_m} 532 ')dnl 533 # ORDER END 534 # ORDER 535 ifdef(`i386', 536 `00001111,00000001,11001000:monitor %eax,%ecx,%edx 537 00001111,00000001,11001001:mwait %eax,%ecx 538 ', 539 `00001111,00000001,11001000:monitor %rax,%rcx,%rdx 540 00001111,00000001,11001001:mwait %rax,%rcx 541 ')dnl 542 ifdef(`i386', 543 `00001111,00000001,{mod}001{r_m}:sidtl {mod}{r_m} 544 ', 545 `00001111,00000001,{mod}001{r_m}:sidt {mod}{r_m} 546 ')dnl 547 # ORDER END 548 00001111,00000000,{mod}000{r_m}:sldt {mod}{r_m} 549 00001111,00000001,{mod}100{r_m}:smsw {mod}{r_m} 550 11111001:stc 551 11111101:std 552 11111011:sti 553 1010101{w}:{R}stos {ax}{w},{es_di} 554 00001111,00000000,{mod}001{r_m}:str {mod}{r_m} 555 0010100{w},{mod}{reg}{r_m}:sub {reg}{w},{mod}{r_m}{w} 556 0010101{w},{mod}{reg}{r_m}:sub {mod}{r_m}{w},{reg}{w} 557 0010110{w},{imm}:sub {imm}{w},{ax}{w} 558 1000000{w},{mod}101{r_m},{imm}:sub{w} {imm}{w},{mod}{r_m}{w} 559 1000001{w},{mod}101{r_m},{imms8}:sub{w} {imms8},{mod}{r_m} 560 1000010{w},{mod}{reg}{r_m}:test {reg}{w},{mod}{r_m}{w} 561 1010100{w},{imm}:test {imm}{w},{ax}{w} 562 1111011{w},{mod}000{r_m},{imm}:test{w} {imm}{w},{mod}{r_m}{w} 563 00001111,00001011:ud2a 564 00001111,00000000,{mod}100{16r_m}:verr {mod}{16r_m} 565 00001111,00000000,{mod}101{16r_m}:verw {mod}{16r_m} 566 00001111,00001001:wbinvd 567 00001111,00001101,{mod}000{8r_m}:prefetch {mod}{8r_m} 568 00001111,00001101,{mod}001{8r_m}:prefetchw {mod}{8r_m} 569 00001111,00011000,{mod}000{r_m}:prefetchnta {mod}{r_m} 570 00001111,00011000,{mod}001{r_m}:prefetcht0 {mod}{r_m} 571 00001111,00011000,{mod}010{r_m}:prefetcht1 {mod}{r_m} 572 00001111,00011000,{mod}011{r_m}:prefetcht2 {mod}{r_m} 573 00001111,00011111,{mod}{reg}{r_m}:nop{w} {mod}{r_m} 574 00001111,00110000:wrmsr 575 00001111,1100000{w},{mod}{reg}{r_m}:xadd {reg}{w},{mod}{r_m}{w} 576 1000011{w},{mod}{reg}{r_m}:xchg {reg}{w},{mod}{r_m}{w} 577 10010{oreg}:xchg {ax},{oreg} 578 11010111:xlat {ds_bx} 579 0011000{w},{mod}{reg}{r_m}:xor {reg}{w},{mod}{r_m}{w} 580 0011001{w},{mod}{reg}{r_m}:xor {mod}{r_m}{w},{reg}{w} 581 0011010{w},{imm}:xor {imm}{w},{ax}{w} 582 1000000{w},{mod}110{r_m},{imm}:xor{w} {imm}{w},{mod}{r_m}{w} 583 1000001{w},{mod}110{r_m},{imms8}:xor{w} {imms8},{mod}{r_m} 584 00001111,01110111:emms 585 01100110,00001111,11011011,{Mod}{xmmreg}{R_m}:pand {Mod}{R_m},{xmmreg} 586 00001111,11011011,{MOD}{mmxreg}{R_M}:pand {MOD}{R_M},{mmxreg} 587 01100110,00001111,11011111,{Mod}{xmmreg}{R_m}:pandn {Mod}{R_m},{xmmreg} 588 00001111,11011111,{MOD}{mmxreg}{R_M}:pandn {MOD}{R_M},{mmxreg} 589 01100110,00001111,11110101,{Mod}{xmmreg}{R_m}:pmaddwd {Mod}{R_m},{xmmreg} 590 00001111,11110101,{MOD}{mmxreg}{R_M}:pmaddwd {MOD}{R_M},{mmxreg} 591 01100110,00001111,11101011,{Mod}{xmmreg}{R_m}:por {Mod}{R_m},{xmmreg} 592 00001111,11101011,{MOD}{mmxreg}{R_M}:por {MOD}{R_M},{mmxreg} 593 01100110,00001111,11101111,{Mod}{xmmreg}{R_m}:pxor {Mod}{R_m},{xmmreg} 594 00001111,11101111,{MOD}{mmxreg}{R_M}:pxor {MOD}{R_M},{mmxreg} 595 00001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg} 596 00001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg} 597 00001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqps {Mod}{R_m},{xmmreg} 598 00001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltps {Mod}{R_m},{xmmreg} 599 00001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpleps {Mod}{R_m},{xmmreg} 600 00001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordps {Mod}{R_m},{xmmreg} 601 00001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqps {Mod}{R_m},{xmmreg} 602 00001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltps {Mod}{R_m},{xmmreg} 603 00001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnleps {Mod}{R_m},{xmmreg} 604 00001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordps {Mod}{R_m},{xmmreg} 605 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqss {Mod}{R_m},{xmmreg} 606 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltss {Mod}{R_m},{xmmreg} 607 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpless {Mod}{R_m},{xmmreg} 608 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordss {Mod}{R_m},{xmmreg} 609 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqss {Mod}{R_m},{xmmreg} 610 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltss {Mod}{R_m},{xmmreg} 611 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnless {Mod}{R_m},{xmmreg} 612 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordss {Mod}{R_m},{xmmreg} 613 00001111,10101110,{mod}001{r_m}:fxrstor {mod}{r_m} 614 00001111,10101110,{mod}000{r_m}:fxsave {mod}{r_m} 615 00001111,10101110,{mod}010{r_m}:ldmxcsr {mod}{r_m} 616 00001111,10101110,{mod}011{r_m}:stmxcsr {mod}{r_m} 617 11110010,00001111,00010000,{Mod}{xmmreg}{R_m}:movsd {Mod}{R_m},{xmmreg} 618 11110011,00001111,00010000,{Mod}{xmmreg}{R_m}:movss {Mod}{R_m},{xmmreg} 619 01100110,00001111,00010000,{Mod}{xmmreg}{R_m}:movupd {Mod}{R_m},{xmmreg} 620 00001111,00010000,{Mod}{xmmreg}{R_m}:movups {Mod}{R_m},{xmmreg} 621 11110010,00001111,00010001,{Mod}{xmmreg}{R_m}:movsd {xmmreg},{Mod}{R_m} 622 11110011,00001111,00010001,{Mod}{xmmreg}{R_m}:movss {xmmreg},{Mod}{R_m} 623 01100110,00001111,00010001,{Mod}{xmmreg}{R_m}:movupd {xmmreg},{Mod}{R_m} 624 00001111,00010001,{Mod}{xmmreg}{R_m}:movups {xmmreg},{Mod}{R_m} 625 11110010,00001111,00010010,{Mod}{xmmreg}{R_m}:movddup {Mod}{R_m},{xmmreg} 626 11110011,00001111,00010010,{Mod}{xmmreg}{R_m}:movsldup {Mod}{R_m},{xmmreg} 627 01100110,00001111,00010010,{Mod}{xmmreg}{R_m}:movlpd {Mod}{R_m},{xmmreg} 628 00001111,00010010,11{xmmreg1}{xmmreg2}:movhlps {xmmreg2},{xmmreg1} 629 00001111,00010010,{Mod}{xmmreg}{R_m}:movlps {Mod}{R_m},{xmmreg} 630 01100110,00001111,00010011,11{xmmreg1}{xmmreg2}:movhlpd {xmmreg1},{xmmreg2} 631 00001111,00010011,11{xmmreg1}{xmmreg2}:movhlps {xmmreg1},{xmmreg2} 632 01100110,00001111,00010011,{Mod}{xmmreg}{R_m}:movlpd {xmmreg},{Mod}{R_m} 633 00001111,00010011,{Mod}{xmmreg}{R_m}:movlps {xmmreg},{Mod}{R_m} 634 01100110,00001111,00010100,{Mod}{xmmreg}{R_m}:unpcklpd {Mod}{R_m},{xmmreg} 635 00001111,00010100,{Mod}{xmmreg}{R_m}:unpcklps {Mod}{R_m},{xmmreg} 636 01100110,00001111,00010101,{Mod}{xmmreg}{R_m}:unpckhpd {Mod}{R_m},{xmmreg} 637 00001111,00010101,{Mod}{xmmreg}{R_m}:unpckhps {Mod}{R_m},{xmmreg} 638 11110011,00001111,00010110,{Mod}{xmmreg}{R_m}:movshdup {Mod}{R_m},{xmmreg} 639 01100110,00001111,00010110,{Mod}{xmmreg}{R_m}:movhpd {Mod}{R_m},{xmmreg} 640 00001111,00010110,11{xmmreg1}{xmmreg2}:movlhps {xmmreg2},{xmmreg1} 641 00001111,00010110,{Mod}{xmmreg}{R_m}:movhps {Mod}{R_m},{xmmreg} 642 01100110,00001111,00010111,11{xmmreg1}{xmmreg2}:movlhpd {xmmreg1},{xmmreg2} 643 00001111,00010111,11{xmmreg1}{xmmreg2}:movlhps {xmmreg1},{xmmreg2} 644 01100110,00001111,00010111,{Mod}{xmmreg}{R_m}:movhpd {xmmreg},{Mod}{R_m} 645 00001111,00010111,{Mod}{xmmreg}{R_m}:movhps {xmmreg},{Mod}{R_m} 646 01100110,00001111,00101000,{Mod}{xmmreg}{R_m}:movapd {Mod}{R_m},{xmmreg} 647 00001111,00101000,{Mod}{xmmreg}{R_m}:movaps {Mod}{R_m},{xmmreg} 648 01100110,00001111,00101001,{Mod}{xmmreg}{R_m}:movapd {xmmreg},{Mod}{R_m} 649 00001111,00101001,{Mod}{xmmreg}{R_m}:movaps {xmmreg},{Mod}{R_m} 650 11110010,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2sd {mod}{r_m},{xmmreg} 651 11110011,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2ss {mod}{r_m},{xmmreg} 652 01100110,00001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2pd {MOD}{R_M},{xmmreg} 653 00001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2ps {MOD}{R_M},{xmmreg} 654 01100110,00001111,00101011,{mod}{xmmreg}{r_m}:movntpd {xmmreg},{mod}{r_m} 655 00001111,00101011,{mod}{xmmreg}{r_m}:movntps {xmmreg},{mod}{r_m} 656 11110010,00001111,00101100,{Mod}{reg}{R_m}:cvttsd2si {Mod}{R_m},{reg} 657 11110011,00001111,00101100,{Mod}{reg}{R_m}:cvttss2si {Mod}{R_m},{reg} 658 01100110,00001111,00101100,{Mod}{mmxreg}{R_m}:cvttpd2pi {Mod}{R_m},{mmxreg} 659 00001111,00101100,{Mod}{mmxreg}{R_m}:cvttps2pi {Mod}{R_m},{mmxreg} 660 01100110,00001111,00101101,{Mod}{mmxreg}{R_m}:cvtpd2pi {Mod}{R_m},{mmxreg} 661 11110010,00001111,00101101,{Mod}{reg}{R_m}:cvtsd2si {Mod}{R_m},{reg} 662 11110011,00001111,00101101,{Mod}{reg}{R_m}:cvtss2si {Mod}{R_m},{reg} 663 00001111,00101101,{Mod}{mmxreg}{R_m}:cvtps2pi {Mod}{R_m},{mmxreg} 664 01100110,00001111,00101110,{Mod}{xmmreg}{R_m}:ucomisd {Mod}{R_m},{xmmreg} 665 00001111,00101110,{Mod}{xmmreg}{R_m}:ucomiss {Mod}{R_m},{xmmreg} 666 01100110,00001111,00101111,{Mod}{xmmreg}{R_m}:comisd {Mod}{R_m},{xmmreg} 667 00001111,00101111,{Mod}{xmmreg}{R_m}:comiss {Mod}{R_m},{xmmreg} 668 00001111,00110111:getsec 669 01100110,00001111,01010000,11{reg}{xmmreg}:movmskpd {xmmreg},{reg} 670 00001111,01010000,11{reg}{xmmreg}:movmskps {xmmreg},{reg} 671 01100110,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtpd {Mod}{R_m},{xmmreg} 672 11110010,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtsd {Mod}{R_m},{xmmreg} 673 11110011,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtss {Mod}{R_m},{xmmreg} 674 00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtps {Mod}{R_m},{xmmreg} 675 11110011,00001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtss {Mod}{R_m},{xmmreg} 676 00001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtps {Mod}{R_m},{xmmreg} 677 11110011,00001111,01010011,{Mod}{xmmreg}{R_m}:rcpss {Mod}{R_m},{xmmreg} 678 00001111,01010011,{Mod}{xmmreg}{R_m}:rcpps {Mod}{R_m},{xmmreg} 679 01100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg} 680 00001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg} 681 01100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg} 682 00001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg} 683 01100110,00001111,01010110,{Mod}{xmmreg}{R_m}:orpd {Mod}{R_m},{xmmreg} 684 00001111,01010110,{Mod}{xmmreg}{R_m}:orps {Mod}{R_m},{xmmreg} 685 01100110,00001111,01010111,{Mod}{xmmreg}{R_m}:xorpd {Mod}{R_m},{xmmreg} 686 00001111,01010111,{Mod}{xmmreg}{R_m}:xorps {Mod}{R_m},{xmmreg} 687 11110010,00001111,01011000,{Mod}{xmmreg}{R_m}:addsd {Mod}{R_m},{xmmreg} 688 11110011,00001111,01011000,{Mod}{xmmreg}{R_m}:addss {Mod}{R_m},{xmmreg} 689 01100110,00001111,01011000,{Mod}{xmmreg}{R_m}:addpd {Mod}{R_m},{xmmreg} 690 00001111,01011000,{Mod}{xmmreg}{R_m}:addps {Mod}{R_m},{xmmreg} 691 11110010,00001111,01011001,{Mod}{xmmreg}{R_m}:mulsd {Mod}{R_m},{xmmreg} 692 11110011,00001111,01011001,{Mod}{xmmreg}{R_m}:mulss {Mod}{R_m},{xmmreg} 693 01100110,00001111,01011001,{Mod}{xmmreg}{R_m}:mulpd {Mod}{R_m},{xmmreg} 694 00001111,01011001,{Mod}{xmmreg}{R_m}:mulps {Mod}{R_m},{xmmreg} 695 11110010,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtsd2ss {Mod}{R_m},{xmmreg} 696 11110011,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtss2sd {Mod}{R_m},{xmmreg} 697 01100110,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtpd2ps {Mod}{R_m},{xmmreg} 698 00001111,01011010,{Mod}{xmmreg}{R_m}:cvtps2pd {Mod}{R_m},{xmmreg} 699 01100110,00001111,01011011,{Mod}{xmmreg}{R_m}:cvtps2dq {Mod}{R_m},{xmmreg} 700 11110011,00001111,01011011,{Mod}{xmmreg}{R_m}:cvttps2dq {Mod}{R_m},{xmmreg} 701 00001111,01011011,{Mod}{xmmreg}{R_m}:cvtdq2ps {Mod}{R_m},{xmmreg} 702 11110010,00001111,01011100,{Mod}{xmmreg}{R_m}:subsd {Mod}{R_m},{xmmreg} 703 11110011,00001111,01011100,{Mod}{xmmreg}{R_m}:subss {Mod}{R_m},{xmmreg} 704 01100110,00001111,01011100,{Mod}{xmmreg}{R_m}:subpd {Mod}{R_m},{xmmreg} 705 00001111,01011100,{Mod}{xmmreg}{R_m}:subps {Mod}{R_m},{xmmreg} 706 11110010,00001111,01011101,{Mod}{xmmreg}{R_m}:minsd {Mod}{R_m},{xmmreg} 707 11110011,00001111,01011101,{Mod}{xmmreg}{R_m}:minss {Mod}{R_m},{xmmreg} 708 01100110,00001111,01011101,{Mod}{xmmreg}{R_m}:minpd {Mod}{R_m},{xmmreg} 709 00001111,01011101,{Mod}{xmmreg}{R_m}:minps {Mod}{R_m},{xmmreg} 710 11110010,00001111,01011110,{Mod}{xmmreg}{R_m}:divsd {Mod}{R_m},{xmmreg} 711 11110011,00001111,01011110,{Mod}{xmmreg}{R_m}:divss {Mod}{R_m},{xmmreg} 712 01100110,00001111,01011110,{Mod}{xmmreg}{R_m}:divpd {Mod}{R_m},{xmmreg} 713 00001111,01011110,{Mod}{xmmreg}{R_m}:divps {Mod}{R_m},{xmmreg} 714 11110010,00001111,01011111,{Mod}{xmmreg}{R_m}:maxsd {Mod}{R_m},{xmmreg} 715 11110011,00001111,01011111,{Mod}{xmmreg}{R_m}:maxss {Mod}{R_m},{xmmreg} 716 01100110,00001111,01011111,{Mod}{xmmreg}{R_m}:maxpd {Mod}{R_m},{xmmreg} 717 00001111,01011111,{Mod}{xmmreg}{R_m}:maxps {Mod}{R_m},{xmmreg} 718 01100110,00001111,01100000,{Mod}{xmmreg}{R_m}:punpcklbw {Mod}{R_m},{xmmreg} 719 00001111,01100000,{MOD}{mmxreg}{R_M}:punpcklbw {MOD}{R_M},{mmxreg} 720 01100110,00001111,01100001,{Mod}{xmmreg}{R_m}:punpcklwd {Mod}{R_m},{xmmreg} 721 00001111,01100001,{MOD}{mmxreg}{R_M}:punpcklwd {MOD}{R_M},{mmxreg} 722 01100110,00001111,01100010,{Mod}{xmmreg}{R_m}:punpckldq {Mod}{R_m},{xmmreg} 723 00001111,01100010,{MOD}{mmxreg}{R_M}:punpckldq {MOD}{R_M},{mmxreg} 724 01100110,00001111,01100011,{Mod}{xmmreg}{R_m}:packsswb {Mod}{R_m},{xmmreg} 725 00001111,01100011,{MOD}{mmxreg}{R_M}:packsswb {MOD}{R_M},{mmxreg} 726 01100110,00001111,01100100,{Mod}{xmmreg}{R_m}:pcmpgtb {Mod}{R_m},{xmmreg} 727 00001111,01100100,{MOD}{mmxreg}{R_M}:pcmpgtb {MOD}{R_M},{mmxreg} 728 01100110,00001111,01100101,{Mod}{xmmreg}{R_m}:pcmpgtw {Mod}{R_m},{xmmreg} 729 00001111,01100101,{MOD}{mmxreg}{R_M}:pcmpgtw {MOD}{R_M},{mmxreg} 730 01100110,00001111,01100110,{Mod}{xmmreg}{R_m}:pcmpgtd {Mod}{R_m},{xmmreg} 731 00001111,01100110,{MOD}{mmxreg}{R_M}:pcmpgtd {MOD}{R_M},{mmxreg} 732 01100110,00001111,01100111,{Mod}{xmmreg}{R_m}:packuswb {Mod}{R_m},{xmmreg} 733 00001111,01100111,{MOD}{mmxreg}{R_M}:packuswb {MOD}{R_M},{mmxreg} 734 01100110,00001111,01101000,{Mod}{xmmreg}{R_m}:punpckhbw {Mod}{R_m},{xmmreg} 735 00001111,01101000,{MOD}{mmxreg}{R_M}:punpckhbw {MOD}{R_M},{mmxreg} 736 01100110,00001111,01101001,{Mod}{xmmreg}{R_m}:punpckhwd {Mod}{R_m},{xmmreg} 737 00001111,01101001,{MOD}{mmxreg}{R_M}:punpckhwd {MOD}{R_M},{mmxreg} 738 01100110,00001111,01101010,{Mod}{xmmreg}{R_m}:punpckhdq {Mod}{R_m},{xmmreg} 739 00001111,01101010,{MOD}{mmxreg}{R_M}:punpckhdq {MOD}{R_M},{mmxreg} 740 01100110,00001111,01101011,{Mod}{xmmreg}{R_m}:packssdw {Mod}{R_m},{xmmreg} 741 00001111,01101011,{MOD}{mmxreg}{R_M}:packssdw {MOD}{R_M},{mmxreg} 742 01100110,00001111,01101100,{Mod}{xmmreg}{R_m}:punpcklqdq {Mod}{R_m},{xmmreg} 743 01100110,00001111,01101101,{Mod}{xmmreg}{R_m}:punpckhqdq {Mod}{R_m},{xmmreg} 744 01100110,00001111,01101110,{mod}{xmmreg}{r_m}:movd {mod}{r_m},{xmmreg} 745 00001111,01101110,{mod}{mmxreg}{r_m}:movd {mod}{r_m},{mmxreg} 746 01100110,00001111,01101111,{Mod}{xmmreg}{R_m}:movdqa {Mod}{R_m},{xmmreg} 747 11110011,00001111,01101111,{Mod}{xmmreg}{R_m}:movdqu {Mod}{R_m},{xmmreg} 748 00001111,01101111,{MOD}{mmxreg}{R_M}:movq {MOD}{R_M},{mmxreg} 749 01100110,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshufd {imm8},{Mod}{R_m},{xmmreg} 750 11110010,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshuflw {imm8},{Mod}{R_m},{xmmreg} 751 11110011,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshufhw {imm8},{Mod}{R_m},{xmmreg} 752 00001111,01110000,{MOD}{mmxreg}{R_M},{imm8}:pshufw {imm8},{MOD}{R_M},{mmxreg} 753 01100110,00001111,01110100,{Mod}{xmmreg}{R_m}:pcmpeqb {Mod}{R_m},{xmmreg} 754 00001111,01110100,{MOD}{mmxreg}{R_M}:pcmpeqb {MOD}{R_M},{mmxreg} 755 01100110,00001111,01110101,{Mod}{xmmreg}{R_m}:pcmpeqw {Mod}{R_m},{xmmreg} 756 00001111,01110101,{MOD}{mmxreg}{R_M}:pcmpeqw {MOD}{R_M},{mmxreg} 757 01100110,00001111,01110110,{Mod}{xmmreg}{R_m}:pcmpeqd {Mod}{R_m},{xmmreg} 758 00001111,01110110,{MOD}{mmxreg}{R_M}:pcmpeqd {MOD}{R_M},{mmxreg} 759 01100110,00001111,01111100,{Mod}{xmmreg}{R_m}:haddpd {Mod}{R_m},{xmmreg} 760 11110010,00001111,01111100,{Mod}{xmmreg}{R_m}:haddps {Mod}{R_m},{xmmreg} 761 01100110,00001111,01111101,{Mod}{xmmreg}{R_m}:hsubpd {Mod}{R_m},{xmmreg} 762 11110010,00001111,01111101,{Mod}{xmmreg}{R_m}:hsubps {Mod}{R_m},{xmmreg} 763 01100110,00001111,01111110,{mod}{xmmreg}{r_m}:movd {xmmreg},{mod}{r_m} 764 11110011,00001111,01111110,{Mod}{xmmreg}{R_m}:movq {Mod}{R_m},{xmmreg} 765 00001111,01111110,{mod}{mmxreg}{r_m}:movd {mmxreg},{mod}{r_m} 766 01100110,00001111,01111111,{Mod}{xmmreg}{R_m}:movdqa {xmmreg},{Mod}{R_m} 767 11110011,00001111,01111111,{Mod}{xmmreg}{R_m}:movdqu {xmmreg},{Mod}{R_m} 768 00001111,01111111,{MOD}{mmxreg}{R_M}:movq {mmxreg},{MOD}{R_M} 769 00001111,11000011,{mod}{reg}{r_m}:movnti {reg},{mod}{r_m} 770 01100110,00001111,11000100,{mod}{xmmreg}{r_m},{imm8}:pinsrw {imm8},{mod}{r_m},{xmmreg} 771 00001111,11000100,{mod}{mmxreg}{r_m},{imm8}:pinsrw {imm8},{mod}{r_m},{mmxreg} 772 01100110,00001111,11000101,11{reg}{xmmreg},{imm8}:pextrw {imm8},{xmmreg},{reg} 773 00001111,11000101,11{reg}{mmxreg},{imm8}:pextrw {imm8},{mmxreg},{reg} 774 01100110,00001111,11000110,{Mod}{xmmreg}{R_m},{imm8}:shufpd {imm8},{Mod}{R_m},{xmmreg} 775 00001111,11000110,{Mod}{xmmreg}{R_m},{imm8}:shufps {imm8},{Mod}{R_m},{xmmreg} 776 01100110,00001111,11010001,{Mod}{xmmreg}{R_m}:psrlw {Mod}{R_m},{xmmreg} 777 00001111,11010001,{MOD}{mmxreg}{R_M}:psrlw {MOD}{R_M},{mmxreg} 778 01100110,00001111,11010010,{Mod}{xmmreg}{R_m}:psrld {Mod}{R_m},{xmmreg} 779 00001111,11010010,{MOD}{mmxreg}{R_M}:psrld {MOD}{R_M},{mmxreg} 780 01100110,00001111,11010011,{Mod}{xmmreg}{R_m}:psrlq {Mod}{R_m},{xmmreg} 781 00001111,11010011,{MOD}{mmxreg}{R_M}:psrlq {MOD}{R_M},{mmxreg} 782 01100110,00001111,11010100,{Mod}{xmmreg}{R_m}:paddq {Mod}{R_m},{xmmreg} 783 00001111,11010100,{MOD}{mmxreg}{R_M}:paddq {MOD}{R_M},{mmxreg} 784 01100110,00001111,11010101,{Mod}{xmmreg}{R_m}:pmullw {Mod}{R_m},{xmmreg} 785 00001111,11010101,{MOD}{mmxreg}{R_M}:pmullw {MOD}{R_M},{mmxreg} 786 01100110,00001111,11010110,{Mod}{xmmreg}{R_m}:movq {xmmreg},{Mod}{R_m} 787 11110010,00001111,11010110,11{mmxreg}{xmmreg}:movdq2q {xmmreg},{mmxreg} 788 11110011,00001111,11010110,11{xmmreg}{mmxreg}:movq2dq {mmxreg},{xmmreg} 789 01100110,00001111,11010111,11{reg}{xmmreg}:pmovmskb {xmmreg},{reg} 790 00001111,11010111,11{reg}{mmxreg}:pmovmskb {mmxreg},{reg} 791 01100110,00001111,11011000,{Mod}{xmmreg}{R_m}:psubusb {Mod}{R_m},{xmmreg} 792 00001111,11011000,{MOD}{mmxreg}{R_M}:psubusb {MOD}{R_M},{mmxreg} 793 01100110,00001111,11011001,{Mod}{xmmreg}{R_m}:psubusw {Mod}{R_m},{xmmreg} 794 00001111,11011001,{MOD}{mmxreg}{R_M}:psubusw {MOD}{R_M},{mmxreg} 795 01100110,00001111,11011010,{Mod}{xmmreg}{R_m}:pminub {Mod}{R_m},{xmmreg} 796 00001111,11011010,{MOD}{mmxreg}{R_M}:pminub {MOD}{R_M},{mmxreg} 797 01100110,00001111,11011100,{Mod}{xmmreg}{R_m}:paddusb {Mod}{R_m},{xmmreg} 798 00001111,11011100,{MOD}{mmxreg}{R_M}:paddusb {MOD}{R_M},{mmxreg} 799 01100110,00001111,11011101,{Mod}{xmmreg}{R_m}:paddusw {Mod}{R_m},{xmmreg} 800 00001111,11011101,{MOD}{mmxreg}{R_M}:paddusw {MOD}{R_M},{mmxreg} 801 01100110,00001111,11011110,{Mod}{xmmreg}{R_m}:pmaxub {Mod}{R_m},{xmmreg} 802 00001111,11011110,{MOD}{mmxreg}{R_M}:pmaxub {MOD}{R_M},{mmxreg} 803 01100110,00001111,11100000,{Mod}{xmmreg}{R_m}:pavgb {Mod}{R_m},{xmmreg} 804 00001111,11100000,{MOD}{mmxreg}{R_M}:pavgb {MOD}{R_M},{mmxreg} 805 01100110,00001111,11100001,{Mod}{xmmreg}{R_m}:psraw {Mod}{R_m},{xmmreg} 806 00001111,11100001,{MOD}{mmxreg}{R_M}:psraw {MOD}{R_M},{mmxreg} 807 01100110,00001111,11100010,{Mod}{xmmreg}{R_m}:psrad {Mod}{R_m},{xmmreg} 808 00001111,11100010,{MOD}{mmxreg}{R_M}:psrad {MOD}{R_M},{mmxreg} 809 01100110,00001111,11100011,{Mod}{xmmreg}{R_m}:pavgw {Mod}{R_m},{xmmreg} 810 00001111,11100011,{MOD}{mmxreg}{R_M}:pavgw {MOD}{R_M},{mmxreg} 811 01100110,00001111,11100100,{Mod}{xmmreg}{R_m}:pmulhuw {Mod}{R_m},{xmmreg} 812 00001111,11100100,{MOD}{mmxreg}{R_M}:pmulhuw {MOD}{R_M},{mmxreg} 813 01100110,00001111,11100101,{Mod}{xmmreg}{R_m}:pmulhw {Mod}{R_m},{xmmreg} 814 00001111,11100101,{MOD}{mmxreg}{R_M}:pmulhw {MOD}{R_M},{mmxreg} 815 01100110,00001111,11100111,{Mod}{xmmreg}{R_m}:movntdq {xmmreg},{Mod}{R_m} 816 00001111,11100111,{MOD}{mmxreg}{R_M}:movntq {mmxreg},{MOD}{R_M} 817 01100110,00001111,11101000,{Mod}{xmmreg}{R_m}:psubsb {Mod}{R_m},{xmmreg} 818 00001111,11101000,{MOD}{mmxreg}{R_M}:psubsb {MOD}{R_M},{mmxreg} 819 01100110,00001111,11101001,{Mod}{xmmreg}{R_m}:psubsw {Mod}{R_m},{xmmreg} 820 00001111,11101001,{MOD}{mmxreg}{R_M}:psubsw {MOD}{R_M},{mmxreg} 821 01100110,00001111,11101010,{Mod}{xmmreg}{R_m}:pminsw {Mod}{R_m},{xmmreg} 822 00001111,11101010,{MOD}{mmxreg}{R_M}:pminsw {MOD}{R_M},{mmxreg} 823 01100110,00001111,11101100,{Mod}{xmmreg}{R_m}:paddsb {Mod}{R_m},{xmmreg} 824 00001111,11101100,{MOD}{mmxreg}{R_M}:paddsb {MOD}{R_M},{mmxreg} 825 01100110,00001111,11101101,{Mod}{xmmreg}{R_m}:paddsw {Mod}{R_m},{xmmreg} 826 00001111,11101101,{MOD}{mmxreg}{R_M}:paddsw {MOD}{R_M},{mmxreg} 827 01100110,00001111,11101110,{Mod}{xmmreg}{R_m}:pmaxsw {Mod}{R_m},{xmmreg} 828 00001111,11101110,{MOD}{mmxreg}{R_M}:pmaxsw {MOD}{R_M},{mmxreg} 829 11110010,00001111,11110000,{mod}{xmmreg}{r_m}:lddqu {mod}{r_m},{xmmreg} 830 01100110,00001111,11110001,{Mod}{xmmreg}{R_m}:psllw {Mod}{R_m},{xmmreg} 831 00001111,11110001,{MOD}{mmxreg}{R_M}:psllw {MOD}{R_M},{mmxreg} 832 01100110,00001111,11110010,{Mod}{xmmreg}{R_m}:pslld {Mod}{R_m},{xmmreg} 833 00001111,11110010,{MOD}{mmxreg}{R_M}:pslld {MOD}{R_M},{mmxreg} 834 01100110,00001111,11110011,{Mod}{xmmreg}{R_m}:psllq {Mod}{R_m},{xmmreg} 835 00001111,11110011,{MOD}{mmxreg}{R_M}:psllq {MOD}{R_M},{mmxreg} 836 01100110,00001111,11110100,{Mod}{xmmreg}{R_m}:pmuludq {Mod}{R_m},{xmmreg} 837 00001111,11110100,{MOD}{mmxreg}{R_M}:pmuludq {MOD}{R_M},{mmxreg} 838 01100110,00001111,11110110,{Mod}{xmmreg}{R_m}:psadbw {Mod}{R_m},{xmmreg} 839 00001111,11110110,{MOD}{mmxreg}{R_M}:psadbw {MOD}{R_M},{mmxreg} 840 01100110,00001111,11110111,11{xmmreg1}{xmmreg2}:maskmovdqu {xmmreg2},{xmmreg1} 841 00001111,11110111,11{mmxreg1}{mmxreg2}:maskmovq {mmxreg2},{mmxreg1} 842 01100110,00001111,11111000,{Mod}{xmmreg}{R_m}:psubb {Mod}{R_m},{xmmreg} 843 00001111,11111000,{MOD}{mmxreg}{R_M}:psubb {MOD}{R_M},{mmxreg} 844 01100110,00001111,11111001,{Mod}{xmmreg}{R_m}:psubw {Mod}{R_m},{xmmreg} 845 00001111,11111001,{MOD}{mmxreg}{R_M}:psubw {MOD}{R_M},{mmxreg} 846 01100110,00001111,11111010,{Mod}{xmmreg}{R_m}:psubd {Mod}{R_m},{xmmreg} 847 00001111,11111010,{MOD}{mmxreg}{R_M}:psubd {MOD}{R_M},{mmxreg} 848 01100110,00001111,11111011,{Mod}{xmmreg}{R_m}:psubq {Mod}{R_m},{xmmreg} 849 00001111,11111011,{MOD}{mmxreg}{R_M}:psubq {MOD}{R_M},{mmxreg} 850 01100110,00001111,11111100,{Mod}{xmmreg}{R_m}:paddb {Mod}{R_m},{xmmreg} 851 00001111,11111100,{MOD}{mmxreg}{R_M}:paddb {MOD}{R_M},{mmxreg} 852 01100110,00001111,11111101,{Mod}{xmmreg}{R_m}:paddw {Mod}{R_m},{xmmreg} 853 00001111,11111101,{MOD}{mmxreg}{R_M}:paddw {MOD}{R_M},{mmxreg} 854 01100110,00001111,11111110,{Mod}{xmmreg}{R_m}:paddd {Mod}{R_m},{xmmreg} 855 00001111,11111110,{MOD}{mmxreg}{R_M}:paddd {MOD}{R_M},{mmxreg} 856 01100110,00001111,00111000,00000000,{Mod}{xmmreg}{R_m}:pshufb {Mod}{R_m},{xmmreg} 857 00001111,00111000,00000000,{MOD}{mmxreg}{R_M}:pshufb {MOD}{R_M},{mmxreg} 858 01100110,00001111,00111000,00000001,{Mod}{xmmreg}{R_m}:phaddw {Mod}{R_m},{xmmreg} 859 00001111,00111000,00000001,{MOD}{mmxreg}{R_M}:phaddw {MOD}{R_M},{mmxreg} 860 01100110,00001111,00111000,00000010,{Mod}{xmmreg}{R_m}:phaddd {Mod}{R_m},{xmmreg} 861 00001111,00111000,00000010,{MOD}{mmxreg}{R_M}:phaddd {MOD}{R_M},{mmxreg} 862 01100110,00001111,00111000,00000011,{Mod}{xmmreg}{R_m}:phaddsw {Mod}{R_m},{xmmreg} 863 00001111,00111000,00000011,{MOD}{mmxreg}{R_M}:phaddsw {MOD}{R_M},{mmxreg} 864 01100110,00001111,00111000,00000100,{Mod}{xmmreg}{R_m}:pmaddubsw {Mod}{R_m},{xmmreg} 865 00001111,00111000,00000100,{MOD}{mmxreg}{R_M}:pmaddubsw {MOD}{R_M},{mmxreg} 866 01100110,00001111,00111000,00000101,{Mod}{xmmreg}{R_m}:phsubw {Mod}{R_m},{xmmreg} 867 00001111,00111000,00000101,{MOD}{mmxreg}{R_M}:phsubw {MOD}{R_M},{mmxreg} 868 01100110,00001111,00111000,00000110,{Mod}{xmmreg}{R_m}:phsubd {Mod}{R_m},{xmmreg} 869 00001111,00111000,00000110,{MOD}{mmxreg}{R_M}:phsubd {MOD}{R_M},{mmxreg} 870 01100110,00001111,00111000,00000111,{Mod}{xmmreg}{R_m}:phsubsw {Mod}{R_m},{xmmreg} 871 00001111,00111000,00000111,{MOD}{mmxreg}{R_M}:phsubsw {MOD}{R_M},{mmxreg} 872 01100110,00001111,00111000,00001000,{Mod}{xmmreg}{R_m}:psignb {Mod}{R_m},{xmmreg} 873 00001111,00111000,00001000,{MOD}{mmxreg}{R_M}:psignb {MOD}{R_M},{mmxreg} 874 01100110,00001111,00111000,00001001,{Mod}{xmmreg}{R_m}:psignw {Mod}{R_m},{xmmreg} 875 00001111,00111000,00001001,{MOD}{mmxreg}{R_M}:psignw {MOD}{R_M},{mmxreg} 876 01100110,00001111,00111000,00001010,{Mod}{xmmreg}{R_m}:psignd {Mod}{R_m},{xmmreg} 877 00001111,00111000,00001010,{MOD}{mmxreg}{R_M}:psignd {MOD}{R_M},{mmxreg} 878 01100110,00001111,00111000,00001011,{Mod}{xmmreg}{R_m}:pmulhrsw {Mod}{R_m},{xmmreg} 879 00001111,00111000,00001011,{MOD}{mmxreg}{R_M}:pmulhrsw {MOD}{R_M},{mmxreg} 880 01100110,00001111,00111000,00011100,{Mod}{xmmreg}{R_m}:pabsb {Mod}{R_m},{xmmreg} 881 00001111,00111000,00011100,{MOD}{mmxreg}{R_M}:pabsb {MOD}{R_M},{mmxreg} 882 01100110,00001111,00111000,00011101,{Mod}{xmmreg}{R_m}:pabsw {Mod}{R_m},{xmmreg} 883 00001111,00111000,00011101,{MOD}{mmxreg}{R_M}:pabsw {MOD}{R_M},{mmxreg} 884 01100110,00001111,00111000,00011110,{Mod}{xmmreg}{R_m}:pabsd {Mod}{R_m},{xmmreg} 885 00001111,00111000,00011110,{MOD}{mmxreg}{R_M}:pabsd {MOD}{R_M},{mmxreg} 886 01100110,00001111,00111010,00001111,{Mod}{xmmreg}{R_m},{imm8}:palignr {imm8},{Mod}{R_m},{xmmreg} 887 00001111,00111010,00001111,{MOD}{mmxreg}{R_M},{imm8}:palignr {imm8},{MOD}{R_M},{mmxreg} 888 01100110,00001111,11000111,{mod}110{r_m}:vmclear {mod}{r_m} 889 11110011,00001111,11000111,{mod}110{r_m}:vmxon {mod}{r_m} 890 00001111,11000111,{mod}110{r_m}:vmptrld {mod}{r_m} 891 00001111,11000111,{mod}111{r_m}:vmptrst {mod}{r_m} 892 01100110,00001111,01110001,11010{xmmreg},{imm8}:psrlw {imm8},{xmmreg} 893 00001111,01110001,11010{mmxreg},{imm8}:psrlw {imm8},{mmxreg} 894 01100110,00001111,01110001,11100{xmmreg},{imm8}:psraw {imm8},{xmmreg} 895 00001111,01110001,11100{mmxreg},{imm8}:psraw {imm8},{mmxreg} 896 01100110,00001111,01110001,11110{xmmreg},{imm8}:psllw {imm8},{xmmreg} 897 00001111,01110001,11110{mmxreg},{imm8}:psllw {imm8},{mmxreg} 898 01100110,00001111,01110010,11010{xmmreg},{imm8}:psrld {imm8},{xmmreg} 899 00001111,01110010,11010{mmxreg},{imm8}:psrld {imm8},{mmxreg} 900 01100110,00001111,01110010,11100{xmmreg},{imm8}:psrad {imm8},{xmmreg} 901 00001111,01110010,11100{mmxreg},{imm8}:psrad {imm8},{mmxreg} 902 01100110,00001111,01110010,11110{xmmreg},{imm8}:pslld {imm8},{xmmreg} 903 00001111,01110010,11110{mmxreg},{imm8}:pslld {imm8},{mmxreg} 904 01100110,00001111,01110011,11010{xmmreg},{imm8}:psrlq {imm8},{xmmreg} 905 00001111,01110011,11010{mmxreg},{imm8}:psrlq {imm8},{mmxreg} 906 01100110,00001111,01110011,11011{xmmreg},{imm8}:psrldq {imm8},{xmmreg} 907 01100110,00001111,01110011,11110{xmmreg},{imm8}:psllq {imm8},{xmmreg} 908 00001111,01110011,11110{mmxreg},{imm8}:psllq {imm8},{mmxreg} 909 01100110,00001111,01110011,11111{xmmreg},{imm8}:pslldq {imm8},{xmmreg} 910 00001111,10101110,11101000:lfence 911 00001111,10101110,11110000:mfence 912 00001111,10101110,11111000:sfence 913 00001111,10101110,{mod}111{r_m}:clflush {mod}{r_m} 914 00001111,00001111,{MOD}{mmxreg}{R_M}:INVALID {MOD}{R_M},{mmxreg} 915 01100110,00001111,00111010,00001100,{Mod}{xmmreg}{R_m},{imm8}:blendps {imm8},{Mod}{R_m},{xmmreg} 916 01100110,00001111,00111010,00001101,{Mod}{xmmreg}{R_m},{imm8}:blendpd {imm8},{Mod}{R_m},{xmmreg} 917 01100110,00001111,00111000,00010100,{Mod}{xmmreg}{R_m}:blendvps %xmm0,{Mod}{R_m},{xmmreg} 918 01100110,00001111,00111000,00010101,{Mod}{xmmreg}{R_m}:blendvpd %xmm0,{Mod}{R_m},{xmmreg} 919 # ORDER: 920 dnl Many previous entries depend on this being last. 921 000{sreg2}111:pop {sreg2} 922 # ORDER END: 923
