1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * ioc.h: Definitions for SGI I/O Controller 7 * 8 * Copyright (C) 1996 David S. Miller 9 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle 10 * Copyright (C) 2001, 2003 Ladislav Michl 11 */ 12 13 #ifndef _SGI_IOC_H 14 #define _SGI_IOC_H 15 16 #include <linux/types.h> 17 #include <asm/sgi/pi1.h> 18 19 /* 20 * All registers are 8-bit wide alligned on 32-bit boundary. Bad things 21 * happen if you try word access them. You have been warned. 22 */ 23 24 struct sgioc_uart_regs { 25 u8 _ctrl1[3]; 26 volatile u8 ctrl1; 27 u8 _data1[3]; 28 volatile u8 data1; 29 u8 _ctrl2[3]; 30 volatile u8 ctrl2; 31 u8 _data2[3]; 32 volatile u8 data2; 33 }; 34 35 struct sgioc_keyb_regs { 36 u8 _data[3]; 37 volatile u8 data; 38 u8 _command[3]; 39 volatile u8 command; 40 }; 41 42 struct sgint_regs { 43 u8 _istat0[3]; 44 volatile u8 istat0; /* Interrupt status zero */ 45 #define SGINT_ISTAT0_FFULL 0x01 46 #define SGINT_ISTAT0_SCSI0 0x02 47 #define SGINT_ISTAT0_SCSI1 0x04 48 #define SGINT_ISTAT0_ENET 0x08 49 #define SGINT_ISTAT0_GFXDMA 0x10 50 #define SGINT_ISTAT0_PPORT 0x20 51 #define SGINT_ISTAT0_HPC2 0x40 52 #define SGINT_ISTAT0_LIO2 0x80 53 u8 _imask0[3]; 54 volatile u8 imask0; /* Interrupt mask zero */ 55 u8 _istat1[3]; 56 volatile u8 istat1; /* Interrupt status one */ 57 #define SGINT_ISTAT1_ISDNI 0x01 58 #define SGINT_ISTAT1_PWR 0x02 59 #define SGINT_ISTAT1_ISDNH 0x04 60 #define SGINT_ISTAT1_LIO3 0x08 61 #define SGINT_ISTAT1_HPC3 0x10 62 #define SGINT_ISTAT1_AFAIL 0x20 63 #define SGINT_ISTAT1_VIDEO 0x40 64 #define SGINT_ISTAT1_GIO2 0x80 65 u8 _imask1[3]; 66 volatile u8 imask1; /* Interrupt mask one */ 67 u8 _vmeistat[3]; 68 volatile u8 vmeistat; /* VME interrupt status */ 69 u8 _cmeimask0[3]; 70 volatile u8 cmeimask0; /* VME interrupt mask zero */ 71 u8 _cmeimask1[3]; 72 volatile u8 cmeimask1; /* VME interrupt mask one */ 73 u8 _cmepol[3]; 74 volatile u8 cmepol; /* VME polarity */ 75 u8 _tclear[3]; 76 volatile u8 tclear; 77 u8 _errstat[3]; 78 volatile u8 errstat; /* Error status reg, reserved on INT2 */ 79 u32 _unused0[2]; 80 u8 _tcnt0[3]; 81 volatile u8 tcnt0; /* counter 0 */ 82 u8 _tcnt1[3]; 83 volatile u8 tcnt1; /* counter 1 */ 84 u8 _tcnt2[3]; 85 volatile u8 tcnt2; /* counter 2 */ 86 u8 _tcword[3]; 87 volatile u8 tcword; /* control word */ 88 #define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */ 89 #define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */ 90 #define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */ 91 #define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */ 92 #define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */ 93 #define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */ 94 #define SGINT_TCWORD_MSWST 0x08 /* Software strobe */ 95 #define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */ 96 #define SGINT_TCWORD_CMASK 0x30 /* Command mask */ 97 #define SGINT_TCWORD_CLAT 0x00 /* Latch command */ 98 #define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */ 99 #define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */ 100 #define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */ 101 #define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */ 102 #define SGINT_TCWORD_CNT1 0x40 /* Select counter one */ 103 #define SGINT_TCWORD_CNT2 0x80 /* Select counter two */ 104 #define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */ 105 }; 106 107 /* 108 * The timer is the good old 8254. Unlike in PCs it's clocked at exactly 1MHz 109 */ 110 #define SGINT_TIMER_CLOCK 1000000 111 112 /* 113 * This is the constant we're using for calibrating the counter. 114 */ 115 #define SGINT_TCSAMP_COUNTER ((SGINT_TIMER_CLOCK / HZ) + 255) 116 117 /* We need software copies of these because they are write only. */ 118 extern u8 sgi_ioc_reset, sgi_ioc_write; 119 120 struct sgioc_regs { 121 struct pi1_regs pport; 122 u32 _unused0[2]; 123 struct sgioc_uart_regs uart; 124 struct sgioc_keyb_regs kbdmouse; 125 u8 _gcsel[3]; 126 volatile u8 gcsel; 127 u8 _genctrl[3]; 128 volatile u8 genctrl; 129 u8 _panel[3]; 130 volatile u8 panel; 131 #define SGIOC_PANEL_POWERON 0x01 132 #define SGIOC_PANEL_POWERINTR 0x02 133 #define SGIOC_PANEL_VOLDNINTR 0x10 134 #define SGIOC_PANEL_VOLDNHOLD 0x20 135 #define SGIOC_PANEL_VOLUPINTR 0x40 136 #define SGIOC_PANEL_VOLUPHOLD 0x80 137 u32 _unused1; 138 u8 _sysid[3]; 139 volatile u8 sysid; 140 #define SGIOC_SYSID_FULLHOUSE 0x01 141 #define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1) 142 #define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5) 143 u32 _unused2; 144 u8 _read[3]; 145 volatile u8 read; 146 u32 _unused3; 147 u8 _dmasel[3]; 148 volatile u8 dmasel; 149 #define SGIOC_DMASEL_SCLK10MHZ 0x00 /* use 10MHZ serial clock */ 150 #define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */ 151 #define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */ 152 #define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */ 153 #define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */ 154 #define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */ 155 u32 _unused4; 156 u8 _reset[3]; 157 volatile u8 reset; 158 #define SGIOC_RESET_PPORT 0x01 /* 0=parport reset, 1=nornal */ 159 #define SGIOC_RESET_KBDMOUSE 0x02 /* 0=kbdmouse reset, 1=normal */ 160 #define SGIOC_RESET_EISA 0x04 /* 0=eisa reset, 1=normal */ 161 #define SGIOC_RESET_ISDN 0x08 /* 0=isdn reset, 1=normal */ 162 #define SGIOC_RESET_LC0OFF 0x10 /* guiness: turn led off (red, else green) */ 163 #define SGIOC_RESET_LC1OFF 0x20 /* guiness: turn led off (green, else amber) */ 164 u32 _unused5; 165 u8 _write[3]; 166 volatile u8 write; 167 #define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */ 168 #define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */ 169 #define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ 170 #define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ 171 #define SGIOC_WRITE_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */ 172 #define SGIOC_WRITE_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */ 173 #define SGIOC_WRITE_MLO 0x40 /* 1=4.75V 0=+5V */ 174 #define SGIOC_WRITE_MHI 0x80 /* 1=5.25V 0=+5V */ 175 u32 _unused6; 176 struct sgint_regs int3; 177 u32 _unused7[16]; 178 volatile u32 extio; /* FullHouse only */ 179 #define EXTIO_S0_IRQ_3 0x8000 /* S0: vid.vsync */ 180 #define EXTIO_S0_IRQ_2 0x4000 /* S0: gfx.fifofull */ 181 #define EXTIO_S0_IRQ_1 0x2000 /* S0: gfx.int */ 182 #define EXTIO_S0_RETRACE 0x1000 183 #define EXTIO_SG_IRQ_3 0x0800 /* SG: vid.vsync */ 184 #define EXTIO_SG_IRQ_2 0x0400 /* SG: gfx.fifofull */ 185 #define EXTIO_SG_IRQ_1 0x0200 /* SG: gfx.int */ 186 #define EXTIO_SG_RETRACE 0x0100 187 #define EXTIO_GIO_33MHZ 0x0080 188 #define EXTIO_EISA_BUSERR 0x0040 189 #define EXTIO_MC_BUSERR 0x0020 190 #define EXTIO_HPC3_BUSERR 0x0010 191 #define EXTIO_S0_STAT_1 0x0008 192 #define EXTIO_S0_STAT_0 0x0004 193 #define EXTIO_SG_STAT_1 0x0002 194 #define EXTIO_SG_STAT_0 0x0001 195 }; 196 197 extern struct sgioc_regs *sgioc; 198 extern struct sgint_regs *sgint; 199 200 #endif 201
