1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s 2 3 ; CHECK: @A 4 ; CHECK-NOT: vunpck 5 ; CHECK: vextractf128 $1 6 define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp { 7 entry: 8 %shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8> 9 ret <8 x float> %shuffle 10 } 11 12 ; CHECK: @B 13 ; CHECK-NOT: vunpck 14 ; CHECK: vextractf128 $1 15 define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp { 16 entry: 17 %shuffle = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 4> 18 ret <4 x double> %shuffle 19 } 20 21 ; CHECK: @t0 22 ; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0 23 ; CHECK-NOT: vmovaps %xmm0, (%rdi) 24 ; CHECK: vextractf128 $1, %ymm0, (%rdi) 25 define void @t0(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp { 26 entry: 27 %0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 1) 28 %1 = bitcast float* %addr to <4 x float>* 29 store <4 x float> %0, <4 x float>* %1, align 16 30 ret void 31 } 32 33 declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone 34 35 ; CHECK: @t2 36 ; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0 37 ; CHECK-NOT: vmovaps %xmm0, (%rdi) 38 ; CHECK: vextractf128 $1, %ymm0, (%rdi) 39 define void @t2(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp { 40 entry: 41 %0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 1) 42 %1 = bitcast double* %addr to <2 x double>* 43 store <2 x double> %0, <2 x double>* %1, align 16 44 ret void 45 } 46 47 declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone 48 49 ; CHECK: @t4 50 ; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0 51 ; CHECK-NOT: vmovaps %xmm0, (%rdi) 52 ; CHECK: vextractf128 $1, %ymm0, (%rdi) 53 define void @t4(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp { 54 entry: 55 %0 = bitcast <4 x i64> %a to <8 x i32> 56 %1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 1) 57 %2 = bitcast <4 x i32> %1 to <2 x i64> 58 store <2 x i64> %2, <2 x i64>* %addr, align 16 59 ret void 60 } 61 62 declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone 63 64 ; CHECK: @t5 65 ; CHECK: vmovaps %xmm0, (%rdi) 66 define void @t5(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp { 67 entry: 68 %0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 0) 69 %1 = bitcast float* %addr to <4 x float>* 70 store <4 x float> %0, <4 x float>* %1, align 16 71 ret void 72 } 73 74 ; CHECK: @t6 75 ; CHECK: vmovaps %xmm0, (%rdi) 76 define void @t6(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp { 77 entry: 78 %0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 0) 79 %1 = bitcast double* %addr to <2 x double>* 80 store <2 x double> %0, <2 x double>* %1, align 16 81 ret void 82 } 83 84 ; CHECK: @t7 85 ; CHECK: vmovaps %xmm0, (%rdi) 86 define void @t7(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp { 87 entry: 88 %0 = bitcast <4 x i64> %a to <8 x i32> 89 %1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0) 90 %2 = bitcast <4 x i32> %1 to <2 x i64> 91 store <2 x i64> %2, <2 x i64>* %addr, align 16 92 ret void 93 } 94 95 ; CHECK: @t8 96 ; CHECK: vmovups %xmm0, (%rdi) 97 define void @t8(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp { 98 entry: 99 %0 = bitcast <4 x i64> %a to <8 x i32> 100 %1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0) 101 %2 = bitcast <4 x i32> %1 to <2 x i64> 102 store <2 x i64> %2, <2 x i64>* %addr, align 1 103 ret void 104 } 105
