1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s 2 3 ; CHECK: vpaddq %ymm 4 define <4 x i64> @vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { 5 %x = add <4 x i64> %i, %j 6 ret <4 x i64> %x 7 } 8 9 ; CHECK: vpaddd %ymm 10 define <8 x i32> @vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone { 11 %x = add <8 x i32> %i, %j 12 ret <8 x i32> %x 13 } 14 15 ; CHECK: vpaddw %ymm 16 define <16 x i16> @vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { 17 %x = add <16 x i16> %i, %j 18 ret <16 x i16> %x 19 } 20 21 ; CHECK: vpaddb %ymm 22 define <32 x i8> @vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone { 23 %x = add <32 x i8> %i, %j 24 ret <32 x i8> %x 25 } 26 27 ; CHECK: vpsubq %ymm 28 define <4 x i64> @vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { 29 %x = sub <4 x i64> %i, %j 30 ret <4 x i64> %x 31 } 32 33 ; CHECK: vpsubd %ymm 34 define <8 x i32> @vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone { 35 %x = sub <8 x i32> %i, %j 36 ret <8 x i32> %x 37 } 38 39 ; CHECK: vpsubw %ymm 40 define <16 x i16> @vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { 41 %x = sub <16 x i16> %i, %j 42 ret <16 x i16> %x 43 } 44 45 ; CHECK: vpsubb %ymm 46 define <32 x i8> @vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone { 47 %x = sub <32 x i8> %i, %j 48 ret <32 x i8> %x 49 } 50 51 ; CHECK: vpmulld %ymm 52 define <8 x i32> @vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone { 53 %x = mul <8 x i32> %i, %j 54 ret <8 x i32> %x 55 } 56 57 ; CHECK: vpmullw %ymm 58 define <16 x i16> @vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { 59 %x = mul <16 x i16> %i, %j 60 ret <16 x i16> %x 61 } 62 63 ; CHECK: vpmuludq %ymm 64 ; CHECK-NEXT: vpsrlq $32, %ymm 65 ; CHECK-NEXT: vpmuludq %ymm 66 ; CHECK-NEXT: vpsllq $32, %ymm 67 ; CHECK-NEXT: vpaddq %ymm 68 ; CHECK-NEXT: vpsrlq $32, %ymm 69 ; CHECK-NEXT: vpmuludq %ymm 70 ; CHECK-NEXT: vpsllq $32, %ymm 71 ; CHECK-NEXT: vpaddq %ymm 72 define <4 x i64> @mul-v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone { 73 %x = mul <4 x i64> %i, %j 74 ret <4 x i64> %x 75 } 76 77
