1 ; RUN: llc -march=x86 < %s -verify-machineinstrs 2 ; RUN: llc -march=x86-64 < %s -verify-machineinstrs 3 4 ; PR6497 5 6 ; Chain and flag folding issues. 7 define i32 @test1() nounwind ssp { 8 entry: 9 %tmp5.i = load volatile i32* undef ; <i32> [#uses=1] 10 %conv.i = zext i32 %tmp5.i to i64 ; <i64> [#uses=1] 11 %tmp12.i = load volatile i32* undef ; <i32> [#uses=1] 12 %conv13.i = zext i32 %tmp12.i to i64 ; <i64> [#uses=1] 13 %shl.i = shl i64 %conv13.i, 32 ; <i64> [#uses=1] 14 %or.i = or i64 %shl.i, %conv.i ; <i64> [#uses=1] 15 %add16.i = add i64 %or.i, 256 ; <i64> [#uses=1] 16 %shr.i = lshr i64 %add16.i, 8 ; <i64> [#uses=1] 17 %conv19.i = trunc i64 %shr.i to i32 ; <i32> [#uses=1] 18 store volatile i32 %conv19.i, i32* undef 19 ret i32 undef 20 } 21 22 ; PR6533 23 define void @test2(i1 %x, i32 %y) nounwind { 24 %land.ext = zext i1 %x to i32 ; <i32> [#uses=1] 25 %and = and i32 %y, 1 ; <i32> [#uses=1] 26 %xor = xor i32 %and, %land.ext ; <i32> [#uses=1] 27 %cmp = icmp eq i32 %xor, 1 ; <i1> [#uses=1] 28 br i1 %cmp, label %if.end, label %if.then 29 30 if.then: ; preds = %land.end 31 ret void 32 33 if.end: ; preds = %land.end 34 ret void 35 } 36 37 ; PR6577 38 %pair = type { i64, double } 39 40 define void @test3() { 41 dependentGraph243.exit: 42 %subject19 = load %pair* undef ; <%1> [#uses=1] 43 %0 = extractvalue %pair %subject19, 1 ; <double> [#uses=2] 44 %1 = select i1 undef, double %0, double undef ; <double> [#uses=1] 45 %2 = select i1 undef, double %1, double %0 ; <double> [#uses=1] 46 %3 = insertvalue %pair undef, double %2, 1 ; <%1> [#uses=1] 47 store %pair %3, %pair* undef 48 ret void 49 } 50 51 ; PR6605 52 define i64 @test4(i8* %P) nounwind ssp { 53 entry: 54 %tmp1 = load i8* %P ; <i8> [#uses=3] 55 %tobool = icmp eq i8 %tmp1, 0 ; <i1> [#uses=1] 56 %tmp58 = sext i1 %tobool to i8 ; <i8> [#uses=1] 57 %mul.i = and i8 %tmp58, %tmp1 ; <i8> [#uses=1] 58 %conv6 = zext i8 %mul.i to i32 ; <i32> [#uses=1] 59 %cmp = icmp ne i8 %tmp1, 1 ; <i1> [#uses=1] 60 %conv11 = zext i1 %cmp to i32 ; <i32> [#uses=1] 61 %call12 = tail call i32 @safe(i32 %conv11) nounwind ; <i32> [#uses=1] 62 %and = and i32 %conv6, %call12 ; <i32> [#uses=1] 63 %tobool13 = icmp eq i32 %and, 0 ; <i1> [#uses=1] 64 br i1 %tobool13, label %if.else, label %return 65 66 if.else: ; preds = %entry 67 br label %return 68 69 return: ; preds = %if.else, %entry 70 ret i64 undef 71 } 72 73 declare i32 @safe(i32) 74 75 ; PR6607 76 define fastcc void @test5(i32 %FUNC) nounwind { 77 foo: 78 %0 = load i8* undef, align 1 ; <i8> [#uses=3] 79 %1 = sext i8 %0 to i32 ; <i32> [#uses=2] 80 %2 = zext i8 %0 to i32 ; <i32> [#uses=1] 81 %tmp1.i5037 = urem i32 %2, 10 ; <i32> [#uses=1] 82 %tmp.i5038 = icmp ugt i32 %tmp1.i5037, 15 ; <i1> [#uses=1] 83 %3 = zext i1 %tmp.i5038 to i8 ; <i8> [#uses=1] 84 %4 = icmp slt i8 %0, %3 ; <i1> [#uses=1] 85 %5 = add nsw i32 %1, 256 ; <i32> [#uses=1] 86 %storemerge.i.i57 = select i1 %4, i32 %5, i32 %1 ; <i32> [#uses=1] 87 %6 = shl i32 %storemerge.i.i57, 16 ; <i32> [#uses=1] 88 %7 = sdiv i32 %6, -256 ; <i32> [#uses=1] 89 %8 = trunc i32 %7 to i8 ; <i8> [#uses=1] 90 store i8 %8, i8* undef, align 1 91 ret void 92 } 93 94 95 ; Crash commoning identical asms. 96 ; PR6803 97 define void @test6(i1 %C) nounwind optsize ssp { 98 entry: 99 br i1 %C, label %do.body55, label %do.body92 100 101 do.body55: ; preds = %if.else36 102 call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0 103 ret void 104 105 do.body92: ; preds = %if.then66 106 call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !1 107 ret void 108 } 109 110 !0 = metadata !{i32 633550} 111 !1 = metadata !{i32 634261} 112 113 114 ; Crash during XOR optimization. 115 ; <rdar://problem/7869290> 116 117 define void @test7() nounwind ssp { 118 entry: 119 br i1 undef, label %bb14, label %bb67 120 121 bb14: 122 %tmp0 = trunc i16 undef to i1 123 %tmp1 = load i8* undef, align 8 124 %tmp2 = shl i8 %tmp1, 4 125 %tmp3 = lshr i8 %tmp2, 7 126 %tmp4 = trunc i8 %tmp3 to i1 127 %tmp5 = icmp ne i1 %tmp0, %tmp4 128 br i1 %tmp5, label %bb14, label %bb67 129 130 bb67: 131 ret void 132 } 133 134 ; Crash when trying to copy AH to AL. 135 ; PR7540 136 define void @copy8bitregs() nounwind { 137 entry: 138 %div.i = sdiv i32 115200, 0 139 %shr8.i = lshr i32 %div.i, 8 140 %conv4.i = trunc i32 %shr8.i to i8 141 call void asm sideeffect "outb $0, ${1:w}", "{ax},N{dx},~{dirflag},~{fpsr},~{flags}"(i8 %conv4.i, i32 1017) nounwind 142 unreachable 143 } 144 145 ; Crash trying to form conditional increment with fp value. 146 ; PR8981 147 define i32 @test9(double %X) ssp align 2 { 148 entry: 149 %0 = fcmp one double %X, 0.000000e+00 150 %cond = select i1 %0, i32 1, i32 2 151 ret i32 %cond 152 } 153 154 155 ; PR8514 - Crash in match address do to "heroics" turning and-of-shift into 156 ; shift of and. 157 %struct.S0 = type { i8, [2 x i8], i8 } 158 159 define void @func_59(i32 %p_63) noreturn nounwind { 160 entry: 161 br label %for.body 162 163 for.body: ; preds = %for.inc44, %entry 164 %p_63.addr.1 = phi i32 [ %p_63, %entry ], [ 0, %for.inc44 ] 165 %l_74.0 = phi i32 [ 0, %entry ], [ %add46, %for.inc44 ] 166 br i1 undef, label %for.inc44, label %bb.nph81 167 168 bb.nph81: ; preds = %for.body 169 %tmp98 = add i32 %p_63.addr.1, 0 170 br label %for.body22 171 172 for.body22: ; preds = %for.body22, %bb.nph81 173 %l_75.077 = phi i64 [ %ins, %for.body22 ], [ undef, %bb.nph81 ] 174 %tmp110 = trunc i64 %l_75.077 to i32 175 %tmp111 = and i32 %tmp110, 65535 176 %arrayidx32.0 = getelementptr [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 %tmp111, i32 0 177 store i8 1, i8* %arrayidx32.0, align 4 178 %tmp106 = shl i32 %tmp110, 2 179 %tmp107 = and i32 %tmp106, 262140 180 %scevgep99.sum114 = or i32 %tmp107, 1 181 %arrayidx32.1.1 = getelementptr [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 0, i32 1, i32 %scevgep99.sum114 182 store i8 0, i8* %arrayidx32.1.1, align 1 183 %ins = or i64 undef, undef 184 br label %for.body22 185 186 for.inc44: ; preds = %for.body 187 %add46 = add i32 %l_74.0, 1 188 br label %for.body 189 } 190 191 ; PR9028 192 define void @func_60(i64 %A) nounwind { 193 entry: 194 %0 = zext i64 %A to i160 195 %1 = shl i160 %0, 64 196 %2 = zext i160 %1 to i576 197 %3 = zext i96 undef to i576 198 %4 = or i576 %3, %2 199 store i576 %4, i576* undef, align 8 200 ret void 201 } 202 203 ; <rdar://problem/9187792> 204 define fastcc void @func_61() nounwind sspreq { 205 entry: 206 %t1 = tail call i64 @llvm.objectsize.i64(i8* undef, i1 false) 207 %t2 = icmp eq i64 %t1, -1 208 br i1 %t2, label %bb2, label %bb1 209 210 bb1: 211 ret void 212 213 bb2: 214 ret void 215 } 216 217 declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone 218 219 ; PR10277 220 ; This test has dead code elimination caused by remat during spilling. 221 ; DCE causes a live interval to break into connected components. 222 ; One of the components is spilled. 223 224 %t2 = type { i8 } 225 %t9 = type { %t10 } 226 %t10 = type { %t11 } 227 %t11 = type { %t12 } 228 %t12 = type { %t13*, %t13*, %t13* } 229 %t13 = type { %t14*, %t15, %t15 } 230 %t14 = type opaque 231 %t15 = type { i8, i32, i32 } 232 %t16 = type { %t17, i8* } 233 %t17 = type { %t18 } 234 %t18 = type { %t19 } 235 %t19 = type { %t20*, %t20*, %t20* } 236 %t20 = type { i32, i32 } 237 %t21 = type { %t13* } 238 239 define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 { 240 bb: 241 %tmp = load %t9** undef, align 4, !tbaa !0 242 %tmp2 = getelementptr inbounds %t9* %tmp, i32 0, i32 0 243 %tmp3 = getelementptr inbounds %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1 244 br label %bb4 245 246 bb4: ; preds = %bb37, %bb 247 %tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ] 248 %tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ] 249 br i1 undef, label %bb34, label %bb7 250 251 bb7: ; preds = %bb4 252 %tmp8 = load i32* undef, align 4 253 %tmp9 = and i96 %tmp6, 4294967040 254 %tmp10 = zext i32 %tmp8 to i96 255 %tmp11 = shl nuw nsw i96 %tmp10, 32 256 %tmp12 = or i96 %tmp9, %tmp11 257 %tmp13 = or i96 %tmp12, 1 258 %tmp14 = load i32* undef, align 4 259 %tmp15 = and i96 %tmp5, 4294967040 260 %tmp16 = zext i32 %tmp14 to i96 261 %tmp17 = shl nuw nsw i96 %tmp16, 32 262 %tmp18 = or i96 %tmp15, %tmp17 263 %tmp19 = or i96 %tmp18, 1 264 %tmp20 = load i8* undef, align 1 265 %tmp21 = and i8 %tmp20, 1 266 %tmp22 = icmp ne i8 %tmp21, 0 267 %tmp23 = select i1 %tmp22, i96 %tmp19, i96 %tmp13 268 %tmp24 = select i1 %tmp22, i96 %tmp13, i96 %tmp19 269 store i96 %tmp24, i96* undef, align 4 270 %tmp25 = load %t13** %tmp3, align 4 271 %tmp26 = icmp eq %t13* %tmp25, undef 272 br i1 %tmp26, label %bb28, label %bb27 273 274 bb27: ; preds = %bb7 275 br label %bb29 276 277 bb28: ; preds = %bb7 278 call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) 279 br label %bb29 280 281 bb29: ; preds = %bb28, %bb27 282 store i96 %tmp23, i96* undef, align 4 283 %tmp30 = load %t13** %tmp3, align 4 284 br i1 false, label %bb33, label %bb31 285 286 bb31: ; preds = %bb29 287 %tmp32 = getelementptr inbounds %t13* %tmp30, i32 1 288 store %t13* %tmp32, %t13** %tmp3, align 4 289 br label %bb37 290 291 bb33: ; preds = %bb29 292 unreachable 293 294 bb34: ; preds = %bb4 295 br i1 undef, label %bb36, label %bb35 296 297 bb35: ; preds = %bb34 298 store %t13* null, %t13** %tmp3, align 4 299 br label %bb37 300 301 bb36: ; preds = %bb34 302 call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) 303 br label %bb37 304 305 bb37: ; preds = %bb36, %bb35, %bb31 306 %tmp38 = phi i96 [ %tmp23, %bb31 ], [ %tmp5, %bb35 ], [ %tmp5, %bb36 ] 307 %tmp39 = phi i96 [ %tmp24, %bb31 ], [ %tmp6, %bb35 ], [ %tmp6, %bb36 ] 308 %tmp40 = add i32 undef, 1 309 br label %bb4 310 } 311 312 declare %t14* @_ZN4llvm9MCContext16CreateTempSymbolEv(%t2*) 313 314 declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval align 4, %t13*) 315 316 declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind 317 318 declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind 319 320 ; PR10463 321 ; Spilling a virtual register with <undef> uses. 322 define void @autogen_239_1000() { 323 BB: 324 %Shuff = shufflevector <8 x double> undef, <8 x double> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 undef> 325 br label %CF 326 327 CF: 328 %B16 = frem <8 x double> zeroinitializer, %Shuff 329 %E19 = extractelement <8 x double> %Shuff, i32 5 330 br i1 undef, label %CF, label %CF75 331 332 CF75: 333 br i1 undef, label %CF75, label %CF76 334 335 CF76: 336 store double %E19, double* undef 337 br i1 undef, label %CF76, label %CF77 338 339 CF77: 340 %B55 = fmul <8 x double> %B16, undef 341 br label %CF77 342 } 343 344 ; PR10527 345 define void @pr10527() nounwind uwtable { 346 entry: 347 br label %"4" 348 349 "3": 350 %0 = load <2 x i32>* null, align 8 351 %1 = xor <2 x i32> zeroinitializer, %0 352 %2 = and <2 x i32> %1, %6 353 %3 = or <2 x i32> undef, %2 354 %4 = and <2 x i32> %3, undef 355 store <2 x i32> %4, <2 x i32>* undef 356 %5 = load <2 x i32>* undef, align 1 357 br label %"4" 358 359 "4": 360 %6 = phi <2 x i32> [ %5, %"3" ], [ zeroinitializer, %entry ] 361 %7 = icmp ult i32 undef, undef 362 br i1 %7, label %"3", label %"5" 363 364 "5": 365 ret void 366 } 367 368 ; PR11078 369 ; 370 ; A virtual register used by the "foo" inline asm memory operand gets 371 ; constrained to GR32_ABCD during coalescing. This makes the inline asm 372 ; impossible to allocate without splitting the live range and reinflating the 373 ; register class around the inline asm. 374 ; 375 ; The constraint originally comes from the TEST8ri optimization of (icmp (and %t0, 1), 0). 376 377 @__force_order = external hidden global i32, align 4 378 define void @pr11078(i32* %pgd) nounwind { 379 entry: 380 %t0 = load i32* %pgd, align 4 381 %and2 = and i32 %t0, 1 382 %tobool = icmp eq i32 %and2, 0 383 br i1 %tobool, label %if.then, label %if.end 384 385 if.then: 386 %t1 = tail call i32 asm sideeffect "bar", "=r,=*m,~{dirflag},~{fpsr},~{flags}"(i32* @__force_order) nounwind 387 br label %if.end 388 389 if.end: 390 %t6 = inttoptr i32 %t0 to i64* 391 %t11 = tail call i64 asm sideeffect "foo", "=*m,=A,{bx},{cx},1,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %t6, i32 0, i32 0, i64 0) nounwind 392 ret void 393 } 394 395 ; Avoid emitting wrong kill flags from InstrEmitter. 396 ; InstrEmitter::EmitSubregNode() may steal virtual registers from already 397 ; emitted blocks when isCoalescableExtInstr points out the opportunity. 398 ; Make sure kill flags are cleared on the newly global virtual register. 399 define i64 @ov_read(i8* %vf, i8* nocapture %buffer, i32 %length, i32 %bigendianp, i32 %word, i32 %sgned, i32* %bitstream) nounwind uwtable ssp { 400 entry: 401 br i1 undef, label %return, label %while.body.preheader 402 403 while.body.preheader: ; preds = %entry 404 br i1 undef, label %if.then3, label %if.end7 405 406 if.then3: ; preds = %while.body.preheader 407 %0 = load i32* undef, align 4 408 br i1 undef, label %land.lhs.true.i255, label %if.end7 409 410 land.lhs.true.i255: ; preds = %if.then3 411 br i1 undef, label %if.then.i256, label %if.end7 412 413 if.then.i256: ; preds = %land.lhs.true.i255 414 %sub.i = sub i32 0, %0 415 %conv = sext i32 %sub.i to i64 416 br i1 undef, label %if.end7, label %while.end 417 418 if.end7: ; preds = %if.then.i256, %land.lhs.true.i255, %if.then3, %while.body.preheader 419 unreachable 420 421 while.end: ; preds = %if.then.i256 422 %cmp18 = icmp sgt i32 %sub.i, 0 423 %.conv = select i1 %cmp18, i64 -131, i64 %conv 424 ret i64 %.conv 425 426 return: ; preds = %entry 427 ret i64 -131 428 } 429 430 ; The tail call to a varargs function sets %AL. 431 ; uitofp expands to an FCMOV instruction which splits the basic block. 432 ; Make sure the live range of %AL isn't split. 433 @.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32 434 define void @pr13188(i64* nocapture %this) uwtable ssp address_safety align 2 { 435 entry: 436 %x7 = load i64* %this, align 8 437 %sub = add i64 %x7, -1 438 %conv = uitofp i64 %sub to float 439 %div = fmul float %conv, 5.000000e-01 440 %conv2 = fpext float %div to double 441 tail call void (...)* @_Z6PrintFz(i8* getelementptr inbounds ({ [1 x i8], [63 x i8] }* @.str, i64 0, i32 0, i64 0), double %conv2) 442 ret void 443 } 444 declare void @_Z6PrintFz(...) 445
