1 ; RUN: llc < %s -march=x86 -mattr=+mmx | grep psllq | grep 32 2 ; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psllq | grep 32 3 ; RUN: llc < %s -march=x86 -mattr=+mmx | grep psrad 4 ; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psrlw 5 6 define i64 @t1(<1 x i64> %mm1) nounwind { 7 entry: 8 %tmp = bitcast <1 x i64> %mm1 to x86_mmx 9 %tmp6 = tail call x86_mmx @llvm.x86.mmx.pslli.q( x86_mmx %tmp, i32 32 ) ; <x86_mmx> [#uses=1] 10 %retval1112 = bitcast x86_mmx %tmp6 to i64 11 ret i64 %retval1112 12 } 13 14 declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) nounwind readnone 15 16 define i64 @t2(x86_mmx %mm1, x86_mmx %mm2) nounwind { 17 entry: 18 %tmp7 = tail call x86_mmx @llvm.x86.mmx.psra.d( x86_mmx %mm1, x86_mmx %mm2 ) nounwind readnone ; <x86_mmx> [#uses=1] 19 %retval1112 = bitcast x86_mmx %tmp7 to i64 20 ret i64 %retval1112 21 } 22 23 declare x86_mmx @llvm.x86.mmx.psra.d(x86_mmx, x86_mmx) nounwind readnone 24 25 define i64 @t3(x86_mmx %mm1, i32 %bits) nounwind { 26 entry: 27 %tmp8 = tail call x86_mmx @llvm.x86.mmx.psrli.w( x86_mmx %mm1, i32 %bits ) nounwind readnone ; <x86_mmx> [#uses=1] 28 %retval1314 = bitcast x86_mmx %tmp8 to i64 29 ret i64 %retval1314 30 } 31 32 declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32) nounwind readnone 33
