1 ; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -mcpu=nehalem -post-RA-scheduler=true | FileCheck %s 2 3 ; Currently, floating-point selects are lowered to CFG triangles. 4 ; This means that one side of the select is always unconditionally 5 ; evaluated, however with MachineSink we can sink the other side so 6 ; that it's conditionally evaluated. 7 8 ; CHECK: foo: 9 ; CHECK-NEXT: testb $1, %dil 10 ; CHECK-NEXT: jne 11 ; CHECK-NEXT: divsd 12 ; CHECK-NEXT: movaps 13 ; CHECK-NEXT: ret 14 ; CHECK: divsd 15 16 define double @foo(double %x, double %y, i1 %c) nounwind { 17 %a = fdiv double %x, 3.2 18 %b = fdiv double %y, 3.3 19 %z = select i1 %c, double %a, double %b 20 ret double %z 21 } 22 23 ; Make sure the critical edge is broken so the divsd is sunken below 24 ; the conditional branch. 25 ; rdar://8454886 26 27 ; CHECK: split: 28 ; CHECK-NEXT: testb $1, %dil 29 ; CHECK-NEXT: jne 30 ; CHECK-NEXT: movaps 31 ; CHECK-NEXT: ret 32 ; CHECK: divsd 33 ; CHECK-NEXT: ret 34 define double @split(double %x, double %y, i1 %c) nounwind { 35 %a = fdiv double %x, 3.2 36 %z = select i1 %c, double %a, double %y 37 ret double %z 38 } 39 40 41 ; Hoist floating-point constant-pool loads out of loops. 42 43 ; CHECK: bar: 44 ; CHECK: movsd 45 ; CHECK: align 46 define void @bar(double* nocapture %p, i64 %n) nounwind { 47 entry: 48 %0 = icmp sgt i64 %n, 0 49 br i1 %0, label %bb, label %return 50 51 bb: 52 %i.03 = phi i64 [ 0, %entry ], [ %3, %bb ] 53 %scevgep = getelementptr double* %p, i64 %i.03 54 %1 = load double* %scevgep, align 8 55 %2 = fdiv double 3.200000e+00, %1 56 store double %2, double* %scevgep, align 8 57 %3 = add nsw i64 %i.03, 1 58 %exitcond = icmp eq i64 %3, %n 59 br i1 %exitcond, label %return, label %bb 60 61 return: 62 ret void 63 } 64 65 ; Sink instructions with dead EFLAGS defs. 66 67 ; FIXME: Unfail the zzz test if we can correctly mark pregs with the kill flag. 68 ; 69 ; See <rdar://problem/8030636>. This test isn't valid after we made machine 70 ; sinking more conservative about sinking instructions that define a preg into a 71 ; block when we don't know if the preg is killed within the current block. 72 73 74 ; FIXMEHECK: zzz: 75 ; FIXMEHECK: je 76 ; FIXMEHECK-NEXT: orb 77 78 ; define zeroext i8 @zzz(i8 zeroext %a, i8 zeroext %b) nounwind readnone { 79 ; entry: 80 ; %tmp = zext i8 %a to i32 ; <i32> [#uses=1] 81 ; %tmp2 = icmp eq i8 %a, 0 ; <i1> [#uses=1] 82 ; %tmp3 = or i8 %b, -128 ; <i8> [#uses=1] 83 ; %tmp4 = and i8 %b, 127 ; <i8> [#uses=1] 84 ; %b_addr.0 = select i1 %tmp2, i8 %tmp4, i8 %tmp3 ; <i8> [#uses=1] 85 ; ret i8 %b_addr.0 86 ; } 87 88 ; Codegen should hoist and CSE these constants. 89 90 ; CHECK: vv: 91 ; CHECK: LCPI3_0(%rip), %xmm0 92 ; CHECK: LCPI3_1(%rip), %xmm1 93 ; CHECK: LCPI3_2(%rip), %xmm2 94 ; CHECK: align 95 ; CHECK-NOT: LCPI 96 ; CHECK: ret 97 98 @_minusZero.6007 = internal constant <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00> ; <<4 x float>*> [#uses=0] 99 @twoTo23.6008 = internal constant <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06> ; <<4 x float>*> [#uses=0] 100 101 define void @vv(float* %y, float* %x, i32* %n) nounwind ssp { 102 entry: 103 br label %bb60 104 105 bb: ; preds = %bb60 106 %i.0 = phi i32 [ 0, %bb60 ] ; <i32> [#uses=2] 107 %0 = bitcast float* %x_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1] 108 %1 = load <4 x float>* %0, align 16 ; <<4 x float>> [#uses=4] 109 %tmp20 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1] 110 %tmp22 = and <4 x i32> %tmp20, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1] 111 %tmp23 = bitcast <4 x i32> %tmp22 to <4 x float> ; <<4 x float>> [#uses=1] 112 %tmp25 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1] 113 %tmp27 = and <4 x i32> %tmp25, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=2] 114 %tmp30 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %tmp23, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) ; <<4 x float>> [#uses=1] 115 %tmp34 = bitcast <4 x float> %tmp30 to <4 x i32> ; <<4 x i32>> [#uses=1] 116 %tmp36 = xor <4 x i32> %tmp34, <i32 -1, i32 -1, i32 -1, i32 -1> ; <<4 x i32>> [#uses=1] 117 %tmp37 = and <4 x i32> %tmp36, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> ; <<4 x i32>> [#uses=1] 118 %tmp42 = or <4 x i32> %tmp37, %tmp27 ; <<4 x i32>> [#uses=1] 119 %tmp43 = bitcast <4 x i32> %tmp42 to <4 x float> ; <<4 x float>> [#uses=2] 120 %tmp45 = fadd <4 x float> %1, %tmp43 ; <<4 x float>> [#uses=1] 121 %tmp47 = fsub <4 x float> %tmp45, %tmp43 ; <<4 x float>> [#uses=2] 122 %tmp49 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %1, <4 x float> %tmp47, i8 1) ; <<4 x float>> [#uses=1] 123 %2 = bitcast <4 x float> %tmp49 to <4 x i32> ; <<4 x i32>> [#uses=1] 124 %3 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %2) nounwind readnone ; <<4 x float>> [#uses=1] 125 %tmp53 = fadd <4 x float> %tmp47, %3 ; <<4 x float>> [#uses=1] 126 %tmp55 = bitcast <4 x float> %tmp53 to <4 x i32> ; <<4 x i32>> [#uses=1] 127 %tmp57 = or <4 x i32> %tmp55, %tmp27 ; <<4 x i32>> [#uses=1] 128 %tmp58 = bitcast <4 x i32> %tmp57 to <4 x float> ; <<4 x float>> [#uses=1] 129 %4 = bitcast float* %y_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1] 130 store <4 x float> %tmp58, <4 x float>* %4, align 16 131 %5 = getelementptr float* %x_addr.0, i64 4 ; <float*> [#uses=1] 132 %6 = getelementptr float* %y_addr.0, i64 4 ; <float*> [#uses=1] 133 %7 = add i32 %i.0, 4 ; <i32> [#uses=1] 134 %8 = load i32* %n, align 4 ; <i32> [#uses=1] 135 %9 = icmp sgt i32 %8, %7 ; <i1> [#uses=1] 136 br i1 %9, label %bb60, label %return 137 138 bb60: ; preds = %bb, %entry 139 %x_addr.0 = phi float* [ %x, %entry ], [ %5, %bb ] ; <float*> [#uses=2] 140 %y_addr.0 = phi float* [ %y, %entry ], [ %6, %bb ] ; <float*> [#uses=2] 141 br label %bb 142 143 return: ; preds = %bb60 144 ret void 145 } 146 147 declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone 148 149 declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone 150 151 ; CodeGen should use the correct register class when extracting 152 ; a load from a zero-extending load for hoisting. 153 154 ; CHECK: default_get_pch_validity: 155 ; CHECK: movl cl_options_count(%rip), %ecx 156 157 @cl_options_count = external constant i32 ; <i32*> [#uses=2] 158 159 define void @default_get_pch_validity() nounwind { 160 entry: 161 %tmp4 = load i32* @cl_options_count, align 4 ; <i32> [#uses=1] 162 %tmp5 = icmp eq i32 %tmp4, 0 ; <i1> [#uses=1] 163 br i1 %tmp5, label %bb6, label %bb2 164 165 bb2: ; preds = %bb2, %entry 166 %i.019 = phi i64 [ 0, %entry ], [ %tmp25, %bb2 ] ; <i64> [#uses=1] 167 %tmp25 = add i64 %i.019, 1 ; <i64> [#uses=2] 168 %tmp11 = load i32* @cl_options_count, align 4 ; <i32> [#uses=1] 169 %tmp12 = zext i32 %tmp11 to i64 ; <i64> [#uses=1] 170 %tmp13 = icmp ugt i64 %tmp12, %tmp25 ; <i1> [#uses=1] 171 br i1 %tmp13, label %bb2, label %bb6 172 173 bb6: ; preds = %bb2, %entry 174 ret void 175 } 176
