1 /* 2 * MIPS emulation helpers for qemu. 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include <stdarg.h> 20 #include <stdlib.h> 21 #include <stdio.h> 22 #include <string.h> 23 #include <inttypes.h> 24 #include <signal.h> 25 26 #include "cpu.h" 27 #include "exec-all.h" 28 29 enum { 30 TLBRET_DIRTY = -4, 31 TLBRET_INVALID = -3, 32 TLBRET_NOMATCH = -2, 33 TLBRET_BADADDR = -1, 34 TLBRET_MATCH = 0 35 }; 36 37 /* no MMU emulation */ 38 int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, 39 target_ulong address, int rw, int access_type) 40 { 41 *physical = address; 42 *prot = PAGE_READ | PAGE_WRITE; 43 return TLBRET_MATCH; 44 } 45 46 /* fixed mapping MMU emulation */ 47 int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, 48 target_ulong address, int rw, int access_type) 49 { 50 if (address <= (int32_t)0x7FFFFFFFUL) { 51 if (!(env->CP0_Status & (1 << CP0St_ERL))) 52 *physical = address + 0x40000000UL; 53 else 54 *physical = address; 55 } else if (address <= (int32_t)0xBFFFFFFFUL) 56 *physical = address & 0x1FFFFFFF; 57 else 58 *physical = address; 59 60 *prot = PAGE_READ | PAGE_WRITE; 61 return TLBRET_MATCH; 62 } 63 64 /* MIPS32/MIPS64 R4000-style MMU emulation */ 65 int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, 66 target_ulong address, int rw, int access_type) 67 { 68 uint8_t ASID = env->CP0_EntryHi & 0xFF; 69 r4k_tlb_t *tlb; 70 target_ulong mask; 71 target_ulong tag; 72 target_ulong VPN; 73 int n; 74 int i; 75 76 for (i = 0; i < env->tlb->nb_tlb; i++) { 77 tlb = &env->tlb->mmu.r4k.tlb[i]; 78 /* 1k pages are not supported. */ 79 mask = ~(TARGET_PAGE_MASK << 1); 80 tag = address & ~mask; 81 VPN = tlb->VPN & ~mask; 82 83 #if defined(TARGET_MIPS64) 84 tag &= env->SEGMask; 85 #endif 86 87 /* Check ASID, virtual page number & size */ 88 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { 89 /* TLB match */ 90 n = !!(address & mask & ~(mask >> 1)); 91 /* Check access rights */ 92 if (!(n ? tlb->V1 : tlb->V0)) 93 return TLBRET_INVALID; 94 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { 95 *physical = tlb->PFN[n] | (address & (mask >> 1)); 96 *prot = PAGE_READ; 97 if (n ? tlb->D1 : tlb->D0) 98 *prot |= PAGE_WRITE; 99 return TLBRET_MATCH; 100 } 101 return TLBRET_DIRTY; 102 } 103 } 104 return TLBRET_NOMATCH; 105 } 106 107 #if !defined(CONFIG_USER_ONLY) 108 static int get_physical_address (CPUState *env, target_phys_addr_t *physical, 109 int *prot, target_ulong address, 110 int rw, int access_type) 111 { 112 /* User mode can only access useg/xuseg */ 113 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; 114 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; 115 int kernel_mode = !user_mode && !supervisor_mode; 116 #if defined(TARGET_MIPS64) 117 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; 118 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; 119 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; 120 #endif 121 int ret = TLBRET_MATCH; 122 123 #if 0 124 qemu_log("user mode %d h %08x\n", user_mode, env->hflags); 125 #endif 126 127 if (address <= (int32_t)0x7FFFFFFFUL) { 128 /* useg */ 129 if (unlikely(env->CP0_Status & (1 << CP0St_ERL))) { 130 *physical = address & 0xFFFFFFFF; 131 *prot = PAGE_READ | PAGE_WRITE; 132 } else { 133 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); 134 } 135 #if defined(TARGET_MIPS64) 136 } else if (address < 0x4000000000000000ULL) { 137 /* xuseg */ 138 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { 139 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); 140 } else { 141 ret = TLBRET_BADADDR; 142 } 143 } else if (address < 0x8000000000000000ULL) { 144 /* xsseg */ 145 if ((supervisor_mode || kernel_mode) && 146 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { 147 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); 148 } else { 149 ret = TLBRET_BADADDR; 150 } 151 } else if (address < 0xC000000000000000ULL) { 152 /* xkphys */ 153 if (kernel_mode && KX && 154 (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { 155 *physical = address & env->PAMask; 156 *prot = PAGE_READ | PAGE_WRITE; 157 } else { 158 ret = TLBRET_BADADDR; 159 } 160 } else if (address < 0xFFFFFFFF80000000ULL) { 161 /* xkseg */ 162 if (kernel_mode && KX && 163 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { 164 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); 165 } else { 166 ret = TLBRET_BADADDR; 167 } 168 #endif 169 } else if (address < (int32_t)0xA0000000UL) { 170 /* kseg0 */ 171 if (kernel_mode) { 172 *physical = address - (int32_t)0x80000000UL; 173 *prot = PAGE_READ | PAGE_WRITE; 174 } else { 175 ret = TLBRET_BADADDR; 176 } 177 } else if (address < (int32_t)0xC0000000UL) { 178 /* kseg1 */ 179 if (kernel_mode) { 180 *physical = address - (int32_t)0xA0000000UL; 181 *prot = PAGE_READ | PAGE_WRITE; 182 } else { 183 ret = TLBRET_BADADDR; 184 } 185 } else if (address < (int32_t)0xE0000000UL) { 186 /* sseg (kseg2) */ 187 if (supervisor_mode || kernel_mode) { 188 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); 189 } else { 190 ret = TLBRET_BADADDR; 191 } 192 } else { 193 /* kseg3 */ 194 /* XXX: debug segment is not emulated */ 195 if (kernel_mode) { 196 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); 197 } else { 198 ret = TLBRET_BADADDR; 199 } 200 } 201 #if 0 202 qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n", 203 address, rw, access_type, *physical, *prot, ret); 204 #endif 205 206 return ret; 207 } 208 #endif 209 210 static void raise_mmu_exception(CPUState *env, target_ulong address, 211 int rw, int tlb_error) 212 { 213 int exception = 0, error_code = 0; 214 215 switch (tlb_error) { 216 default: 217 case TLBRET_BADADDR: 218 /* Reference to kernel address from user mode or supervisor mode */ 219 /* Reference to supervisor address from user mode */ 220 if (rw) 221 exception = EXCP_AdES; 222 else 223 exception = EXCP_AdEL; 224 break; 225 case TLBRET_NOMATCH: 226 /* No TLB match for a mapped address */ 227 if (rw) 228 exception = EXCP_TLBS; 229 else 230 exception = EXCP_TLBL; 231 error_code = 1; 232 break; 233 case TLBRET_INVALID: 234 /* TLB match with no valid bit */ 235 if (rw) 236 exception = EXCP_TLBS; 237 else 238 exception = EXCP_TLBL; 239 break; 240 case TLBRET_DIRTY: 241 /* TLB match but 'D' bit is cleared */ 242 exception = EXCP_LTLBL; 243 break; 244 245 } 246 /* Raise exception */ 247 env->CP0_BadVAddr = address; 248 env->CP0_Context = (env->CP0_Context & ~0x007fffff) | 249 ((address >> 9) & 0x007ffff0); 250 env->CP0_EntryHi = 251 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); 252 #if defined(TARGET_MIPS64) 253 env->CP0_EntryHi &= env->SEGMask; 254 env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | 255 ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | 256 ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); 257 #endif 258 env->exception_index = exception; 259 env->error_code = error_code; 260 } 261 262 /* 263 * Get the pgd_current from TLB exception handler 264 * The exception handler is generated by function build_r4000_tlb_refill_handler. 265 * 0x80000000:0x3c1b8033: lui k1,0x8033 266 * 0x80000004:0x401a4000: mfc0 k0,c0_badvaddr 267 * 0x80000008:0x8f7bb000: lw k1,-20480(k1) 268 * 269 */ 270 static inline target_ulong cpu_mips_get_pgd(CPUState *env) 271 { 272 static target_ulong pgd_current_p = 0; 273 static target_ulong probed = 0; 274 275 if (likely(pgd_current_p)) { 276 /* Get pgd_current */ 277 return ldl_phys(pgd_current_p); 278 } 279 else if (unlikely(!probed)) { 280 uint32_t ins1, ins2; 281 uint32_t address; 282 uint32_t ebase; 283 284 probed = 1; 285 286 ebase = env->CP0_EBase - 0x80000000; 287 288 /* Get pgd_current pointer from TLB refill exception handler */ 289 ins1 = ldl_phys(ebase); /* lui k1,%hi(pgd_current_p) */ 290 ins2 = ldl_phys(ebase + 8); /* lw k1,%lo(pgd_current_p)(k1) */ 291 292 address = ((ins1 & 0xffff)<<16); 293 address += (((int32_t)(ins2 & 0xffff))<<16)>>16; 294 /* assumes pgd_current_p != 0 */ 295 if (address > 0x80000000 && address < 0xa0000000) { 296 pgd_current_p = address -= 0x80000000; 297 return ldl_phys(pgd_current_p); 298 } 299 } 300 return 0; 301 } 302 303 static inline int cpu_mips_tlb_refill(CPUState *env, target_ulong address, int rw , 304 int mmu_idx, int is_softmmu) 305 { 306 int32_t saved_hflags; 307 target_ulong saved_badvaddr,saved_entryhi,saved_context; 308 309 target_ulong pgd_addr,pt_addr,index; 310 target_ulong fault_addr,ptw_phys; 311 target_ulong elo_even,elo_odd; 312 uint32_t page_valid; 313 int ret; 314 315 saved_badvaddr = env->CP0_BadVAddr; 316 saved_context = env->CP0_Context; 317 saved_entryhi = env->CP0_EntryHi; 318 saved_hflags = env->hflags; 319 320 env->CP0_BadVAddr = address; 321 env->CP0_Context = (env->CP0_Context & ~0x007fffff) | 322 ((address >> 9) & 0x007ffff0); 323 env->CP0_EntryHi = 324 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); 325 326 env->hflags = MIPS_HFLAG_KM; 327 328 fault_addr = env->CP0_BadVAddr; 329 page_valid = 0; 330 331 pgd_addr = cpu_mips_get_pgd(env); 332 if (unlikely(!pgd_addr)) 333 { 334 /*not valid pgd_addr,just return.*/ 335 //return TLBRET_NOMATCH; 336 ret = TLBRET_NOMATCH; 337 goto out; 338 } 339 340 ptw_phys = pgd_addr - (int32_t)0x80000000UL; 341 index = (fault_addr>>22)<<2; 342 ptw_phys += index; 343 344 pt_addr = ldl_phys(ptw_phys); 345 346 ptw_phys = pt_addr - (int32_t)0x80000000UL; 347 index = (env->CP0_Context>>1)&0xff8; 348 ptw_phys += index; 349 350 /*get the page table entry*/ 351 elo_even = ldl_phys(ptw_phys); 352 elo_odd = ldl_phys(ptw_phys+4); 353 elo_even = elo_even >> 6; 354 elo_odd = elo_odd >> 6; 355 env->CP0_EntryLo0 = elo_even; 356 env->CP0_EntryLo1 = elo_odd; 357 /*Done. refill the TLB */ 358 r4k_helper_ptw_tlbrefill(env); 359 360 /* Since we know the value of TLB entry, we can 361 * return the TLB lookup value here. 362 */ 363 364 env->hflags = saved_hflags; 365 366 target_ulong mask = env->CP0_PageMask | ~(TARGET_PAGE_MASK << 1); 367 int n = !!(address & mask & ~(mask >> 1)); 368 /* Check access rights */ 369 if (!(n ? (elo_odd & 2) != 0 : (elo_even & 2) != 0)) 370 { 371 ret = TLBRET_INVALID; 372 goto out; 373 } 374 375 if (rw == 0 || (n ? (elo_odd & 4) != 0 : (elo_even & 4) != 0)) { 376 target_ulong physical = (n?(elo_odd >> 6) << 12 : (elo_even >> 6) << 12); 377 physical |= (address & (mask >> 1)); 378 int prot = PAGE_READ; 379 if (n ? (elo_odd & 4) != 0 : (elo_even & 4) != 0) 380 prot |= PAGE_WRITE; 381 382 tlb_set_page(env, address & TARGET_PAGE_MASK, 383 physical & TARGET_PAGE_MASK, prot, 384 mmu_idx, is_softmmu); 385 ret = TLBRET_MATCH; 386 goto out; 387 } 388 ret = TLBRET_DIRTY; 389 390 out: 391 env->CP0_BadVAddr = saved_badvaddr; 392 env->CP0_Context = saved_context; 393 env->CP0_EntryHi = saved_entryhi; 394 env->hflags = saved_hflags; 395 return ret; 396 } 397 398 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, 399 int mmu_idx, int is_softmmu) 400 { 401 #if !defined(CONFIG_USER_ONLY) 402 target_phys_addr_t physical; 403 int prot; 404 #endif 405 int exception = 0, error_code = 0; 406 int access_type; 407 int ret = 0; 408 409 #if 0 410 log_cpu_state(env, 0); 411 #endif 412 qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n", 413 __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu); 414 415 rw &= 1; 416 417 /* data access */ 418 /* XXX: put correct access by using cpu_restore_state() 419 correctly */ 420 access_type = ACCESS_INT; 421 #if defined(CONFIG_USER_ONLY) 422 ret = TLBRET_NOMATCH; 423 #else 424 ret = get_physical_address(env, &physical, &prot, 425 address, rw, access_type); 426 qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n", 427 __func__, address, ret, physical, prot); 428 if (ret == TLBRET_MATCH) { 429 ret = tlb_set_page(env, address & TARGET_PAGE_MASK, 430 physical & TARGET_PAGE_MASK, prot, 431 mmu_idx, is_softmmu); 432 } 433 else if (ret == TLBRET_NOMATCH) 434 ret = cpu_mips_tlb_refill(env,address,rw,mmu_idx,is_softmmu); 435 if (ret < 0) 436 #endif 437 { 438 raise_mmu_exception(env, address, rw, ret); 439 ret = 1; 440 } 441 442 return ret; 443 } 444 445 #if !defined(CONFIG_USER_ONLY) 446 target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw) 447 { 448 target_phys_addr_t physical; 449 int prot; 450 int access_type; 451 int ret = 0; 452 453 rw &= 1; 454 455 /* data access */ 456 access_type = ACCESS_INT; 457 ret = get_physical_address(env, &physical, &prot, 458 address, rw, access_type); 459 if (ret != TLBRET_MATCH || ret != TLBRET_DIRTY) { 460 raise_mmu_exception(env, address, rw, ret); 461 return -1LL; 462 } else { 463 return physical; 464 } 465 } 466 #endif 467 468 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) 469 { 470 #if defined(CONFIG_USER_ONLY) 471 return addr; 472 #else 473 target_phys_addr_t phys_addr; 474 int prot, ret; 475 476 ret = get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT); 477 if (ret != TLBRET_MATCH && ret != TLBRET_DIRTY) { 478 target_ulong pgd_addr = cpu_mips_get_pgd(env); 479 if (unlikely(!pgd_addr)) { 480 phys_addr = -1; 481 } 482 else { 483 target_ulong pgd_phys, pgd_index; 484 target_ulong pt_addr, pt_phys, pt_index; 485 target_ulong lo; 486 /* Mimic the steps taken for a TLB refill */ 487 pgd_phys = pgd_addr - (int32_t)0x80000000UL; 488 pgd_index = (addr >> 22) << 2; 489 pt_addr = ldl_phys(pgd_phys + pgd_index); 490 pt_phys = pt_addr - (int32_t)0x80000000UL; 491 pt_index = (((addr >> 9) & 0x007ffff0) >> 1) & 0xff8; 492 /* get the entrylo value */ 493 if (addr & 0x1000) 494 lo = ldl_phys(pt_phys + pt_index + 4); 495 else 496 lo = ldl_phys(pt_phys + pt_index); 497 /* convert software TLB entry to hardware value */ 498 lo >>= 6; 499 if (lo & 0x00000002) 500 /* It is valid */ 501 phys_addr = (lo >> 6) << 12; 502 else 503 phys_addr = -1; 504 } 505 } 506 return phys_addr; 507 #endif 508 } 509 510 static const char * const excp_names[EXCP_LAST + 1] = { 511 [EXCP_RESET] = "reset", 512 [EXCP_SRESET] = "soft reset", 513 [EXCP_DSS] = "debug single step", 514 [EXCP_DINT] = "debug interrupt", 515 [EXCP_NMI] = "non-maskable interrupt", 516 [EXCP_MCHECK] = "machine check", 517 [EXCP_EXT_INTERRUPT] = "interrupt", 518 [EXCP_DFWATCH] = "deferred watchpoint", 519 [EXCP_DIB] = "debug instruction breakpoint", 520 [EXCP_IWATCH] = "instruction fetch watchpoint", 521 [EXCP_AdEL] = "address error load", 522 [EXCP_AdES] = "address error store", 523 [EXCP_TLBF] = "TLB refill", 524 [EXCP_IBE] = "instruction bus error", 525 [EXCP_DBp] = "debug breakpoint", 526 [EXCP_SYSCALL] = "syscall", 527 [EXCP_BREAK] = "break", 528 [EXCP_CpU] = "coprocessor unusable", 529 [EXCP_RI] = "reserved instruction", 530 [EXCP_OVERFLOW] = "arithmetic overflow", 531 [EXCP_TRAP] = "trap", 532 [EXCP_FPE] = "floating point", 533 [EXCP_DDBS] = "debug data break store", 534 [EXCP_DWATCH] = "data watchpoint", 535 [EXCP_LTLBL] = "TLB modify", 536 [EXCP_TLBL] = "TLB load", 537 [EXCP_TLBS] = "TLB store", 538 [EXCP_DBE] = "data bus error", 539 [EXCP_DDBL] = "debug data break load", 540 [EXCP_THREAD] = "thread", 541 [EXCP_MDMX] = "MDMX", 542 [EXCP_C2E] = "precise coprocessor 2", 543 [EXCP_CACHE] = "cache error", 544 }; 545 546 void do_interrupt (CPUState *env) 547 { 548 #if !defined(CONFIG_USER_ONLY) 549 target_ulong offset; 550 int cause = -1; 551 const char *name; 552 553 if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { 554 if (env->exception_index < 0 || env->exception_index > EXCP_LAST) 555 name = "unknown"; 556 else 557 name = excp_names[env->exception_index]; 558 559 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", 560 __func__, env->active_tc.PC, env->CP0_EPC, name); 561 } 562 if (env->exception_index == EXCP_EXT_INTERRUPT && 563 (env->hflags & MIPS_HFLAG_DM)) 564 env->exception_index = EXCP_DINT; 565 offset = 0x180; 566 switch (env->exception_index) { 567 case EXCP_DSS: 568 env->CP0_Debug |= 1 << CP0DB_DSS; 569 /* Debug single step cannot be raised inside a delay slot and 570 resume will always occur on the next instruction 571 (but we assume the pc has always been updated during 572 code translation). */ 573 env->CP0_DEPC = env->active_tc.PC; 574 goto enter_debug_mode; 575 case EXCP_DINT: 576 env->CP0_Debug |= 1 << CP0DB_DINT; 577 goto set_DEPC; 578 case EXCP_DIB: 579 env->CP0_Debug |= 1 << CP0DB_DIB; 580 goto set_DEPC; 581 case EXCP_DBp: 582 env->CP0_Debug |= 1 << CP0DB_DBp; 583 goto set_DEPC; 584 case EXCP_DDBS: 585 env->CP0_Debug |= 1 << CP0DB_DDBS; 586 goto set_DEPC; 587 case EXCP_DDBL: 588 env->CP0_Debug |= 1 << CP0DB_DDBL; 589 set_DEPC: 590 if (env->hflags & MIPS_HFLAG_BMASK) { 591 /* If the exception was raised from a delay slot, 592 come back to the jump. */ 593 env->CP0_DEPC = env->active_tc.PC - 4; 594 env->hflags &= ~MIPS_HFLAG_BMASK; 595 } else { 596 env->CP0_DEPC = env->active_tc.PC; 597 } 598 enter_debug_mode: 599 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; 600 env->hflags &= ~(MIPS_HFLAG_KSU); 601 /* EJTAG probe trap enable is not implemented... */ 602 if (!(env->CP0_Status & (1 << CP0St_EXL))) 603 env->CP0_Cause &= ~(1 << CP0Ca_BD); 604 env->active_tc.PC = (int32_t)0xBFC00480; 605 break; 606 case EXCP_RESET: 607 cpu_reset(env); 608 break; 609 case EXCP_SRESET: 610 env->CP0_Status |= (1 << CP0St_SR); 611 memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); 612 goto set_error_EPC; 613 case EXCP_NMI: 614 env->CP0_Status |= (1 << CP0St_NMI); 615 set_error_EPC: 616 if (env->hflags & MIPS_HFLAG_BMASK) { 617 /* If the exception was raised from a delay slot, 618 come back to the jump. */ 619 env->CP0_ErrorEPC = env->active_tc.PC - 4; 620 env->hflags &= ~MIPS_HFLAG_BMASK; 621 } else { 622 env->CP0_ErrorEPC = env->active_tc.PC; 623 } 624 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); 625 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; 626 env->hflags &= ~(MIPS_HFLAG_KSU); 627 if (!(env->CP0_Status & (1 << CP0St_EXL))) 628 env->CP0_Cause &= ~(1 << CP0Ca_BD); 629 env->active_tc.PC = (int32_t)0xBFC00000; 630 break; 631 case EXCP_EXT_INTERRUPT: 632 cause = 0; 633 if (env->CP0_Cause & (1 << CP0Ca_IV)) 634 offset = 0x200; 635 goto set_EPC; 636 case EXCP_LTLBL: 637 cause = 1; 638 goto set_EPC; 639 case EXCP_TLBL: 640 cause = 2; 641 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { 642 #if defined(TARGET_MIPS64) 643 int R = env->CP0_BadVAddr >> 62; 644 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; 645 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; 646 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; 647 648 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) 649 offset = 0x080; 650 else 651 #endif 652 offset = 0x000; 653 } 654 goto set_EPC; 655 case EXCP_TLBS: 656 cause = 3; 657 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { 658 #if defined(TARGET_MIPS64) 659 int R = env->CP0_BadVAddr >> 62; 660 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; 661 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; 662 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; 663 664 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) 665 offset = 0x080; 666 else 667 #endif 668 offset = 0x000; 669 } 670 goto set_EPC; 671 case EXCP_AdEL: 672 cause = 4; 673 goto set_EPC; 674 case EXCP_AdES: 675 cause = 5; 676 goto set_EPC; 677 case EXCP_IBE: 678 cause = 6; 679 goto set_EPC; 680 case EXCP_DBE: 681 cause = 7; 682 goto set_EPC; 683 case EXCP_SYSCALL: 684 cause = 8; 685 goto set_EPC; 686 case EXCP_BREAK: 687 cause = 9; 688 goto set_EPC; 689 case EXCP_RI: 690 cause = 10; 691 goto set_EPC; 692 case EXCP_CpU: 693 cause = 11; 694 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | 695 (env->error_code << CP0Ca_CE); 696 goto set_EPC; 697 case EXCP_OVERFLOW: 698 cause = 12; 699 goto set_EPC; 700 case EXCP_TRAP: 701 cause = 13; 702 goto set_EPC; 703 case EXCP_FPE: 704 cause = 15; 705 goto set_EPC; 706 case EXCP_C2E: 707 cause = 18; 708 goto set_EPC; 709 case EXCP_MDMX: 710 cause = 22; 711 goto set_EPC; 712 case EXCP_DWATCH: 713 cause = 23; 714 /* XXX: TODO: manage defered watch exceptions */ 715 goto set_EPC; 716 case EXCP_MCHECK: 717 cause = 24; 718 goto set_EPC; 719 case EXCP_THREAD: 720 cause = 25; 721 goto set_EPC; 722 case EXCP_CACHE: 723 cause = 30; 724 if (env->CP0_Status & (1 << CP0St_BEV)) { 725 offset = 0x100; 726 } else { 727 offset = 0x20000100; 728 } 729 set_EPC: 730 if (!(env->CP0_Status & (1 << CP0St_EXL))) { 731 if (env->hflags & MIPS_HFLAG_BMASK) { 732 /* If the exception was raised from a delay slot, 733 come back to the jump. */ 734 env->CP0_EPC = env->active_tc.PC - 4; 735 env->CP0_Cause |= (1 << CP0Ca_BD); 736 } else { 737 env->CP0_EPC = env->active_tc.PC; 738 env->CP0_Cause &= ~(1 << CP0Ca_BD); 739 } 740 env->CP0_Status |= (1 << CP0St_EXL); 741 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; 742 env->hflags &= ~(MIPS_HFLAG_KSU); 743 } 744 env->hflags &= ~MIPS_HFLAG_BMASK; 745 if (env->CP0_Status & (1 << CP0St_BEV)) { 746 env->active_tc.PC = (int32_t)0xBFC00200; 747 } else { 748 env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); 749 } 750 env->active_tc.PC += offset; 751 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); 752 break; 753 default: 754 qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index); 755 printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); 756 exit(1); 757 } 758 if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { 759 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" 760 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", 761 __func__, env->active_tc.PC, env->CP0_EPC, cause, 762 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, 763 env->CP0_DEPC); 764 } 765 #endif 766 env->exception_index = EXCP_NONE; 767 } 768 769 void r4k_invalidate_tlb (CPUState *env, int idx) 770 { 771 r4k_tlb_t *tlb; 772 target_ulong addr; 773 target_ulong end; 774 uint8_t ASID = env->CP0_EntryHi & 0xFF; 775 target_ulong mask; 776 777 tlb = &env->tlb->mmu.r4k.tlb[idx]; 778 /* The qemu TLB is flushed when the ASID changes, so no need to 779 flush these entries again. */ 780 if (tlb->G == 0 && tlb->ASID != ASID) { 781 return; 782 } 783 784 /* 1k pages are not supported. */ 785 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); 786 if (tlb->V0) { 787 addr = tlb->VPN & ~mask; 788 #if defined(TARGET_MIPS64) 789 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { 790 addr |= 0x3FFFFF0000000000ULL; 791 } 792 #endif 793 end = addr | (mask >> 1); 794 while (addr < end) { 795 tlb_flush_page (env, addr); 796 addr += TARGET_PAGE_SIZE; 797 } 798 } 799 if (tlb->V1) { 800 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); 801 #if defined(TARGET_MIPS64) 802 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { 803 addr |= 0x3FFFFF0000000000ULL; 804 } 805 #endif 806 end = addr | mask; 807 while (addr - 1 < end) { 808 tlb_flush_page (env, addr); 809 addr += TARGET_PAGE_SIZE; 810 } 811 } 812 } 813
