1 /* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #include <errno.h> 17 #include <fcntl.h> 18 #include <math.h> 19 #include <poll.h> 20 #include <pthread.h> 21 #include <stdio.h> 22 #include <stdlib.h> 23 24 #include <sys/ioctl.h> 25 #include <sys/mman.h> 26 #include <sys/time.h> 27 #include <sys/resource.h> 28 29 #include <s3c-fb.h> 30 31 #include <EGL/egl.h> 32 33 #define HWC_REMOVE_DEPRECATED_VERSIONS 1 34 35 #include <cutils/compiler.h> 36 #include <cutils/log.h> 37 #include <cutils/properties.h> 38 #include <hardware/gralloc.h> 39 #include <hardware/hardware.h> 40 #include <hardware/hwcomposer.h> 41 #include <hardware_legacy/uevent.h> 42 #include <utils/String8.h> 43 #include <utils/Vector.h> 44 45 #include <sync/sync.h> 46 47 #include "ion.h" 48 #include "gralloc_priv.h" 49 #include "exynos_gscaler.h" 50 #include "exynos_format.h" 51 #include "exynos_v4l2.h" 52 #include "s5p_tvout_v4l2.h" 53 54 const size_t NUM_HW_WINDOWS = 5; 55 const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1; 56 const size_t MAX_PIXELS = 2560 * 1600 * 2; 57 const size_t GSC_W_ALIGNMENT = 16; 58 const size_t GSC_H_ALIGNMENT = 16; 59 const size_t GSC_DST_CROP_W_ALIGNMENT_RGB888 = 32; 60 const size_t GSC_DST_W_ALIGNMENT_RGB888 = 32; 61 const size_t GSC_DST_H_ALIGNMENT_RGB888 = 1; 62 const size_t FIMD_GSC_IDX = 0; 63 const size_t HDMI_GSC_IDX = 1; 64 const int AVAILABLE_GSC_UNITS[] = { 0, 3 }; 65 const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) / 66 sizeof(AVAILABLE_GSC_UNITS[0]); 67 const size_t BURSTLEN_BYTES = 16 * 8; 68 const size_t NUM_HDMI_BUFFERS = 3; 69 70 struct exynos5_hwc_composer_device_1_t; 71 72 struct exynos5_gsc_map_t { 73 enum { 74 GSC_NONE = 0, 75 GSC_M2M, 76 // TODO: GSC_LOCAL_PATH 77 } mode; 78 int idx; 79 }; 80 81 struct exynos5_hwc_post_data_t { 82 int overlay_map[NUM_HW_WINDOWS]; 83 exynos5_gsc_map_t gsc_map[NUM_HW_WINDOWS]; 84 size_t fb_window; 85 }; 86 87 const size_t NUM_GSC_DST_BUFS = 3; 88 struct exynos5_gsc_data_t { 89 void *gsc; 90 exynos_gsc_img src_cfg; 91 exynos_gsc_img dst_cfg; 92 buffer_handle_t dst_buf[NUM_GSC_DST_BUFS]; 93 int dst_buf_fence[NUM_GSC_DST_BUFS]; 94 size_t current_buf; 95 }; 96 97 struct hdmi_layer_t { 98 int id; 99 int fd; 100 bool enabled; 101 exynos_gsc_img cfg; 102 103 bool streaming; 104 size_t current_buf; 105 size_t queued_buf; 106 }; 107 108 struct exynos5_hwc_composer_device_1_t { 109 hwc_composer_device_1_t base; 110 111 int fd; 112 int vsync_fd; 113 exynos5_hwc_post_data_t bufs; 114 115 const private_module_t *gralloc_module; 116 alloc_device_t *alloc_device; 117 const hwc_procs_t *procs; 118 pthread_t vsync_thread; 119 int force_gpu; 120 121 int32_t xres; 122 int32_t yres; 123 int32_t xdpi; 124 int32_t ydpi; 125 int32_t vsync_period; 126 127 int hdmi_mixer0; 128 bool hdmi_hpd; 129 bool hdmi_enabled; 130 bool hdmi_blanked; 131 int hdmi_w; 132 int hdmi_h; 133 134 hdmi_layer_t hdmi_layers[2]; 135 136 exynos5_gsc_data_t gsc[NUM_GSC_UNITS]; 137 138 struct s3c_fb_win_config last_config[NUM_HW_WINDOWS]; 139 size_t last_fb_window; 140 const void *last_handles[NUM_HW_WINDOWS]; 141 exynos5_gsc_map_t last_gsc_map[NUM_HW_WINDOWS]; 142 }; 143 144 static void exynos5_cleanup_gsc_m2m(exynos5_hwc_composer_device_1_t *pdev, 145 size_t gsc_idx); 146 147 static void dump_handle(private_handle_t *h) 148 { 149 ALOGV("\t\tformat = %d, width = %u, height = %u, stride = %u, vstride = %u", 150 h->format, h->width, h->height, h->stride, h->vstride); 151 } 152 153 static void dump_layer(hwc_layer_1_t const *l) 154 { 155 ALOGV("\ttype=%d, flags=%08x, handle=%p, tr=%02x, blend=%04x, " 156 "{%d,%d,%d,%d}, {%d,%d,%d,%d}", 157 l->compositionType, l->flags, l->handle, l->transform, 158 l->blending, 159 l->sourceCrop.left, 160 l->sourceCrop.top, 161 l->sourceCrop.right, 162 l->sourceCrop.bottom, 163 l->displayFrame.left, 164 l->displayFrame.top, 165 l->displayFrame.right, 166 l->displayFrame.bottom); 167 168 if(l->handle && !(l->flags & HWC_SKIP_LAYER)) 169 dump_handle(private_handle_t::dynamicCast(l->handle)); 170 } 171 172 static void dump_config(s3c_fb_win_config &c) 173 { 174 ALOGV("\tstate = %u", c.state); 175 if (c.state == c.S3C_FB_WIN_STATE_BUFFER) { 176 ALOGV("\t\tfd = %d, offset = %u, stride = %u, " 177 "x = %d, y = %d, w = %u, h = %u, " 178 "format = %u, blending = %u", 179 c.fd, c.offset, c.stride, 180 c.x, c.y, c.w, c.h, 181 c.format, c.blending); 182 } 183 else if (c.state == c.S3C_FB_WIN_STATE_COLOR) { 184 ALOGV("\t\tcolor = %u", c.color); 185 } 186 } 187 188 static void dump_gsc_img(exynos_gsc_img &c) 189 { 190 ALOGV("\tx = %u, y = %u, w = %u, h = %u, fw = %u, fh = %u", 191 c.x, c.y, c.w, c.h, c.fw, c.fh); 192 ALOGV("\taddr = {%u, %u, %u}, rot = %u, cacheable = %u, drmMode = %u", 193 c.yaddr, c.uaddr, c.vaddr, c.rot, c.cacheable, c.drmMode); 194 } 195 196 inline int WIDTH(const hwc_rect &rect) { return rect.right - rect.left; } 197 inline int HEIGHT(const hwc_rect &rect) { return rect.bottom - rect.top; } 198 template<typename T> inline T max(T a, T b) { return (a > b) ? a : b; } 199 template<typename T> inline T min(T a, T b) { return (a < b) ? a : b; } 200 201 template<typename T> void align_crop_and_center(T &w, T &h, 202 hwc_rect_t *crop, size_t alignment) 203 { 204 double aspect = 1.0 * h / w; 205 T w_orig = w, h_orig = h; 206 207 w = ALIGN(w, alignment); 208 h = round(aspect * w); 209 if (crop) { 210 crop->left = (w - w_orig) / 2; 211 crop->top = (h - h_orig) / 2; 212 crop->right = crop->left + w_orig; 213 crop->bottom = crop->top + h_orig; 214 } 215 } 216 217 static bool is_transformed(const hwc_layer_1_t &layer) 218 { 219 return layer.transform != 0; 220 } 221 222 static bool is_rotated(const hwc_layer_1_t &layer) 223 { 224 return (layer.transform & HAL_TRANSFORM_ROT_90) || 225 (layer.transform & HAL_TRANSFORM_ROT_180); 226 } 227 228 static bool is_scaled(const hwc_layer_1_t &layer) 229 { 230 return WIDTH(layer.displayFrame) != WIDTH(layer.sourceCrop) || 231 HEIGHT(layer.displayFrame) != HEIGHT(layer.sourceCrop); 232 } 233 234 static inline bool gsc_dst_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 235 { 236 return c1.x != c2.x || 237 c1.y != c2.y || 238 c1.w != c2.w || 239 c1.h != c2.h || 240 c1.format != c2.format || 241 c1.rot != c2.rot || 242 c1.cacheable != c2.cacheable || 243 c1.drmMode != c2.drmMode; 244 } 245 246 static inline bool gsc_src_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 247 { 248 return gsc_dst_cfg_changed(c1, c2) || 249 c1.fw != c2.fw || 250 c1.fh != c2.fh; 251 } 252 253 static enum s3c_fb_pixel_format exynos5_format_to_s3c_format(int format) 254 { 255 switch (format) { 256 case HAL_PIXEL_FORMAT_RGBA_8888: 257 return S3C_FB_PIXEL_FORMAT_RGBA_8888; 258 case HAL_PIXEL_FORMAT_RGBX_8888: 259 return S3C_FB_PIXEL_FORMAT_RGBX_8888; 260 case HAL_PIXEL_FORMAT_RGBA_5551: 261 return S3C_FB_PIXEL_FORMAT_RGBA_5551; 262 case HAL_PIXEL_FORMAT_RGB_565: 263 return S3C_FB_PIXEL_FORMAT_RGB_565; 264 case HAL_PIXEL_FORMAT_BGRA_8888: 265 return S3C_FB_PIXEL_FORMAT_BGRA_8888; 266 default: 267 return S3C_FB_PIXEL_FORMAT_MAX; 268 } 269 } 270 271 static bool exynos5_format_is_supported(int format) 272 { 273 return exynos5_format_to_s3c_format(format) < S3C_FB_PIXEL_FORMAT_MAX; 274 } 275 276 static bool exynos5_format_is_rgb(int format) 277 { 278 switch (format) { 279 case HAL_PIXEL_FORMAT_RGBA_8888: 280 case HAL_PIXEL_FORMAT_RGBX_8888: 281 case HAL_PIXEL_FORMAT_RGB_888: 282 case HAL_PIXEL_FORMAT_RGB_565: 283 case HAL_PIXEL_FORMAT_BGRA_8888: 284 case HAL_PIXEL_FORMAT_RGBA_5551: 285 case HAL_PIXEL_FORMAT_RGBA_4444: 286 return true; 287 288 default: 289 return false; 290 } 291 } 292 293 static bool exynos5_format_is_supported_by_gscaler(int format) 294 { 295 switch (format) { 296 case HAL_PIXEL_FORMAT_RGBX_8888: 297 case HAL_PIXEL_FORMAT_RGB_565: 298 case HAL_PIXEL_FORMAT_EXYNOS_YV12: 299 case HAL_PIXEL_FORMAT_YCbCr_420_SP: 300 case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: 301 return true; 302 303 default: 304 return false; 305 } 306 } 307 308 static bool exynos5_format_is_ycrcb(int format) 309 { 310 return format == HAL_PIXEL_FORMAT_EXYNOS_YV12; 311 } 312 313 static bool exynos5_format_requires_gscaler(int format) 314 { 315 return (exynos5_format_is_supported_by_gscaler(format) && 316 (format != HAL_PIXEL_FORMAT_RGBX_8888) && (format != HAL_PIXEL_FORMAT_RGB_565)); 317 } 318 319 static uint8_t exynos5_format_to_bpp(int format) 320 { 321 switch (format) { 322 case HAL_PIXEL_FORMAT_RGBA_8888: 323 case HAL_PIXEL_FORMAT_RGBX_8888: 324 case HAL_PIXEL_FORMAT_BGRA_8888: 325 return 32; 326 327 case HAL_PIXEL_FORMAT_RGBA_5551: 328 case HAL_PIXEL_FORMAT_RGBA_4444: 329 case HAL_PIXEL_FORMAT_RGB_565: 330 return 16; 331 332 default: 333 ALOGW("unrecognized pixel format %u", format); 334 return 0; 335 } 336 } 337 338 static bool is_x_aligned(const hwc_layer_1_t &layer, int format) 339 { 340 if (!exynos5_format_is_supported(format)) 341 return true; 342 343 uint8_t bpp = exynos5_format_to_bpp(format); 344 uint8_t pixel_alignment = 32 / bpp; 345 346 return (layer.displayFrame.left % pixel_alignment) == 0 && 347 (layer.displayFrame.right % pixel_alignment) == 0; 348 } 349 350 static bool dst_crop_w_aligned(int dest_w) 351 { 352 int dst_crop_w_alignement; 353 354 /* GSC's dst crop size should be aligned 128Bytes */ 355 dst_crop_w_alignement = GSC_DST_CROP_W_ALIGNMENT_RGB888; 356 357 return (dest_w % dst_crop_w_alignement) == 0; 358 } 359 360 static bool exynos5_supports_gscaler(hwc_layer_1_t &layer, int format, 361 bool local_path) 362 { 363 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 364 365 int max_w = is_rotated(layer) ? 2048 : 4800; 366 int max_h = is_rotated(layer) ? 2048 : 3344; 367 368 bool rot90or270 = !!(layer.transform & HAL_TRANSFORM_ROT_90); 369 // n.b.: HAL_TRANSFORM_ROT_270 = HAL_TRANSFORM_ROT_90 | 370 // HAL_TRANSFORM_ROT_180 371 372 int src_w = WIDTH(layer.sourceCrop), src_h = HEIGHT(layer.sourceCrop); 373 int dest_w, dest_h; 374 if (rot90or270) { 375 dest_w = HEIGHT(layer.displayFrame); 376 dest_h = WIDTH(layer.displayFrame); 377 } else { 378 dest_w = WIDTH(layer.displayFrame); 379 dest_h = HEIGHT(layer.displayFrame); 380 } 381 382 if (handle->flags & GRALLOC_USAGE_PROTECTED) 383 align_crop_and_center(dest_w, dest_h, NULL, 384 GSC_DST_CROP_W_ALIGNMENT_RGB888); 385 386 int max_downscale = local_path ? 4 : 16; 387 const int max_upscale = 8; 388 389 return exynos5_format_is_supported_by_gscaler(format) && 390 dst_crop_w_aligned(dest_w) && 391 handle->stride <= max_w && 392 handle->stride % GSC_W_ALIGNMENT == 0 && 393 src_w <= dest_w * max_downscale && 394 dest_w <= src_w * max_upscale && 395 handle->vstride <= max_h && 396 handle->vstride % GSC_H_ALIGNMENT == 0 && 397 src_h <= dest_h * max_downscale && 398 dest_h <= src_h * max_upscale && 399 // per 46.2 400 (!rot90or270 || layer.sourceCrop.top % 2 == 0) && 401 (!rot90or270 || layer.sourceCrop.left % 2 == 0); 402 // per 46.3.1.6 403 } 404 405 static bool exynos5_requires_gscaler(hwc_layer_1_t &layer, int format) 406 { 407 return exynos5_format_requires_gscaler(format) || is_scaled(layer) 408 || is_transformed(layer) || !is_x_aligned(layer, format); 409 } 410 411 int hdmi_get_config(struct exynos5_hwc_composer_device_1_t *dev) 412 { 413 struct v4l2_dv_preset preset; 414 struct v4l2_dv_enum_preset enum_preset; 415 int index = 0; 416 bool found = false; 417 int ret; 418 419 if (ioctl(dev->hdmi_layers[0].fd, VIDIOC_G_DV_PRESET, &preset) < 0) { 420 ALOGE("%s: g_dv_preset error, %d", __func__, errno); 421 return -1; 422 } 423 424 while (true) { 425 enum_preset.index = index++; 426 ret = ioctl(dev->hdmi_layers[0].fd, VIDIOC_ENUM_DV_PRESETS, &enum_preset); 427 428 if (ret < 0) { 429 if (errno == EINVAL) 430 break; 431 ALOGE("%s: enum_dv_presets error, %d", __func__, errno); 432 return -1; 433 } 434 435 ALOGV("%s: %d preset=%02d width=%d height=%d name=%s", 436 __func__, enum_preset.index, enum_preset.preset, 437 enum_preset.width, enum_preset.height, enum_preset.name); 438 439 if (preset.preset == enum_preset.preset) { 440 dev->hdmi_w = enum_preset.width; 441 dev->hdmi_h = enum_preset.height; 442 found = true; 443 } 444 } 445 446 return found ? 0 : -1; 447 } 448 449 static enum s3c_fb_blending exynos5_blending_to_s3c_blending(int32_t blending) 450 { 451 switch (blending) { 452 case HWC_BLENDING_NONE: 453 return S3C_FB_BLENDING_NONE; 454 case HWC_BLENDING_PREMULT: 455 return S3C_FB_BLENDING_PREMULT; 456 case HWC_BLENDING_COVERAGE: 457 return S3C_FB_BLENDING_COVERAGE; 458 459 default: 460 return S3C_FB_BLENDING_MAX; 461 } 462 } 463 464 static bool exynos5_blending_is_supported(int32_t blending) 465 { 466 return exynos5_blending_to_s3c_blending(blending) < S3C_FB_BLENDING_MAX; 467 } 468 469 470 static int hdmi_enable_layer(struct exynos5_hwc_composer_device_1_t *dev, 471 hdmi_layer_t &hl) 472 { 473 if (hl.enabled) 474 return 0; 475 476 struct v4l2_requestbuffers reqbuf; 477 memset(&reqbuf, 0, sizeof(reqbuf)); 478 reqbuf.count = NUM_HDMI_BUFFERS; 479 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 480 reqbuf.memory = V4L2_MEMORY_DMABUF; 481 if (exynos_v4l2_reqbufs(hl.fd, &reqbuf) < 0) { 482 ALOGE("%s: layer%d: reqbufs failed %d", __func__, hl.id, errno); 483 return -1; 484 } 485 486 if (reqbuf.count != NUM_HDMI_BUFFERS) { 487 ALOGE("%s: layer%d: didn't get buffer", __func__, hl.id); 488 return -1; 489 } 490 491 if (hl.id == 1) { 492 if (exynos_v4l2_s_ctrl(hl.fd, V4L2_CID_TV_PIXEL_BLEND_ENABLE, 1) < 0) { 493 ALOGE("%s: layer%d: PIXEL_BLEND_ENABLE failed %d", __func__, 494 hl.id, errno); 495 return -1; 496 } 497 } 498 499 ALOGV("%s: layer%d enabled", __func__, hl.id); 500 hl.enabled = true; 501 return 0; 502 } 503 504 static void hdmi_disable_layer(struct exynos5_hwc_composer_device_1_t *dev, 505 hdmi_layer_t &hl) 506 { 507 if (!hl.enabled) 508 return; 509 510 if (hl.streaming) { 511 if (exynos_v4l2_streamoff(hl.fd, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) < 0) 512 ALOGE("%s: layer%d: streamoff failed %d", __func__, hl.id, errno); 513 hl.streaming = false; 514 } 515 516 struct v4l2_requestbuffers reqbuf; 517 memset(&reqbuf, 0, sizeof(reqbuf)); 518 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 519 reqbuf.memory = V4L2_MEMORY_DMABUF; 520 if (exynos_v4l2_reqbufs(hl.fd, &reqbuf) < 0) 521 ALOGE("%s: layer%d: reqbufs failed %d", __func__, hl.id, errno); 522 523 memset(&hl.cfg, 0, sizeof(hl.cfg)); 524 hl.current_buf = 0; 525 hl.queued_buf = 0; 526 hl.enabled = false; 527 528 ALOGV("%s: layer%d disabled", __func__, hl.id); 529 } 530 531 static int hdmi_enable(struct exynos5_hwc_composer_device_1_t *dev) 532 { 533 if (dev->hdmi_enabled) 534 return 0; 535 536 if (dev->hdmi_blanked) 537 return 0; 538 539 struct v4l2_subdev_format sd_fmt; 540 memset(&sd_fmt, 0, sizeof(sd_fmt)); 541 sd_fmt.pad = MIXER_G0_SUBDEV_PAD_SINK; 542 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 543 sd_fmt.format.width = dev->hdmi_w; 544 sd_fmt.format.height = dev->hdmi_h; 545 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 546 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 547 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 548 return -1; 549 } 550 551 struct v4l2_subdev_crop sd_crop; 552 memset(&sd_crop, 0, sizeof(sd_crop)); 553 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SINK; 554 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 555 sd_crop.rect.width = dev->hdmi_w; 556 sd_crop.rect.height = dev->hdmi_h; 557 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 558 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 559 return -1; 560 } 561 562 memset(&sd_fmt, 0, sizeof(sd_fmt)); 563 sd_fmt.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 564 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 565 sd_fmt.format.width = dev->hdmi_w; 566 sd_fmt.format.height = dev->hdmi_h; 567 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 568 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 569 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 570 return -1; 571 } 572 573 memset(&sd_crop, 0, sizeof(sd_crop)); 574 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 575 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 576 sd_crop.rect.width = dev->hdmi_w; 577 sd_crop.rect.height = dev->hdmi_h; 578 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 579 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 580 return -1; 581 } 582 583 char value[PROPERTY_VALUE_MAX]; 584 property_get("persist.hdmi.hdcp_enabled", value, "1"); 585 int hdcp_enabled = atoi(value); 586 587 if (exynos_v4l2_s_ctrl(dev->hdmi_layers[1].fd, V4L2_CID_TV_HDCP_ENABLE, 588 hdcp_enabled) < 0) 589 ALOGE("%s: s_ctrl(CID_TV_HDCP_ENABLE) failed %d", __func__, errno); 590 591 /* "3" is RGB709_16_235 */ 592 property_get("persist.hdmi.color_range", value, "3"); 593 int color_range = atoi(value); 594 595 if (exynos_v4l2_s_ctrl(dev->hdmi_layers[1].fd, V4L2_CID_TV_SET_COLOR_RANGE, 596 color_range) < 0) 597 ALOGE("%s: s_ctrl(CID_TV_COLOR_RANGE) failed %d", __func__, errno); 598 599 hdmi_enable_layer(dev, dev->hdmi_layers[1]); 600 601 dev->hdmi_enabled = true; 602 return 0; 603 } 604 605 static void hdmi_disable(struct exynos5_hwc_composer_device_1_t *dev) 606 { 607 if (!dev->hdmi_enabled) 608 return; 609 610 hdmi_disable_layer(dev, dev->hdmi_layers[0]); 611 hdmi_disable_layer(dev, dev->hdmi_layers[1]); 612 613 exynos5_cleanup_gsc_m2m(dev, HDMI_GSC_IDX); 614 dev->hdmi_enabled = false; 615 } 616 617 static int hdmi_output(struct exynos5_hwc_composer_device_1_t *dev, 618 hdmi_layer_t &hl, 619 hwc_layer_1_t &layer, 620 private_handle_t *h, 621 int acquireFenceFd, 622 int *releaseFenceFd) 623 { 624 int ret = 0; 625 626 exynos_gsc_img cfg; 627 memset(&cfg, 0, sizeof(cfg)); 628 cfg.x = layer.displayFrame.left; 629 cfg.y = layer.displayFrame.top; 630 cfg.w = WIDTH(layer.displayFrame); 631 cfg.h = HEIGHT(layer.displayFrame); 632 633 if (gsc_src_cfg_changed(hl.cfg, cfg)) { 634 hdmi_disable_layer(dev, hl); 635 636 struct v4l2_format fmt; 637 memset(&fmt, 0, sizeof(fmt)); 638 fmt.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 639 fmt.fmt.pix_mp.width = h->stride; 640 fmt.fmt.pix_mp.height = cfg.h; 641 fmt.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_BGR32; 642 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY; 643 fmt.fmt.pix_mp.num_planes = 1; 644 ret = exynos_v4l2_s_fmt(hl.fd, &fmt); 645 if (ret < 0) { 646 ALOGE("%s: layer%d: s_fmt failed %d", __func__, hl.id, errno); 647 goto err; 648 } 649 650 struct v4l2_subdev_crop sd_crop; 651 memset(&sd_crop, 0, sizeof(sd_crop)); 652 if (hl.id == 0) 653 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 654 else 655 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 656 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 657 sd_crop.rect.left = cfg.x; 658 sd_crop.rect.top = cfg.y; 659 sd_crop.rect.width = cfg.w; 660 sd_crop.rect.height = cfg.h; 661 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 662 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 663 goto err; 664 } 665 666 hdmi_enable_layer(dev, hl); 667 668 ALOGV("HDMI layer%d configuration:", hl.id); 669 dump_gsc_img(cfg); 670 hl.cfg = cfg; 671 } 672 673 struct v4l2_buffer buffer; 674 struct v4l2_plane planes[1]; 675 676 if (hl.queued_buf == NUM_HDMI_BUFFERS) { 677 memset(&buffer, 0, sizeof(buffer)); 678 memset(planes, 0, sizeof(planes)); 679 buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 680 buffer.memory = V4L2_MEMORY_DMABUF; 681 buffer.length = 1; 682 buffer.m.planes = planes; 683 ret = exynos_v4l2_dqbuf(hl.fd, &buffer); 684 if (ret < 0) { 685 ALOGE("%s: layer%d: dqbuf failed %d", __func__, hl.id, errno); 686 goto err; 687 } 688 hl.queued_buf--; 689 } 690 691 memset(&buffer, 0, sizeof(buffer)); 692 memset(planes, 0, sizeof(planes)); 693 buffer.index = hl.current_buf; 694 buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 695 buffer.memory = V4L2_MEMORY_DMABUF; 696 buffer.flags = V4L2_BUF_FLAG_USE_SYNC; 697 buffer.reserved = acquireFenceFd; 698 buffer.length = 1; 699 buffer.m.planes = planes; 700 buffer.m.planes[0].m.fd = h->fd; 701 if (exynos_v4l2_qbuf(hl.fd, &buffer) < 0) { 702 ALOGE("%s: layer%d: qbuf failed %d", __func__, hl.id, errno); 703 ret = -1; 704 goto err; 705 } 706 707 if (releaseFenceFd) 708 *releaseFenceFd = buffer.reserved; 709 else 710 close(buffer.reserved); 711 712 hl.queued_buf++; 713 hl.current_buf = (hl.current_buf + 1) % NUM_HDMI_BUFFERS; 714 715 if (!hl.streaming) { 716 if (exynos_v4l2_streamon(hl.fd, buffer.type) < 0) { 717 ALOGE("%s: layer%d: streamon failed %d", __func__, hl.id, errno); 718 ret = -1; 719 goto err; 720 } 721 hl.streaming = true; 722 } 723 724 err: 725 if (acquireFenceFd >= 0) 726 close(acquireFenceFd); 727 728 return ret; 729 } 730 731 bool exynos5_is_offscreen(hwc_layer_1_t &layer, 732 struct exynos5_hwc_composer_device_1_t *pdev) 733 { 734 return layer.sourceCrop.left > pdev->xres || 735 layer.sourceCrop.right < 0 || 736 layer.sourceCrop.top > pdev->yres || 737 layer.sourceCrop.bottom < 0; 738 } 739 740 size_t exynos5_visible_width(hwc_layer_1_t &layer, int format, 741 struct exynos5_hwc_composer_device_1_t *pdev) 742 { 743 int bpp; 744 if (exynos5_requires_gscaler(layer, format)) 745 bpp = 32; 746 else 747 bpp = exynos5_format_to_bpp(format); 748 int left = max(layer.displayFrame.left, 0); 749 int right = min(layer.displayFrame.right, pdev->xres); 750 751 return (right - left) * bpp / 8; 752 } 753 754 bool exynos5_supports_overlay(hwc_layer_1_t &layer, size_t i, 755 struct exynos5_hwc_composer_device_1_t *pdev) 756 { 757 if (layer.flags & HWC_SKIP_LAYER) { 758 ALOGV("\tlayer %u: skipping", i); 759 return false; 760 } 761 762 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 763 764 if (!handle) { 765 ALOGV("\tlayer %u: handle is NULL", i); 766 return false; 767 } 768 769 if (exynos5_visible_width(layer, handle->format, pdev) < BURSTLEN_BYTES) { 770 ALOGV("\tlayer %u: visible area is too narrow", i); 771 return false; 772 } 773 if (exynos5_requires_gscaler(layer, handle->format)) { 774 if (!exynos5_supports_gscaler(layer, handle->format, false)) { 775 ALOGV("\tlayer %u: gscaler required but not supported", i); 776 return false; 777 } 778 } else { 779 if (!exynos5_format_is_supported(handle->format)) { 780 ALOGV("\tlayer %u: pixel format %u not supported", i, handle->format); 781 return false; 782 } 783 } 784 if (!exynos5_blending_is_supported(layer.blending)) { 785 ALOGV("\tlayer %u: blending %d not supported", i, layer.blending); 786 return false; 787 } 788 if (CC_UNLIKELY(exynos5_is_offscreen(layer, pdev))) { 789 ALOGW("\tlayer %u: off-screen", i); 790 return false; 791 } 792 793 return true; 794 } 795 796 inline bool intersect(const hwc_rect &r1, const hwc_rect &r2) 797 { 798 return !(r1.left > r2.right || 799 r1.right < r2.left || 800 r1.top > r2.bottom || 801 r1.bottom < r2.top); 802 } 803 804 inline hwc_rect intersection(const hwc_rect &r1, const hwc_rect &r2) 805 { 806 hwc_rect i; 807 i.top = max(r1.top, r2.top); 808 i.bottom = min(r1.bottom, r2.bottom); 809 i.left = max(r1.left, r2.left); 810 i.right = min(r1.right, r2.right); 811 return i; 812 } 813 814 static int exynos5_prepare_fimd(exynos5_hwc_composer_device_1_t *pdev, 815 hwc_display_contents_1_t* contents) 816 { 817 ALOGV("preparing %u layers for FIMD", contents->numHwLayers); 818 819 memset(pdev->bufs.gsc_map, 0, sizeof(pdev->bufs.gsc_map)); 820 821 bool force_fb = pdev->force_gpu; 822 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 823 pdev->bufs.overlay_map[i] = -1; 824 825 bool fb_needed = false; 826 size_t first_fb = 0, last_fb = 0; 827 828 // find unsupported overlays 829 for (size_t i = 0; i < contents->numHwLayers; i++) { 830 hwc_layer_1_t &layer = contents->hwLayers[i]; 831 832 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 833 ALOGV("\tlayer %u: framebuffer target", i); 834 continue; 835 } 836 837 if (layer.compositionType == HWC_BACKGROUND && !force_fb) { 838 ALOGV("\tlayer %u: background supported", i); 839 dump_layer(&contents->hwLayers[i]); 840 continue; 841 } 842 843 if (exynos5_supports_overlay(contents->hwLayers[i], i, pdev) && 844 !force_fb) { 845 ALOGV("\tlayer %u: overlay supported", i); 846 layer.compositionType = HWC_OVERLAY; 847 dump_layer(&contents->hwLayers[i]); 848 continue; 849 } 850 851 if (!fb_needed) { 852 first_fb = i; 853 fb_needed = true; 854 } 855 last_fb = i; 856 layer.compositionType = HWC_FRAMEBUFFER; 857 858 dump_layer(&contents->hwLayers[i]); 859 } 860 861 // can't composite overlays sandwiched between framebuffers 862 if (fb_needed) 863 for (size_t i = first_fb; i < last_fb; i++) 864 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 865 866 // Incrementally try to add our supported layers to hardware windows. 867 // If adding a layer would violate a hardware constraint, force it 868 // into the framebuffer and try again. (Revisiting the entire list is 869 // necessary because adding a layer to the framebuffer can cause other 870 // windows to retroactively violate constraints.) 871 bool changed; 872 bool gsc_used; 873 do { 874 android::Vector<hwc_rect> rects; 875 android::Vector<hwc_rect> overlaps; 876 size_t pixels_left, windows_left; 877 878 gsc_used = false; 879 880 if (fb_needed) { 881 hwc_rect_t fb_rect; 882 fb_rect.top = fb_rect.left = 0; 883 fb_rect.right = pdev->xres - 1; 884 fb_rect.bottom = pdev->yres - 1; 885 pixels_left = MAX_PIXELS - pdev->xres * pdev->yres; 886 windows_left = NUM_HW_WINDOWS - 1; 887 rects.push_back(fb_rect); 888 } 889 else { 890 pixels_left = MAX_PIXELS; 891 windows_left = NUM_HW_WINDOWS; 892 } 893 894 changed = false; 895 896 for (size_t i = 0; i < contents->numHwLayers; i++) { 897 hwc_layer_1_t &layer = contents->hwLayers[i]; 898 if ((layer.flags & HWC_SKIP_LAYER) || 899 layer.compositionType == HWC_FRAMEBUFFER_TARGET) 900 continue; 901 902 private_handle_t *handle = private_handle_t::dynamicCast( 903 layer.handle); 904 905 // we've already accounted for the framebuffer above 906 if (layer.compositionType == HWC_FRAMEBUFFER) 907 continue; 908 909 // only layer 0 can be HWC_BACKGROUND, so we can 910 // unconditionally allow it without extra checks 911 if (layer.compositionType == HWC_BACKGROUND) { 912 windows_left--; 913 continue; 914 } 915 916 size_t pixels_needed = WIDTH(layer.displayFrame) * 917 HEIGHT(layer.displayFrame); 918 bool can_compose = windows_left && pixels_needed <= pixels_left; 919 bool gsc_required = exynos5_requires_gscaler(layer, handle->format); 920 if (gsc_required) 921 can_compose = can_compose && !gsc_used; 922 923 // hwc_rect_t right and bottom values are normally exclusive; 924 // the intersection logic is simpler if we make them inclusive 925 hwc_rect_t visible_rect = layer.displayFrame; 926 visible_rect.right--; visible_rect.bottom--; 927 928 // no more than 2 layers can overlap on a given pixel 929 for (size_t j = 0; can_compose && j < overlaps.size(); j++) { 930 if (intersect(visible_rect, overlaps.itemAt(j))) 931 can_compose = false; 932 } 933 934 if (!can_compose) { 935 layer.compositionType = HWC_FRAMEBUFFER; 936 if (!fb_needed) { 937 first_fb = last_fb = i; 938 fb_needed = true; 939 } 940 else { 941 first_fb = min(i, first_fb); 942 last_fb = max(i, last_fb); 943 } 944 changed = true; 945 break; 946 } 947 948 for (size_t j = 0; j < rects.size(); j++) { 949 const hwc_rect_t &other_rect = rects.itemAt(j); 950 if (intersect(visible_rect, other_rect)) 951 overlaps.push_back(intersection(visible_rect, other_rect)); 952 } 953 rects.push_back(visible_rect); 954 pixels_left -= pixels_needed; 955 windows_left--; 956 if (gsc_required) 957 gsc_used = true; 958 } 959 960 if (changed) 961 for (size_t i = first_fb; i < last_fb; i++) 962 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 963 } while(changed); 964 965 unsigned int nextWindow = 0; 966 967 for (size_t i = 0; i < contents->numHwLayers; i++) { 968 hwc_layer_1_t &layer = contents->hwLayers[i]; 969 970 if (fb_needed && i == first_fb) { 971 ALOGV("assigning framebuffer to window %u\n", 972 nextWindow); 973 nextWindow++; 974 continue; 975 } 976 977 if (layer.compositionType != HWC_FRAMEBUFFER && 978 layer.compositionType != HWC_FRAMEBUFFER_TARGET) { 979 ALOGV("assigning layer %u to window %u", i, nextWindow); 980 pdev->bufs.overlay_map[nextWindow] = i; 981 if (layer.compositionType == HWC_OVERLAY) { 982 private_handle_t *handle = 983 private_handle_t::dynamicCast(layer.handle); 984 if (exynos5_requires_gscaler(layer, handle->format)) { 985 ALOGV("\tusing gscaler %u", AVAILABLE_GSC_UNITS[FIMD_GSC_IDX]); 986 pdev->bufs.gsc_map[nextWindow].mode = 987 exynos5_gsc_map_t::GSC_M2M; 988 pdev->bufs.gsc_map[nextWindow].idx = FIMD_GSC_IDX; 989 } 990 } 991 nextWindow++; 992 } 993 } 994 995 if (!gsc_used) 996 exynos5_cleanup_gsc_m2m(pdev, FIMD_GSC_IDX); 997 998 if (fb_needed) 999 pdev->bufs.fb_window = first_fb; 1000 else 1001 pdev->bufs.fb_window = NO_FB_NEEDED; 1002 1003 return 0; 1004 } 1005 1006 static int exynos5_prepare_hdmi(exynos5_hwc_composer_device_1_t *pdev, 1007 hwc_display_contents_1_t* contents) 1008 { 1009 ALOGV("preparing %u layers for HDMI", contents->numHwLayers); 1010 hwc_layer_1_t *video_layer = NULL; 1011 1012 for (size_t i = 0; i < contents->numHwLayers; i++) { 1013 hwc_layer_1_t &layer = contents->hwLayers[i]; 1014 1015 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 1016 ALOGV("\tlayer %u: framebuffer target", i); 1017 continue; 1018 } 1019 1020 if (layer.compositionType == HWC_BACKGROUND) { 1021 ALOGV("\tlayer %u: background layer", i); 1022 dump_layer(&layer); 1023 continue; 1024 } 1025 1026 if (layer.handle) { 1027 private_handle_t *h = private_handle_t::dynamicCast(layer.handle); 1028 if (h->flags & GRALLOC_USAGE_PROTECTED) { 1029 if (!video_layer) { 1030 video_layer = &layer; 1031 layer.compositionType = HWC_OVERLAY; 1032 ALOGV("\tlayer %u: video layer", i); 1033 dump_layer(&layer); 1034 continue; 1035 } 1036 } 1037 } 1038 1039 layer.compositionType = HWC_FRAMEBUFFER; 1040 dump_layer(&layer); 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int exynos5_prepare(hwc_composer_device_1_t *dev, 1047 size_t numDisplays, hwc_display_contents_1_t** displays) 1048 { 1049 if (!numDisplays || !displays) 1050 return 0; 1051 1052 exynos5_hwc_composer_device_1_t *pdev = 1053 (exynos5_hwc_composer_device_1_t *)dev; 1054 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 1055 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 1056 1057 if (pdev->hdmi_hpd) { 1058 hdmi_enable(pdev); 1059 } else { 1060 hdmi_disable(pdev); 1061 } 1062 1063 if (fimd_contents) { 1064 int err = exynos5_prepare_fimd(pdev, fimd_contents); 1065 if (err) 1066 return err; 1067 } 1068 1069 if (hdmi_contents) { 1070 int err = exynos5_prepare_hdmi(pdev, hdmi_contents); 1071 if (err) 1072 return err; 1073 } 1074 1075 return 0; 1076 } 1077 1078 static int exynos5_config_gsc_m2m(hwc_layer_1_t &layer, 1079 alloc_device_t* alloc_device, exynos5_gsc_data_t *gsc_data, 1080 int gsc_idx, int dst_format, hwc_rect_t *sourceCrop) 1081 { 1082 ALOGV("configuring gscaler %u for memory-to-memory", AVAILABLE_GSC_UNITS[gsc_idx]); 1083 1084 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 1085 buffer_handle_t dst_buf; 1086 private_handle_t *dst_handle; 1087 int ret = 0; 1088 1089 exynos_gsc_img src_cfg, dst_cfg; 1090 memset(&src_cfg, 0, sizeof(src_cfg)); 1091 memset(&dst_cfg, 0, sizeof(dst_cfg)); 1092 1093 hwc_rect_t sourceCropTemp; 1094 if (!sourceCrop) 1095 sourceCrop = &sourceCropTemp; 1096 1097 src_cfg.x = layer.sourceCrop.left; 1098 src_cfg.y = layer.sourceCrop.top; 1099 src_cfg.w = WIDTH(layer.sourceCrop); 1100 src_cfg.fw = src_handle->stride; 1101 src_cfg.h = HEIGHT(layer.sourceCrop); 1102 src_cfg.fh = src_handle->vstride; 1103 src_cfg.yaddr = src_handle->fd; 1104 if (exynos5_format_is_ycrcb(src_handle->format)) { 1105 src_cfg.uaddr = src_handle->fd2; 1106 src_cfg.vaddr = src_handle->fd1; 1107 } else { 1108 src_cfg.uaddr = src_handle->fd1; 1109 src_cfg.vaddr = src_handle->fd2; 1110 } 1111 src_cfg.format = src_handle->format; 1112 src_cfg.drmMode = !!(src_handle->flags & GRALLOC_USAGE_PROTECTED); 1113 src_cfg.acquireFenceFd = layer.acquireFenceFd; 1114 layer.acquireFenceFd = -1; 1115 1116 dst_cfg.x = 0; 1117 dst_cfg.y = 0; 1118 dst_cfg.w = WIDTH(layer.displayFrame); 1119 dst_cfg.h = HEIGHT(layer.displayFrame); 1120 dst_cfg.rot = layer.transform; 1121 dst_cfg.drmMode = src_cfg.drmMode; 1122 dst_cfg.format = dst_format; 1123 dst_cfg.narrowRgb = !exynos5_format_is_rgb(src_handle->format); 1124 if (dst_cfg.drmMode) 1125 align_crop_and_center(dst_cfg.w, dst_cfg.h, sourceCrop, 1126 GSC_DST_CROP_W_ALIGNMENT_RGB888); 1127 1128 ALOGV("source configuration:"); 1129 dump_gsc_img(src_cfg); 1130 1131 bool reconfigure = gsc_src_cfg_changed(src_cfg, gsc_data->src_cfg) || 1132 gsc_dst_cfg_changed(dst_cfg, gsc_data->dst_cfg); 1133 if (reconfigure) { 1134 int dst_stride; 1135 int usage = GRALLOC_USAGE_SW_READ_NEVER | 1136 GRALLOC_USAGE_SW_WRITE_NEVER | 1137 GRALLOC_USAGE_HW_COMPOSER; 1138 1139 if (src_handle->flags & GRALLOC_USAGE_PROTECTED) 1140 usage |= GRALLOC_USAGE_PROTECTED; 1141 1142 int w = ALIGN(dst_cfg.w, GSC_DST_W_ALIGNMENT_RGB888); 1143 int h = ALIGN(dst_cfg.h, GSC_DST_H_ALIGNMENT_RGB888); 1144 1145 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1146 if (gsc_data->dst_buf[i]) { 1147 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1148 gsc_data->dst_buf[i] = NULL; 1149 } 1150 1151 if (gsc_data->dst_buf_fence[i] >= 0) { 1152 close(gsc_data->dst_buf_fence[i]); 1153 gsc_data->dst_buf_fence[i] = -1; 1154 } 1155 1156 int ret = alloc_device->alloc(alloc_device, w, h, 1157 HAL_PIXEL_FORMAT_RGBX_8888, usage, &gsc_data->dst_buf[i], 1158 &dst_stride); 1159 if (ret < 0) { 1160 ALOGE("failed to allocate destination buffer: %s", 1161 strerror(-ret)); 1162 goto err_alloc; 1163 } 1164 } 1165 1166 gsc_data->current_buf = 0; 1167 } 1168 1169 dst_buf = gsc_data->dst_buf[gsc_data->current_buf]; 1170 dst_handle = private_handle_t::dynamicCast(dst_buf); 1171 1172 dst_cfg.fw = dst_handle->stride; 1173 dst_cfg.fh = dst_handle->vstride; 1174 dst_cfg.yaddr = dst_handle->fd; 1175 dst_cfg.acquireFenceFd = gsc_data->dst_buf_fence[gsc_data->current_buf]; 1176 gsc_data->dst_buf_fence[gsc_data->current_buf] = -1; 1177 1178 ALOGV("destination configuration:"); 1179 dump_gsc_img(dst_cfg); 1180 1181 if ((int)dst_cfg.w != WIDTH(layer.displayFrame)) 1182 ALOGV("padding %u x %u output to %u x %u and cropping to {%u,%u,%u,%u}", 1183 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame), 1184 dst_cfg.w, dst_cfg.h, sourceCrop->left, sourceCrop->top, 1185 sourceCrop->right, sourceCrop->bottom); 1186 1187 if (gsc_data->gsc) { 1188 ALOGV("reusing open gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]); 1189 } else { 1190 ALOGV("opening gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]); 1191 gsc_data->gsc = exynos_gsc_create_exclusive( 1192 AVAILABLE_GSC_UNITS[gsc_idx], GSC_M2M_MODE, GSC_DUMMY, true); 1193 if (!gsc_data->gsc) { 1194 ALOGE("failed to create gscaler handle"); 1195 ret = -1; 1196 goto err_alloc; 1197 } 1198 } 1199 1200 if (reconfigure) { 1201 ret = exynos_gsc_stop_exclusive(gsc_data->gsc); 1202 if (ret < 0) { 1203 ALOGE("failed to stop gscaler %u", gsc_idx); 1204 goto err_gsc_config; 1205 } 1206 1207 ret = exynos_gsc_config_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1208 if (ret < 0) { 1209 ALOGE("failed to configure gscaler %u", gsc_idx); 1210 goto err_gsc_config; 1211 } 1212 } 1213 1214 ret = exynos_gsc_run_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1215 if (ret < 0) { 1216 ALOGE("failed to run gscaler %u", gsc_idx); 1217 goto err_gsc_config; 1218 } 1219 1220 gsc_data->src_cfg = src_cfg; 1221 gsc_data->dst_cfg = dst_cfg; 1222 1223 layer.releaseFenceFd = src_cfg.releaseFenceFd; 1224 1225 return 0; 1226 1227 err_gsc_config: 1228 exynos_gsc_destroy(gsc_data->gsc); 1229 gsc_data->gsc = NULL; 1230 err_alloc: 1231 if (src_cfg.acquireFenceFd >= 0) 1232 close(src_cfg.acquireFenceFd); 1233 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1234 if (gsc_data->dst_buf[i]) { 1235 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1236 gsc_data->dst_buf[i] = NULL; 1237 } 1238 if (gsc_data->dst_buf_fence[i] >= 0) { 1239 close(gsc_data->dst_buf_fence[i]); 1240 gsc_data->dst_buf_fence[i] = -1; 1241 } 1242 } 1243 memset(&gsc_data->src_cfg, 0, sizeof(gsc_data->src_cfg)); 1244 memset(&gsc_data->dst_cfg, 0, sizeof(gsc_data->dst_cfg)); 1245 return ret; 1246 } 1247 1248 1249 static void exynos5_cleanup_gsc_m2m(exynos5_hwc_composer_device_1_t *pdev, 1250 size_t gsc_idx) 1251 { 1252 exynos5_gsc_data_t &gsc_data = pdev->gsc[gsc_idx]; 1253 if (!gsc_data.gsc) 1254 return; 1255 1256 ALOGV("closing gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]); 1257 1258 exynos_gsc_stop_exclusive(gsc_data.gsc); 1259 exynos_gsc_destroy(gsc_data.gsc); 1260 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1261 if (gsc_data.dst_buf[i]) 1262 pdev->alloc_device->free(pdev->alloc_device, gsc_data.dst_buf[i]); 1263 if (gsc_data.dst_buf_fence[i] >= 0) 1264 close(gsc_data.dst_buf_fence[i]); 1265 } 1266 1267 memset(&gsc_data, 0, sizeof(gsc_data)); 1268 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) 1269 gsc_data.dst_buf_fence[i] = -1; 1270 } 1271 1272 static void exynos5_config_handle(private_handle_t *handle, 1273 hwc_rect_t &sourceCrop, hwc_rect_t &displayFrame, 1274 int32_t blending, int fence_fd, s3c_fb_win_config &cfg, 1275 exynos5_hwc_composer_device_1_t *pdev) 1276 { 1277 uint32_t x, y; 1278 uint32_t w = WIDTH(displayFrame); 1279 uint32_t h = HEIGHT(displayFrame); 1280 uint8_t bpp = exynos5_format_to_bpp(handle->format); 1281 uint32_t offset = (sourceCrop.top * handle->stride + sourceCrop.left) * bpp / 8; 1282 1283 if (displayFrame.left < 0) { 1284 unsigned int crop = -displayFrame.left; 1285 ALOGV("layer off left side of screen; cropping %u pixels from left edge", 1286 crop); 1287 x = 0; 1288 w -= crop; 1289 offset += crop * bpp / 8; 1290 } else { 1291 x = displayFrame.left; 1292 } 1293 1294 if (displayFrame.right > pdev->xres) { 1295 unsigned int crop = displayFrame.right - pdev->xres; 1296 ALOGV("layer off right side of screen; cropping %u pixels from right edge", 1297 crop); 1298 w -= crop; 1299 } 1300 1301 if (displayFrame.top < 0) { 1302 unsigned int crop = -displayFrame.top; 1303 ALOGV("layer off top side of screen; cropping %u pixels from top edge", 1304 crop); 1305 y = 0; 1306 h -= crop; 1307 offset += handle->stride * crop * bpp / 8; 1308 } else { 1309 y = displayFrame.top; 1310 } 1311 1312 if (displayFrame.bottom > pdev->yres) { 1313 int crop = displayFrame.bottom - pdev->yres; 1314 ALOGV("layer off bottom side of screen; cropping %u pixels from bottom edge", 1315 crop); 1316 h -= crop; 1317 } 1318 1319 cfg.state = cfg.S3C_FB_WIN_STATE_BUFFER; 1320 cfg.fd = handle->fd; 1321 cfg.x = x; 1322 cfg.y = y; 1323 cfg.w = w; 1324 cfg.h = h; 1325 cfg.format = exynos5_format_to_s3c_format(handle->format); 1326 cfg.offset = offset; 1327 cfg.stride = handle->stride * bpp / 8; 1328 cfg.blending = exynos5_blending_to_s3c_blending(blending); 1329 cfg.fence_fd = fence_fd; 1330 } 1331 1332 static void exynos5_config_overlay(hwc_layer_1_t *layer, s3c_fb_win_config &cfg, 1333 exynos5_hwc_composer_device_1_t *pdev) 1334 { 1335 if (layer->compositionType == HWC_BACKGROUND) { 1336 hwc_color_t color = layer->backgroundColor; 1337 cfg.state = cfg.S3C_FB_WIN_STATE_COLOR; 1338 cfg.color = (color.r << 16) | (color.g << 8) | color.b; 1339 cfg.x = 0; 1340 cfg.y = 0; 1341 cfg.w = pdev->xres; 1342 cfg.h = pdev->yres; 1343 return; 1344 } 1345 1346 private_handle_t *handle = private_handle_t::dynamicCast(layer->handle); 1347 exynos5_config_handle(handle, layer->sourceCrop, layer->displayFrame, 1348 layer->blending, layer->acquireFenceFd, cfg, pdev); 1349 } 1350 1351 static int exynos5_post_fimd(exynos5_hwc_composer_device_1_t *pdev, 1352 hwc_display_contents_1_t* contents) 1353 { 1354 exynos5_hwc_post_data_t *pdata = &pdev->bufs; 1355 struct s3c_fb_win_config_data win_data; 1356 struct s3c_fb_win_config *config = win_data.config; 1357 1358 memset(config, 0, sizeof(win_data.config)); 1359 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1360 config[i].fence_fd = -1; 1361 1362 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1363 int layer_idx = pdata->overlay_map[i]; 1364 if (layer_idx != -1) { 1365 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1366 private_handle_t *handle = 1367 private_handle_t::dynamicCast(layer.handle); 1368 1369 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1370 int gsc_idx = pdata->gsc_map[i].idx; 1371 exynos5_gsc_data_t &gsc = pdev->gsc[gsc_idx]; 1372 1373 // RGBX8888 surfaces are already in the right color order from the GPU, 1374 // RGB565 and YUV surfaces need the Gscaler to swap R & B 1375 int dst_format = HAL_PIXEL_FORMAT_BGRA_8888; 1376 if (exynos5_format_is_rgb(handle->format) && 1377 handle->format != HAL_PIXEL_FORMAT_RGB_565) 1378 dst_format = HAL_PIXEL_FORMAT_RGBX_8888; 1379 1380 hwc_rect_t sourceCrop = { 0, 0, 1381 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame) }; 1382 int err = exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1383 gsc_idx, dst_format, &sourceCrop); 1384 if (err < 0) { 1385 ALOGE("failed to configure gscaler %u for layer %u", 1386 gsc_idx, i); 1387 pdata->gsc_map[i].mode = exynos5_gsc_map_t::GSC_NONE; 1388 continue; 1389 } 1390 1391 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1392 private_handle_t *dst_handle = 1393 private_handle_t::dynamicCast(dst_buf); 1394 int fence = gsc.dst_cfg.releaseFenceFd; 1395 exynos5_config_handle(dst_handle, sourceCrop, 1396 layer.displayFrame, layer.blending, fence, config[i], 1397 pdev); 1398 } else { 1399 exynos5_config_overlay(&layer, config[i], pdev); 1400 } 1401 } 1402 if (i == 0 && config[i].blending != S3C_FB_BLENDING_NONE) { 1403 ALOGV("blending not supported on window 0; forcing BLENDING_NONE"); 1404 config[i].blending = S3C_FB_BLENDING_NONE; 1405 } 1406 1407 ALOGV("window %u configuration:", i); 1408 dump_config(config[i]); 1409 } 1410 1411 int ret = ioctl(pdev->fd, S3CFB_WIN_CONFIG, &win_data); 1412 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1413 if (config[i].fence_fd != -1) 1414 close(config[i].fence_fd); 1415 if (ret < 0) { 1416 ALOGE("ioctl S3CFB_WIN_CONFIG failed: %s", strerror(errno)); 1417 return ret; 1418 } 1419 1420 memcpy(pdev->last_config, &win_data.config, sizeof(win_data.config)); 1421 memcpy(pdev->last_gsc_map, pdata->gsc_map, sizeof(pdata->gsc_map)); 1422 pdev->last_fb_window = pdata->fb_window; 1423 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1424 int layer_idx = pdata->overlay_map[i]; 1425 if (layer_idx != -1) { 1426 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1427 pdev->last_handles[i] = layer.handle; 1428 } 1429 } 1430 1431 return win_data.fence; 1432 } 1433 1434 static int exynos5_clear_fimd(exynos5_hwc_composer_device_1_t *pdev) 1435 { 1436 struct s3c_fb_win_config_data win_data; 1437 memset(&win_data, 0, sizeof(win_data)); 1438 1439 int ret = ioctl(pdev->fd, S3CFB_WIN_CONFIG, &win_data); 1440 LOG_ALWAYS_FATAL_IF(ret < 0, 1441 "ioctl S3CFB_WIN_CONFIG failed to clear screen: %s", 1442 strerror(errno)); 1443 // the causes of an empty config failing are all unrecoverable 1444 1445 return win_data.fence; 1446 } 1447 1448 static int exynos5_set_fimd(exynos5_hwc_composer_device_1_t *pdev, 1449 hwc_display_contents_1_t* contents) 1450 { 1451 if (!contents->dpy || !contents->sur) 1452 return 0; 1453 1454 hwc_layer_1_t *fb_layer = NULL; 1455 int err = 0; 1456 1457 if (pdev->bufs.fb_window != NO_FB_NEEDED) { 1458 for (size_t i = 0; i < contents->numHwLayers; i++) { 1459 if (contents->hwLayers[i].compositionType == 1460 HWC_FRAMEBUFFER_TARGET) { 1461 pdev->bufs.overlay_map[pdev->bufs.fb_window] = i; 1462 fb_layer = &contents->hwLayers[i]; 1463 break; 1464 } 1465 } 1466 1467 if (CC_UNLIKELY(!fb_layer)) { 1468 ALOGE("framebuffer target expected, but not provided"); 1469 err = -EINVAL; 1470 } else { 1471 ALOGV("framebuffer target buffer:"); 1472 dump_layer(fb_layer); 1473 } 1474 } 1475 1476 int fence; 1477 if (!err) { 1478 fence = exynos5_post_fimd(pdev, contents); 1479 if (fence < 0) 1480 err = fence; 1481 } 1482 1483 if (err) 1484 fence = exynos5_clear_fimd(pdev); 1485 1486 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1487 if (pdev->bufs.overlay_map[i] != -1) { 1488 hwc_layer_1_t &layer = 1489 contents->hwLayers[pdev->bufs.overlay_map[i]]; 1490 int dup_fd = dup(fence); 1491 if (dup_fd < 0) 1492 ALOGW("release fence dup failed: %s", strerror(errno)); 1493 if (pdev->bufs.gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1494 int gsc_idx = pdev->bufs.gsc_map[i].idx; 1495 exynos5_gsc_data_t &gsc = pdev->gsc[gsc_idx]; 1496 gsc.dst_buf_fence[gsc.current_buf] = dup_fd; 1497 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1498 } else { 1499 layer.releaseFenceFd = dup_fd; 1500 } 1501 } 1502 } 1503 close(fence); 1504 1505 return err; 1506 } 1507 1508 static int exynos5_set_hdmi(exynos5_hwc_composer_device_1_t *pdev, 1509 hwc_display_contents_1_t* contents) 1510 { 1511 hwc_layer_1_t *fb_layer = NULL; 1512 hwc_layer_1_t *video_layer = NULL; 1513 1514 if (!pdev->hdmi_enabled) { 1515 for (size_t i = 0; i < contents->numHwLayers; i++) { 1516 hwc_layer_1_t &layer = contents->hwLayers[i]; 1517 if (layer.acquireFenceFd != -1) { 1518 close(layer.acquireFenceFd); 1519 layer.acquireFenceFd = -1; 1520 } 1521 } 1522 return 0; 1523 } 1524 1525 for (size_t i = 0; i < contents->numHwLayers; i++) { 1526 hwc_layer_1_t &layer = contents->hwLayers[i]; 1527 1528 if (layer.flags & HWC_SKIP_LAYER) { 1529 ALOGV("HDMI skipping layer %d", i); 1530 continue; 1531 } 1532 1533 if (layer.compositionType == HWC_OVERLAY) { 1534 if (!layer.handle) 1535 continue; 1536 1537 ALOGV("HDMI video layer:"); 1538 dump_layer(&layer); 1539 1540 exynos5_gsc_data_t &gsc = pdev->gsc[HDMI_GSC_IDX]; 1541 int ret = exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1, 1542 HAL_PIXEL_FORMAT_RGBX_8888, NULL); 1543 if (ret < 0) { 1544 ALOGE("failed to configure gscaler for video layer"); 1545 continue; 1546 } 1547 1548 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1549 private_handle_t *h = private_handle_t::dynamicCast(dst_buf); 1550 1551 int acquireFenceFd = gsc.dst_cfg.releaseFenceFd; 1552 int releaseFenceFd = -1; 1553 1554 hdmi_output(pdev, pdev->hdmi_layers[0], layer, h, acquireFenceFd, 1555 &releaseFenceFd); 1556 video_layer = &layer; 1557 1558 gsc.dst_buf_fence[gsc.current_buf] = releaseFenceFd; 1559 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1560 } 1561 1562 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 1563 if (!layer.handle) 1564 continue; 1565 1566 ALOGV("HDMI FB layer:"); 1567 dump_layer(&layer); 1568 1569 private_handle_t *h = private_handle_t::dynamicCast(layer.handle); 1570 hdmi_output(pdev, pdev->hdmi_layers[1], layer, h, layer.acquireFenceFd, 1571 &layer.releaseFenceFd); 1572 fb_layer = &layer; 1573 } 1574 } 1575 1576 if (!video_layer) { 1577 hdmi_disable_layer(pdev, pdev->hdmi_layers[0]); 1578 exynos5_cleanup_gsc_m2m(pdev, HDMI_GSC_IDX); 1579 } 1580 if (!fb_layer) 1581 hdmi_disable_layer(pdev, pdev->hdmi_layers[1]); 1582 1583 if (exynos_v4l2_s_ctrl(pdev->hdmi_layers[1].fd, V4L2_CID_TV_UPDATE, 1) < 0) { 1584 ALOGE("%s: s_ctrl(CID_TV_UPDATE) failed %d", __func__, errno); 1585 return -1; 1586 } 1587 1588 return 0; 1589 } 1590 1591 static int exynos5_set(struct hwc_composer_device_1 *dev, 1592 size_t numDisplays, hwc_display_contents_1_t** displays) 1593 { 1594 if (!numDisplays || !displays) 1595 return 0; 1596 1597 exynos5_hwc_composer_device_1_t *pdev = 1598 (exynos5_hwc_composer_device_1_t *)dev; 1599 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 1600 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 1601 int fimd_err = 0, hdmi_err = 0; 1602 1603 if (fimd_contents) 1604 fimd_err = exynos5_set_fimd(pdev, fimd_contents); 1605 1606 if (hdmi_contents) 1607 hdmi_err = exynos5_set_hdmi(pdev, hdmi_contents); 1608 1609 if (fimd_err) 1610 return fimd_err; 1611 1612 return hdmi_err; 1613 } 1614 1615 static void exynos5_registerProcs(struct hwc_composer_device_1* dev, 1616 hwc_procs_t const* procs) 1617 { 1618 struct exynos5_hwc_composer_device_1_t* pdev = 1619 (struct exynos5_hwc_composer_device_1_t*)dev; 1620 pdev->procs = procs; 1621 } 1622 1623 static int exynos5_query(struct hwc_composer_device_1* dev, int what, int *value) 1624 { 1625 struct exynos5_hwc_composer_device_1_t *pdev = 1626 (struct exynos5_hwc_composer_device_1_t *)dev; 1627 1628 switch (what) { 1629 case HWC_BACKGROUND_LAYER_SUPPORTED: 1630 // we support the background layer 1631 value[0] = 1; 1632 break; 1633 case HWC_VSYNC_PERIOD: 1634 // vsync period in nanosecond 1635 value[0] = pdev->vsync_period; 1636 break; 1637 default: 1638 // unsupported query 1639 return -EINVAL; 1640 } 1641 return 0; 1642 } 1643 1644 static int exynos5_eventControl(struct hwc_composer_device_1 *dev, int dpy, 1645 int event, int enabled) 1646 { 1647 struct exynos5_hwc_composer_device_1_t *pdev = 1648 (struct exynos5_hwc_composer_device_1_t *)dev; 1649 1650 switch (event) { 1651 case HWC_EVENT_VSYNC: 1652 __u32 val = !!enabled; 1653 int err = ioctl(pdev->fd, S3CFB_SET_VSYNC_INT, &val); 1654 if (err < 0) { 1655 ALOGE("vsync ioctl failed"); 1656 return -errno; 1657 } 1658 1659 return 0; 1660 } 1661 1662 return -EINVAL; 1663 } 1664 1665 static void handle_hdmi_uevent(struct exynos5_hwc_composer_device_1_t *pdev, 1666 const char *buff, int len) 1667 { 1668 const char *s = buff; 1669 s += strlen(s) + 1; 1670 1671 while (*s) { 1672 if (!strncmp(s, "SWITCH_STATE=", strlen("SWITCH_STATE="))) 1673 pdev->hdmi_hpd = atoi(s + strlen("SWITCH_STATE=")) == 1; 1674 1675 s += strlen(s) + 1; 1676 if (s - buff >= len) 1677 break; 1678 } 1679 1680 if (pdev->hdmi_hpd) { 1681 if (hdmi_get_config(pdev)) { 1682 ALOGE("Error reading HDMI configuration"); 1683 pdev->hdmi_hpd = false; 1684 return; 1685 } 1686 1687 pdev->hdmi_blanked = false; 1688 } 1689 1690 ALOGV("HDMI HPD changed to %s", pdev->hdmi_hpd ? "enabled" : "disabled"); 1691 if (pdev->hdmi_hpd) 1692 ALOGI("HDMI Resolution changed to %dx%d", pdev->hdmi_h, pdev->hdmi_w); 1693 1694 /* hwc_dev->procs is set right after the device is opened, but there is 1695 * still a race condition where a hotplug event might occur after the open 1696 * but before the procs are registered. */ 1697 if (pdev->procs) 1698 pdev->procs->hotplug(pdev->procs, HWC_DISPLAY_EXTERNAL, pdev->hdmi_hpd); 1699 } 1700 1701 static void handle_vsync_event(struct exynos5_hwc_composer_device_1_t *pdev) 1702 { 1703 if (!pdev->procs) 1704 return; 1705 1706 int err = lseek(pdev->vsync_fd, 0, SEEK_SET); 1707 if (err < 0) { 1708 ALOGE("error seeking to vsync timestamp: %s", strerror(errno)); 1709 return; 1710 } 1711 1712 char buf[4096]; 1713 err = read(pdev->vsync_fd, buf, sizeof(buf)); 1714 if (err < 0) { 1715 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1716 return; 1717 } 1718 buf[sizeof(buf) - 1] = '\0'; 1719 1720 errno = 0; 1721 uint64_t timestamp = strtoull(buf, NULL, 0); 1722 if (!errno) 1723 pdev->procs->vsync(pdev->procs, 0, timestamp); 1724 } 1725 1726 static void *hwc_vsync_thread(void *data) 1727 { 1728 struct exynos5_hwc_composer_device_1_t *pdev = 1729 (struct exynos5_hwc_composer_device_1_t *)data; 1730 char uevent_desc[4096]; 1731 memset(uevent_desc, 0, sizeof(uevent_desc)); 1732 1733 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); 1734 1735 uevent_init(); 1736 1737 char temp[4096]; 1738 int err = read(pdev->vsync_fd, temp, sizeof(temp)); 1739 if (err < 0) { 1740 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1741 return NULL; 1742 } 1743 1744 struct pollfd fds[2]; 1745 fds[0].fd = pdev->vsync_fd; 1746 fds[0].events = POLLPRI; 1747 fds[1].fd = uevent_get_fd(); 1748 fds[1].events = POLLIN; 1749 1750 while (true) { 1751 int err = poll(fds, 2, -1); 1752 1753 if (err > 0) { 1754 if (fds[0].revents & POLLPRI) { 1755 handle_vsync_event(pdev); 1756 } 1757 else if (fds[1].revents & POLLIN) { 1758 int len = uevent_next_event(uevent_desc, 1759 sizeof(uevent_desc) - 2); 1760 1761 bool hdmi = !strcmp(uevent_desc, 1762 "change@/devices/virtual/switch/hdmi"); 1763 if (hdmi) 1764 handle_hdmi_uevent(pdev, uevent_desc, len); 1765 } 1766 } 1767 else if (err == -1) { 1768 if (errno == EINTR) 1769 break; 1770 ALOGE("error in vsync thread: %s", strerror(errno)); 1771 } 1772 } 1773 1774 return NULL; 1775 } 1776 1777 static int exynos5_blank(struct hwc_composer_device_1 *dev, int disp, int blank) 1778 { 1779 struct exynos5_hwc_composer_device_1_t *pdev = 1780 (struct exynos5_hwc_composer_device_1_t *)dev; 1781 1782 switch (disp) { 1783 case HWC_DISPLAY_PRIMARY: { 1784 int fb_blank = blank ? FB_BLANK_POWERDOWN : FB_BLANK_UNBLANK; 1785 int err = ioctl(pdev->fd, FBIOBLANK, fb_blank); 1786 if (err < 0) { 1787 if (errno == EBUSY) 1788 ALOGI("%sblank ioctl failed (display already %sblanked)", 1789 blank ? "" : "un", blank ? "" : "un"); 1790 else 1791 ALOGE("%sblank ioctl failed: %s", blank ? "" : "un", 1792 strerror(errno)); 1793 return -errno; 1794 } 1795 break; 1796 } 1797 1798 case HWC_DISPLAY_EXTERNAL: 1799 if (pdev->hdmi_hpd) { 1800 if (blank && !pdev->hdmi_blanked) 1801 hdmi_disable(pdev); 1802 pdev->hdmi_blanked = !!blank; 1803 } 1804 break; 1805 1806 default: 1807 return -EINVAL; 1808 1809 } 1810 1811 return 0; 1812 } 1813 1814 static void exynos5_dump(hwc_composer_device_1* dev, char *buff, int buff_len) 1815 { 1816 if (buff_len <= 0) 1817 return; 1818 1819 struct exynos5_hwc_composer_device_1_t *pdev = 1820 (struct exynos5_hwc_composer_device_1_t *)dev; 1821 1822 android::String8 result; 1823 1824 result.appendFormat(" hdmi_enabled=%u\n", pdev->hdmi_enabled); 1825 if (pdev->hdmi_enabled) 1826 result.appendFormat(" w=%u, h=%u\n", pdev->hdmi_w, pdev->hdmi_h); 1827 result.append( 1828 " type | handle | color | blend | format | position | size | gsc \n" 1829 "----------+----------|----------+-------+--------+---------------+---------------------\n"); 1830 // 8_______ | 8_______ | 8_______ | 5____ | 6_____ | [5____,5____] | [5____,5____] | 3__ \n" 1831 1832 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1833 struct s3c_fb_win_config &config = pdev->last_config[i]; 1834 if (config.state == config.S3C_FB_WIN_STATE_DISABLED) { 1835 result.appendFormat(" %8s | %8s | %8s | %5s | %6s | %13s | %13s", 1836 "DISABLED", "-", "-", "-", "-", "-", "-"); 1837 } 1838 else { 1839 if (config.state == config.S3C_FB_WIN_STATE_COLOR) 1840 result.appendFormat(" %8s | %8s | %8x | %5s | %6s", "COLOR", 1841 "-", config.color, "-", "-"); 1842 else 1843 result.appendFormat(" %8s | %8x | %8s | %5x | %6x", 1844 pdev->last_fb_window == i ? "FB" : "OVERLAY", 1845 intptr_t(pdev->last_handles[i]), 1846 "-", config.blending, config.format); 1847 1848 result.appendFormat(" | [%5d,%5d] | [%5u,%5u]", config.x, config.y, 1849 config.w, config.h); 1850 } 1851 if (pdev->last_gsc_map[i].mode == exynos5_gsc_map_t::GSC_NONE) 1852 result.appendFormat(" | %3s", "-"); 1853 else 1854 result.appendFormat(" | %3d", 1855 AVAILABLE_GSC_UNITS[pdev->last_gsc_map[i].idx]); 1856 result.append("\n"); 1857 } 1858 1859 strlcpy(buff, result.string(), buff_len); 1860 } 1861 1862 static int exynos5_getDisplayConfigs(struct hwc_composer_device_1 *dev, 1863 int disp, uint32_t *configs, size_t *numConfigs) 1864 { 1865 struct exynos5_hwc_composer_device_1_t *pdev = 1866 (struct exynos5_hwc_composer_device_1_t *)dev; 1867 1868 if (*numConfigs == 0) 1869 return 0; 1870 1871 if (disp == HWC_DISPLAY_PRIMARY) { 1872 configs[0] = 0; 1873 *numConfigs = 1; 1874 return 0; 1875 } else if (disp == HWC_DISPLAY_EXTERNAL) { 1876 if (!pdev->hdmi_hpd) { 1877 return -EINVAL; 1878 } 1879 1880 int err = hdmi_get_config(pdev); 1881 if (err) { 1882 return -EINVAL; 1883 } 1884 1885 configs[0] = 0; 1886 *numConfigs = 1; 1887 return 0; 1888 } 1889 1890 return -EINVAL; 1891 } 1892 1893 static int32_t exynos5_fimd_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1894 const uint32_t attribute) 1895 { 1896 switch(attribute) { 1897 case HWC_DISPLAY_VSYNC_PERIOD: 1898 return pdev->vsync_period; 1899 1900 case HWC_DISPLAY_WIDTH: 1901 return pdev->xres; 1902 1903 case HWC_DISPLAY_HEIGHT: 1904 return pdev->yres; 1905 1906 case HWC_DISPLAY_DPI_X: 1907 return pdev->xdpi; 1908 1909 case HWC_DISPLAY_DPI_Y: 1910 return pdev->ydpi; 1911 1912 default: 1913 ALOGE("unknown display attribute %u", attribute); 1914 return -EINVAL; 1915 } 1916 } 1917 1918 static int32_t exynos5_hdmi_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1919 const uint32_t attribute) 1920 { 1921 switch(attribute) { 1922 case HWC_DISPLAY_VSYNC_PERIOD: 1923 return pdev->vsync_period; 1924 1925 case HWC_DISPLAY_WIDTH: 1926 return pdev->hdmi_w; 1927 1928 case HWC_DISPLAY_HEIGHT: 1929 return pdev->hdmi_h; 1930 1931 case HWC_DISPLAY_DPI_X: 1932 case HWC_DISPLAY_DPI_Y: 1933 return 0; // unknown 1934 1935 default: 1936 ALOGE("unknown display attribute %u", attribute); 1937 return -EINVAL; 1938 } 1939 } 1940 1941 static int exynos5_getDisplayAttributes(struct hwc_composer_device_1 *dev, 1942 int disp, uint32_t config, const uint32_t *attributes, int32_t *values) 1943 { 1944 struct exynos5_hwc_composer_device_1_t *pdev = 1945 (struct exynos5_hwc_composer_device_1_t *)dev; 1946 1947 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; i++) { 1948 if (disp == HWC_DISPLAY_PRIMARY) 1949 values[i] = exynos5_fimd_attribute(pdev, attributes[i]); 1950 else if (disp == HWC_DISPLAY_EXTERNAL) 1951 values[i] = exynos5_hdmi_attribute(pdev, attributes[i]); 1952 else { 1953 ALOGE("unknown display type %u", disp); 1954 return -EINVAL; 1955 } 1956 } 1957 1958 return 0; 1959 } 1960 1961 static int exynos5_close(hw_device_t* device); 1962 1963 static int exynos5_open(const struct hw_module_t *module, const char *name, 1964 struct hw_device_t **device) 1965 { 1966 int ret; 1967 int refreshRate; 1968 int sw_fd; 1969 1970 if (strcmp(name, HWC_HARDWARE_COMPOSER)) { 1971 return -EINVAL; 1972 } 1973 1974 struct exynos5_hwc_composer_device_1_t *dev; 1975 dev = (struct exynos5_hwc_composer_device_1_t *)malloc(sizeof(*dev)); 1976 memset(dev, 0, sizeof(*dev)); 1977 1978 if (hw_get_module(GRALLOC_HARDWARE_MODULE_ID, 1979 (const struct hw_module_t **)&dev->gralloc_module)) { 1980 ALOGE("failed to get gralloc hw module"); 1981 ret = -EINVAL; 1982 goto err_get_module; 1983 } 1984 1985 if (gralloc_open((const hw_module_t *)dev->gralloc_module, 1986 &dev->alloc_device)) { 1987 ALOGE("failed to open gralloc"); 1988 ret = -EINVAL; 1989 goto err_get_module; 1990 } 1991 1992 dev->fd = open("/dev/graphics/fb0", O_RDWR); 1993 if (dev->fd < 0) { 1994 ALOGE("failed to open framebuffer"); 1995 ret = dev->fd; 1996 goto err_open_fb; 1997 } 1998 1999 struct fb_var_screeninfo info; 2000 if (ioctl(dev->fd, FBIOGET_VSCREENINFO, &info) == -1) { 2001 ALOGE("FBIOGET_VSCREENINFO ioctl failed: %s", strerror(errno)); 2002 ret = -errno; 2003 goto err_ioctl; 2004 } 2005 2006 refreshRate = 1000000000000LLU / 2007 ( 2008 uint64_t( info.upper_margin + info.lower_margin + info.yres ) 2009 * ( info.left_margin + info.right_margin + info.xres ) 2010 * info.pixclock 2011 ); 2012 2013 if (refreshRate == 0) { 2014 ALOGW("invalid refresh rate, assuming 60 Hz"); 2015 refreshRate = 60; 2016 } 2017 2018 dev->xres = 2560; 2019 dev->yres = 1600; 2020 dev->xdpi = 1000 * (info.xres * 25.4f) / info.width; 2021 dev->ydpi = 1000 * (info.yres * 25.4f) / info.height; 2022 dev->vsync_period = 1000000000 / refreshRate; 2023 2024 ALOGV("using\n" 2025 "xres = %d px\n" 2026 "yres = %d px\n" 2027 "width = %d mm (%f dpi)\n" 2028 "height = %d mm (%f dpi)\n" 2029 "refresh rate = %d Hz\n", 2030 dev->xres, dev->yres, info.width, dev->xdpi / 1000.0, 2031 info.height, dev->ydpi / 1000.0, refreshRate); 2032 2033 for (size_t i = 0; i < NUM_GSC_UNITS; i++) 2034 for (size_t j = 0; j < NUM_GSC_DST_BUFS; j++) 2035 dev->gsc[i].dst_buf_fence[j] = -1; 2036 2037 dev->hdmi_mixer0 = open("/dev/v4l-subdev7", O_RDWR); 2038 if (dev->hdmi_mixer0 < 0) { 2039 ALOGE("failed to open hdmi mixer0 subdev"); 2040 ret = dev->hdmi_mixer0; 2041 goto err_ioctl; 2042 } 2043 2044 dev->hdmi_layers[0].id = 0; 2045 dev->hdmi_layers[0].fd = open("/dev/video16", O_RDWR); 2046 if (dev->hdmi_layers[0].fd < 0) { 2047 ALOGE("failed to open hdmi layer0 device"); 2048 ret = dev->hdmi_layers[0].fd; 2049 goto err_mixer0; 2050 } 2051 2052 dev->hdmi_layers[1].id = 1; 2053 dev->hdmi_layers[1].fd = open("/dev/video17", O_RDWR); 2054 if (dev->hdmi_layers[1].fd < 0) { 2055 ALOGE("failed to open hdmi layer1 device"); 2056 ret = dev->hdmi_layers[1].fd; 2057 goto err_hdmi0; 2058 } 2059 2060 dev->vsync_fd = open("/sys/devices/platform/exynos5-fb.1/vsync", O_RDONLY); 2061 if (dev->vsync_fd < 0) { 2062 ALOGE("failed to open vsync attribute"); 2063 ret = dev->vsync_fd; 2064 goto err_hdmi1; 2065 } 2066 2067 sw_fd = open("/sys/class/switch/hdmi/state", O_RDONLY); 2068 if (sw_fd) { 2069 char val; 2070 if (read(sw_fd, &val, 1) == 1 && val == '1') { 2071 dev->hdmi_hpd = true; 2072 if (hdmi_get_config(dev)) { 2073 ALOGE("Error reading HDMI configuration"); 2074 dev->hdmi_hpd = false; 2075 } 2076 } 2077 } 2078 2079 dev->base.common.tag = HARDWARE_DEVICE_TAG; 2080 dev->base.common.version = HWC_DEVICE_API_VERSION_1_1; 2081 dev->base.common.module = const_cast<hw_module_t *>(module); 2082 dev->base.common.close = exynos5_close; 2083 2084 dev->base.prepare = exynos5_prepare; 2085 dev->base.set = exynos5_set; 2086 dev->base.eventControl = exynos5_eventControl; 2087 dev->base.blank = exynos5_blank; 2088 dev->base.query = exynos5_query; 2089 dev->base.registerProcs = exynos5_registerProcs; 2090 dev->base.dump = exynos5_dump; 2091 dev->base.getDisplayConfigs = exynos5_getDisplayConfigs; 2092 dev->base.getDisplayAttributes = exynos5_getDisplayAttributes; 2093 2094 *device = &dev->base.common; 2095 2096 ret = pthread_create(&dev->vsync_thread, NULL, hwc_vsync_thread, dev); 2097 if (ret) { 2098 ALOGE("failed to start vsync thread: %s", strerror(ret)); 2099 ret = -ret; 2100 goto err_vsync; 2101 } 2102 2103 char value[PROPERTY_VALUE_MAX]; 2104 property_get("debug.hwc.force_gpu", value, "0"); 2105 dev->force_gpu = atoi(value); 2106 2107 return 0; 2108 2109 err_vsync: 2110 close(dev->vsync_fd); 2111 err_mixer0: 2112 close(dev->hdmi_mixer0); 2113 err_hdmi1: 2114 close(dev->hdmi_layers[0].fd); 2115 err_hdmi0: 2116 close(dev->hdmi_layers[1].fd); 2117 err_ioctl: 2118 close(dev->fd); 2119 err_open_fb: 2120 gralloc_close(dev->alloc_device); 2121 err_get_module: 2122 free(dev); 2123 return ret; 2124 } 2125 2126 static int exynos5_close(hw_device_t *device) 2127 { 2128 struct exynos5_hwc_composer_device_1_t *dev = 2129 (struct exynos5_hwc_composer_device_1_t *)device; 2130 pthread_kill(dev->vsync_thread, SIGTERM); 2131 pthread_join(dev->vsync_thread, NULL); 2132 for (size_t i = 0; i < NUM_GSC_UNITS; i++) 2133 exynos5_cleanup_gsc_m2m(dev, i); 2134 gralloc_close(dev->alloc_device); 2135 close(dev->vsync_fd); 2136 close(dev->hdmi_mixer0); 2137 close(dev->hdmi_layers[0].fd); 2138 close(dev->hdmi_layers[1].fd); 2139 close(dev->fd); 2140 return 0; 2141 } 2142 2143 static struct hw_module_methods_t exynos5_hwc_module_methods = { 2144 open: exynos5_open, 2145 }; 2146 2147 hwc_module_t HAL_MODULE_INFO_SYM = { 2148 common: { 2149 tag: HARDWARE_MODULE_TAG, 2150 module_api_version: HWC_MODULE_API_VERSION_0_1, 2151 hal_api_version: HARDWARE_HAL_API_VERSION, 2152 id: HWC_HARDWARE_MODULE_ID, 2153 name: "Samsung exynos5 hwcomposer module", 2154 author: "Google", 2155 methods: &exynos5_hwc_module_methods, 2156 } 2157 }; 2158
