Lines Matching refs:LRI
245 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
246 addKillFlag(*LRI);
247 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
249 PhysRegState[LRI->PhysReg] = regFree;
252 LiveVirtRegs.erase(LRI);
259 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
260 if (LRI != LiveVirtRegs.end())
261 killVirtReg(LRI);
269 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
270 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
271 spillVirtReg(MI, LRI);
276 LiveRegMap::iterator LRI) {
277 LiveReg &LR = *LRI;
278 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
287 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
288 int FI = getStackSpaceFor(LRI->VirtReg, RC);
297 LiveDbgValueMap[LRI->VirtReg];
327 killVirtReg(LRI);
503 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
504 assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
505 assignVirtToPhysReg(*LRI, PhysReg);
506 return LRI;
511 LiveRegMap::iterator LRI,
513 const unsigned VirtReg = LRI->VirtReg;
533 // That invalidates LRI, so run a new lookup for VirtReg.
544 assignVirtToPhysReg(*LRI, PhysReg);
545 return LRI;
560 assignVirtToPhysReg(*LRI, *I);
561 return LRI;
570 // That invalidates LRI, so run a new lookup for VirtReg.
586 LiveRegMap::iterator LRI;
588 tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
598 LRI = allocVirtReg(MI, LRI, Hint);
599 } else if (LRI->LastUse) {
602 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
603 addKillFlag(*LRI);
605 assert(LRI->PhysReg && "Register not assigned");
606 LRI->LastUse = MI;
607 LRI->LastOpNum = OpNum;
608 LRI->Dirty = true;
609 markRegUsedInInstr(LRI->PhysReg);
610 return LRI;
619 LiveRegMap::iterator LRI;
621 tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
624 LRI = allocVirtReg(MI, LRI, Hint);
628 << PrintReg(LRI->PhysReg, TRI) << "\n");
629 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
631 } else if (LRI->Dirty) {
656 assert(LRI->PhysReg && "Register not assigned");
657 LRI->LastUse = MI;
658 LRI->LastOpNum = OpNum;
659 markRegUsedInInstr(LRI->PhysReg);
660 return LRI;
739 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
740 unsigned PhysReg = LRI->PhysReg;
748 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
749 PartialDefs.push_back(LRI->PhysReg);
762 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
763 unsigned PhysReg = LRI->PhysReg;
850 LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
851 if (LRI != LiveVirtRegs.end())
852 setPhysReg(MI, i, LRI->PhysReg);
971 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
972 unsigned PhysReg = LRI->PhysReg;
975 killVirtReg(LRI);
1027 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
1028 unsigned PhysReg = LRI->PhysReg;
