Lines Matching refs:VirtReg
72 unsigned VirtReg; // Virtual register number.
78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
81 return TargetRegisterInfo::virtReg2Index(VirtReg);
113 // PhysRegState - One of the RegState enums, or a virtreg.
167 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
172 void killVirtReg(unsigned VirtReg);
174 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
181 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
183 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
184 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
190 unsigned VirtReg, unsigned Hint);
192 unsigned VirtReg, unsigned Hint);
201 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
203 int SS = StackSlotForVirtReg[VirtReg];
212 StackSlotForVirtReg[VirtReg] = FrameIdx;
244 /// killVirtReg - Mark virtreg as no longer available.
247 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
255 /// killVirtReg - Mark virtreg as no longer available.
256 void RAFast::killVirtReg(unsigned VirtReg) {
257 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
259 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
264 /// spillVirtReg - This method spills the value specified by VirtReg into the
266 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
267 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
269 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
278 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
287 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
288 int FI = getStackSpaceFor(LRI->VirtReg, RC);
297 LiveDbgValueMap[LRI->VirtReg];
334 // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
344 /// Check that the register is not used by a virtreg.
405 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
409 spillVirtReg(MI, VirtReg);
421 switch (unsigned VirtReg = PhysRegState[Alias]) {
425 spillVirtReg(MI, VirtReg);
448 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
454 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
458 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
459 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
469 switch (unsigned VirtReg = PhysRegState[Alias]) {
478 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
479 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
490 /// that PhysReg is the proper container for VirtReg now. The physical
494 DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
496 PhysRegState[PhysReg] = LR.VirtReg;
502 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
503 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
504 assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
509 /// allocVirtReg - Allocate a physical register for VirtReg.
513 const unsigned VirtReg = LRI->VirtReg;
515 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
518 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
533 // That invalidates LRI, so run a new lookup for VirtReg.
534 return assignVirtToPhysReg(VirtReg, Hint);
549 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
570 // That invalidates LRI, so run a new lookup for VirtReg.
571 return assignVirtToPhysReg(VirtReg, BestReg);
577 return assignVirtToPhysReg(VirtReg, *AO.begin());
580 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
583 unsigned VirtReg, unsigned Hint) {
584 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
588 tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
592 MRI->hasOneNonDBGUse(VirtReg)) {
593 const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
601 // instruction defining VirtReg multiple times.
613 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
616 unsigned VirtReg, unsigned Hint) {
617 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
621 tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
625 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
626 int FrameIndex = getStackSpaceFor(VirtReg, RC);
627 DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
820 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
832 assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) &&
836 assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");
904 // Find the end of the virtreg operands
964 // Allocate virtreg uses.