| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.h | 26 const ARMSubtarget &STI;
29 explicit ARMFrameLowering(const ARMSubtarget &sti)
30 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
31 STI(sti) {
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| ARMHazardRecognizer.h | 33 const ARMSubtarget &STI;
42 const ARMSubtarget &sti,
45 TRI(tri), STI(sti), LastMI(0) {}
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| ARMBaseRegisterInfo.h | 78 const ARMSubtarget &STI;
90 const ARMSubtarget &STI);
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| MLxExpansionPass.cpp | 383 const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
384 isLikeA9 = STI->isLikeA9() || STI->isSwift();
385 isSwift = STI->isSwift();
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| ARMExpandPseudoInsts.cpp | 44 const ARMSubtarget *STI;
623 if (!STI->hasV6T2Ops() &&
[all...] |
| Thumb2SizeReduction.cpp | 140 const ARMSubtarget *STI;
231 if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
611 STI->avoidMOVsShifterOperand())
729 STI->avoidMOVsShifterOperand())
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.h | 21 const HexagonSubtarget &STI;
25 explicit HexagonFrameLowering(const HexagonSubtarget &sti)
26 : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) {
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| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.h | 26 const MSP430Subtarget &STI;
29 explicit MSP430FrameLowering(const MSP430Subtarget &sti)
30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) {
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| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.h | 26 const MipsSubtarget &STI;
29 explicit MipsFrameLowering(const MipsSubtarget &sti)
30 : TargetFrameLowering(StackGrowsDown, sti.hasMips64() ? 16 : 8, 0,
31 sti.hasMips64() ? 16 : 8), STI(sti) {}
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| MipsSEInstrInfo.cpp | 259 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
261 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
262 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
279 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
281 unsigned Size = STI.isABI_N64() ? 64 : 32;
282 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
283 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
284 const TargetRegisterClass *RC = STI.isABI_N64() ?
368 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
369 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.h | 25 const MBlazeSubtarget &STI;
28 explicit MBlazeFrameLowering(const MBlazeSubtarget &sti)
29 : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 4, 0), STI(sti) {
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| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.h | 27 const X86Subtarget &STI;
29 explicit X86FrameLowering(const X86TargetMachine &tm, const X86Subtarget &sti)
31 sti.getStackAlignment(),
32 (sti.is64Bit() ? -8 : -4)),
33 TM(tm), STI(sti) {
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| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.h | 40 const AArch64Subtarget &STI;
43 explicit AArch64FrameLowering(const AArch64Subtarget &sti)
45 STI(sti) {
|
| /external/llvm/include/llvm/MC/ |
| MCDisassembler.h | 56 MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0),
58 STI(STI), CommentStream(0) {}
100 const MCSubtargetInfo &STI;
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| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 37 const TargetSubtargetInfo *STI;
44 TargetSchedModel(): STI(0), TII(0) {}
51 void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
110 return STI->getWriteProcResBegin(SC);
113 return STI->getWriteProcResEnd(SC);
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| /external/llvm/lib/CodeGen/ |
| LLVMTargetMachine.cpp | 164 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
172 Context->getRegisterInfo(), STI);
178 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
179 MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI, STI,
199 STI, *Context);
271 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
273 STI, *Ctx);
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| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 61 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU,
63 if (!STI)
72 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI);
80 *MAI, *MII, *MRI, *STI);
87 STI, MII, Ctx, DisAsm, IP);
212 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
216 AsmPrinterVariant, *MAI, *MII, *MRI, *STI);
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 29 const MCSubtargetInfo* STI;
33 STI(AArch64_MC::createAArch64MCSubtargetInfo(TT, "", ""))
38 delete STI;
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 35 const MCSubtargetInfo &STI;
39 PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
41 : STI(sti), TT(STI.getTargetTriple()) {
47 return (STI.getFeatureBits() & PPC::Feature64Bit) != 0;
108 const MCSubtargetInfo &STI,
110 return new PPCMCCodeEmitter(MCII, STI, Ctx);
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 42 const MCSubtargetInfo &STI;
53 const MCSubtargetInfo &sti, MCContext &ctx)
54 : MCII(mcii), MRI(mri), STI(sti), Ctx(ctx) { }
71 const MCSubtargetInfo &STI,
73 return new SIMCCodeEmitter(MCII, MRI, STI, Ctx);
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| R600MCCodeEmitter.cpp | 45 const MCSubtargetInfo &STI;
51 const MCSubtargetInfo &sti, MCContext &ctx)
52 : MCII(mcii), MRI(mri), STI(sti), Ctx(ctx) { }
136 const MCSubtargetInfo &STI,
138 return new R600MCCodeEmitter(MCII, MRI, STI, Ctx);
207 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
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| /frameworks/compile/mclinker/lib/CodeGen/ |
| MCLDTargetMachine.cpp | 281 const MCSubtargetInfo &STI = getTM().getSubtarget<MCSubtargetInfo>();
286 Context->getRegisterInfo(), STI);
291 MCE = getTarget().get()->createMCCodeEmitter(MII, MRI, STI, *Context);
326 const MCSubtargetInfo &STI = getTM().getSubtarget<MCSubtargetInfo>();
328 getTarget().get()->createMCCodeEmitter(MII, MRI, STI, *Context);
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 43 const MCSubtargetInfo* STI;
47 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
51 delete STI;
57 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
|
| ARMMCCodeEmitter.cpp | 41 const MCSubtargetInfo &STI;
45 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
47 : MCII(mcii), STI(sti), CTX(ctx) {
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
60 Triple TT(STI.getTargetTriple());
342 const MCSubtargetInfo &STI,
344 return new ARMMCCodeEmitter(MCII, STI, Ctx);
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 35 const MCSubtargetInfo &STI;
38 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
40 : MCII(mcii), STI(sti), Ctx(ctx) {
47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
52 return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
144 const MCSubtargetInfo &STI,
146 return new X86MCCodeEmitter(MCII, STI, Ctx);
[all...] |
