1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsSEInstrInfo.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MipsMachineFunction.h" 17 #include "MipsTargetMachine.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/TargetRegistry.h" 23 24 using namespace llvm; 25 26 MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm) 27 : MipsInstrInfo(tm, 28 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J), 29 RI(*tm.getSubtargetImpl(), *this), 30 IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {} 31 32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { 33 return RI; 34 } 35 36 /// isLoadFromStackSlot - If the specified machine instruction is a direct 37 /// load from a stack slot, return the virtual or physical register number of 38 /// the destination along with the FrameIndex of the loaded stack slot. If 39 /// not, return 0. This predicate must return 0 if the instruction has 40 /// any side effects other than loading from the stack slot. 41 unsigned MipsSEInstrInfo:: 42 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const 43 { 44 unsigned Opc = MI->getOpcode(); 45 46 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) || 47 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || 48 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) || 49 (Opc == Mips::LDC164_P8)) { 50 if ((MI->getOperand(1).isFI()) && // is a stack slot 51 (MI->getOperand(2).isImm()) && // the imm is zero 52 (isZeroImm(MI->getOperand(2)))) { 53 FrameIndex = MI->getOperand(1).getIndex(); 54 return MI->getOperand(0).getReg(); 55 } 56 } 57 58 return 0; 59 } 60 61 /// isStoreToStackSlot - If the specified machine instruction is a direct 62 /// store to a stack slot, return the virtual or physical register number of 63 /// the source reg along with the FrameIndex of the loaded stack slot. If 64 /// not, return 0. This predicate must return 0 if the instruction has 65 /// any side effects other than storing to the stack slot. 66 unsigned MipsSEInstrInfo:: 67 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const 68 { 69 unsigned Opc = MI->getOpcode(); 70 71 if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) || 72 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) || 73 (Opc == Mips::SDC1) || (Opc == Mips::SDC164) || 74 (Opc == Mips::SDC164_P8)) { 75 if ((MI->getOperand(1).isFI()) && // is a stack slot 76 (MI->getOperand(2).isImm()) && // the imm is zero 77 (isZeroImm(MI->getOperand(2)))) { 78 FrameIndex = MI->getOperand(1).getIndex(); 79 return MI->getOperand(0).getReg(); 80 } 81 } 82 return 0; 83 } 84 85 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 86 MachineBasicBlock::iterator I, DebugLoc DL, 87 unsigned DestReg, unsigned SrcReg, 88 bool KillSrc) const { 89 unsigned Opc = 0, ZeroReg = 0; 90 91 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg. 92 if (Mips::CPURegsRegClass.contains(SrcReg)) 93 Opc = Mips::OR, ZeroReg = Mips::ZERO; 94 else if (Mips::CCRRegClass.contains(SrcReg)) 95 Opc = Mips::CFC1; 96 else if (Mips::FGR32RegClass.contains(SrcReg)) 97 Opc = Mips::MFC1; 98 else if (SrcReg == Mips::HI) 99 Opc = Mips::MFHI, SrcReg = 0; 100 else if (SrcReg == Mips::LO) 101 Opc = Mips::MFLO, SrcReg = 0; 102 } 103 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg. 104 if (Mips::CCRRegClass.contains(DestReg)) 105 Opc = Mips::CTC1; 106 else if (Mips::FGR32RegClass.contains(DestReg)) 107 Opc = Mips::MTC1; 108 else if (DestReg == Mips::HI) 109 Opc = Mips::MTHI, DestReg = 0; 110 else if (DestReg == Mips::LO) 111 Opc = Mips::MTLO, DestReg = 0; 112 } 113 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 114 Opc = Mips::FMOV_S; 115 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) 116 Opc = Mips::FMOV_D32; 117 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) 118 Opc = Mips::FMOV_D64; 119 else if (Mips::CCRRegClass.contains(DestReg, SrcReg)) 120 Opc = Mips::MOVCCRToCCR; 121 else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg. 122 if (Mips::CPU64RegsRegClass.contains(SrcReg)) 123 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; 124 else if (SrcReg == Mips::HI64) 125 Opc = Mips::MFHI64, SrcReg = 0; 126 else if (SrcReg == Mips::LO64) 127 Opc = Mips::MFLO64, SrcReg = 0; 128 else if (Mips::FGR64RegClass.contains(SrcReg)) 129 Opc = Mips::DMFC1; 130 } 131 else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 132 if (DestReg == Mips::HI64) 133 Opc = Mips::MTHI64, DestReg = 0; 134 else if (DestReg == Mips::LO64) 135 Opc = Mips::MTLO64, DestReg = 0; 136 else if (Mips::FGR64RegClass.contains(DestReg)) 137 Opc = Mips::DMTC1; 138 } 139 140 assert(Opc && "Cannot copy registers"); 141 142 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 143 144 if (DestReg) 145 MIB.addReg(DestReg, RegState::Define); 146 147 if (SrcReg) 148 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 149 150 if (ZeroReg) 151 MIB.addReg(ZeroReg); 152 } 153 154 void MipsSEInstrInfo:: 155 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 156 unsigned SrcReg, bool isKill, int FI, 157 const TargetRegisterClass *RC, 158 const TargetRegisterInfo *TRI) const { 159 DebugLoc DL; 160 if (I != MBB.end()) DL = I->getDebugLoc(); 161 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 162 163 unsigned Opc = 0; 164 165 if (Mips::CPURegsRegClass.hasSubClassEq(RC)) 166 Opc = IsN64 ? Mips::SW_P8 : Mips::SW; 167 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC)) 168 Opc = IsN64 ? Mips::SD_P8 : Mips::SD; 169 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 170 Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1; 171 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 172 Opc = Mips::SDC1; 173 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 174 Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164; 175 176 assert(Opc && "Register class not handled!"); 177 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 178 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 179 } 180 181 void MipsSEInstrInfo:: 182 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 183 unsigned DestReg, int FI, 184 const TargetRegisterClass *RC, 185 const TargetRegisterInfo *TRI) const 186 { 187 DebugLoc DL; 188 if (I != MBB.end()) DL = I->getDebugLoc(); 189 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 190 unsigned Opc = 0; 191 192 if (Mips::CPURegsRegClass.hasSubClassEq(RC)) 193 Opc = IsN64 ? Mips::LW_P8 : Mips::LW; 194 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC)) 195 Opc = IsN64 ? Mips::LD_P8 : Mips::LD; 196 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 197 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1; 198 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 199 Opc = Mips::LDC1; 200 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 201 Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164; 202 203 assert(Opc && "Register class not handled!"); 204 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0) 205 .addMemOperand(MMO); 206 } 207 208 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 209 MachineBasicBlock &MBB = *MI->getParent(); 210 211 switch(MI->getDesc().getOpcode()) { 212 default: 213 return false; 214 case Mips::RetRA: 215 ExpandRetRA(MBB, MI, Mips::RET); 216 break; 217 case Mips::BuildPairF64: 218 ExpandBuildPairF64(MBB, MI); 219 break; 220 case Mips::ExtractElementF64: 221 ExpandExtractElementF64(MBB, MI); 222 break; 223 case Mips::MIPSeh_return32: 224 case Mips::MIPSeh_return64: 225 ExpandEhReturn(MBB, MI); 226 break; 227 } 228 229 MBB.erase(MI); 230 return true; 231 } 232 233 /// GetOppositeBranchOpc - Return the inverse of the specified 234 /// opcode, e.g. turning BEQ to BNE. 235 unsigned MipsSEInstrInfo::GetOppositeBranchOpc(unsigned Opc) const { 236 switch (Opc) { 237 default: llvm_unreachable("Illegal opcode!"); 238 case Mips::BEQ: return Mips::BNE; 239 case Mips::BNE: return Mips::BEQ; 240 case Mips::BGTZ: return Mips::BLEZ; 241 case Mips::BGEZ: return Mips::BLTZ; 242 case Mips::BLTZ: return Mips::BGEZ; 243 case Mips::BLEZ: return Mips::BGTZ; 244 case Mips::BEQ64: return Mips::BNE64; 245 case Mips::BNE64: return Mips::BEQ64; 246 case Mips::BGTZ64: return Mips::BLEZ64; 247 case Mips::BGEZ64: return Mips::BLTZ64; 248 case Mips::BLTZ64: return Mips::BGEZ64; 249 case Mips::BLEZ64: return Mips::BGTZ64; 250 case Mips::BC1T: return Mips::BC1F; 251 case Mips::BC1F: return Mips::BC1T; 252 } 253 } 254 255 /// Adjust SP by Amount bytes. 256 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 257 MachineBasicBlock &MBB, 258 MachineBasicBlock::iterator I) const { 259 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); 260 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 261 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 262 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 263 264 if (isInt<16>(Amount))// addi sp, sp, amount 265 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 266 else { // Expand immediate that doesn't fit in 16-bit. 267 unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0); 268 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); 269 } 270 } 271 272 /// This function generates the sequence of instructions needed to get the 273 /// result of adding register REG and immediate IMM. 274 unsigned 275 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 276 MachineBasicBlock::iterator II, DebugLoc DL, 277 unsigned *NewImm) const { 278 MipsAnalyzeImmediate AnalyzeImm; 279 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); 280 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 281 unsigned Size = STI.isABI_N64() ? 64 : 32; 282 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; 283 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 284 const TargetRegisterClass *RC = STI.isABI_N64() ? 285 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass; 286 bool LastInstrIsADDiu = NewImm; 287 288 const MipsAnalyzeImmediate::InstSeq &Seq = 289 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu); 290 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 291 292 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1))); 293 294 // The first instruction can be a LUi, which is different from other 295 // instructions (ADDiu, ORI and SLL) in that it does not have a register 296 // operand. 297 unsigned Reg = RegInfo.createVirtualRegister(RC); 298 299 if (Inst->Opc == LUi) 300 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); 301 else 302 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 303 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 304 305 // Build the remaining instructions in Seq. 306 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst) 307 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 308 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 309 310 if (LastInstrIsADDiu) 311 *NewImm = Inst->ImmOpnd; 312 313 return Reg; 314 } 315 316 unsigned MipsSEInstrInfo::GetAnalyzableBrOpc(unsigned Opc) const { 317 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || 318 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || 319 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || 320 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || 321 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || 322 Opc == Mips::J) ? 323 Opc : 0; 324 } 325 326 void MipsSEInstrInfo::ExpandRetRA(MachineBasicBlock &MBB, 327 MachineBasicBlock::iterator I, 328 unsigned Opc) const { 329 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA); 330 } 331 332 void MipsSEInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB, 333 MachineBasicBlock::iterator I) const { 334 unsigned DstReg = I->getOperand(0).getReg(); 335 unsigned SrcReg = I->getOperand(1).getReg(); 336 unsigned N = I->getOperand(2).getImm(); 337 const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1); 338 DebugLoc dl = I->getDebugLoc(); 339 340 assert(N < 2 && "Invalid immediate"); 341 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven; 342 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); 343 344 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg); 345 } 346 347 void MipsSEInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB, 348 MachineBasicBlock::iterator I) const { 349 unsigned DstReg = I->getOperand(0).getReg(); 350 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); 351 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); 352 DebugLoc dl = I->getDebugLoc(); 353 const TargetRegisterInfo &TRI = getRegisterInfo(); 354 355 // mtc1 Lo, $fp 356 // mtc1 Hi, $fp + 1 357 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven)) 358 .addReg(LoReg); 359 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd)) 360 .addReg(HiReg); 361 } 362 363 void MipsSEInstrInfo::ExpandEhReturn(MachineBasicBlock &MBB, 364 MachineBasicBlock::iterator I) const { 365 // This pseudo instruction is generated as part of the lowering of 366 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and 367 // indirect jump to TargetReg 368 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); 369 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 370 unsigned OR = STI.isABI_N64() ? Mips::OR64 : Mips::OR; 371 unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR; 372 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 373 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA; 374 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 375 unsigned OffsetReg = I->getOperand(0).getReg(); 376 unsigned TargetReg = I->getOperand(1).getReg(); 377 378 // or $ra, $v0, $zero 379 // addu $sp, $sp, $v1 380 // jr $ra 381 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA) 382 .addReg(TargetReg).addReg(ZERO); 383 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP) 384 .addReg(SP).addReg(OffsetReg); 385 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA); 386 } 387 388 const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) { 389 return new MipsSEInstrInfo(TM); 390 } 391
