Home | History | Annotate | Download | only in CodeGen 
      1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the VirtRegMap class.
     11 //
     12 // It also contains implementations of the Spiller interface, which, given a
     13 // virtual register map and a machine function, eliminates all virtual
     14 // references by replacing them with physical register references - adding spill
     15 // code as necessary.
     16 //
     17 //===----------------------------------------------------------------------===//
     18 
     19 #define DEBUG_TYPE "regalloc"
     20 #include "llvm/CodeGen/VirtRegMap.h"
     21 #include "LiveDebugVariables.h"
     22 #include "llvm/ADT/STLExtras.h"
     23 #include "llvm/ADT/Statistic.h"
     24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
     25 #include "llvm/CodeGen/LiveStackAnalysis.h"
     26 #include "llvm/CodeGen/MachineFrameInfo.h"
     27 #include "llvm/CodeGen/MachineFunction.h"
     28 #include "llvm/CodeGen/MachineInstrBuilder.h"
     29 #include "llvm/CodeGen/MachineRegisterInfo.h"
     30 #include "llvm/CodeGen/Passes.h"
     31 #include "llvm/Support/CommandLine.h"
     32 #include "llvm/Support/Compiler.h"
     33 #include "llvm/Support/Debug.h"
     34 #include "llvm/Support/raw_ostream.h"
     35 #include "llvm/Target/TargetInstrInfo.h"
     36 #include "llvm/Target/TargetMachine.h"
     37 #include "llvm/Target/TargetRegisterInfo.h"
     38 #include <algorithm>
     39 using namespace llvm;
     40 
     41 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
     42 STATISTIC(NumIdCopies,   "Number of identity moves eliminated after rewriting");
     43 
     44 //===----------------------------------------------------------------------===//
     45 //  VirtRegMap implementation
     46 //===----------------------------------------------------------------------===//
     47 
     48 char VirtRegMap::ID = 0;
     49 
     50 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
     51 
     52 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
     53   MRI = &mf.getRegInfo();
     54   TII = mf.getTarget().getInstrInfo();
     55   TRI = mf.getTarget().getRegisterInfo();
     56   MF = &mf;
     57 
     58   Virt2PhysMap.clear();
     59   Virt2StackSlotMap.clear();
     60   Virt2SplitMap.clear();
     61 
     62   grow();
     63   return false;
     64 }
     65 
     66 void VirtRegMap::grow() {
     67   unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
     68   Virt2PhysMap.resize(NumRegs);
     69   Virt2StackSlotMap.resize(NumRegs);
     70   Virt2SplitMap.resize(NumRegs);
     71 }
     72 
     73 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
     74   int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
     75                                                       RC->getAlignment());
     76   ++NumSpillSlots;
     77   return SS;
     78 }
     79 
     80 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
     81   unsigned Hint = MRI->getSimpleHint(VirtReg);
     82   if (!Hint)
     83     return 0;
     84   if (TargetRegisterInfo::isVirtualRegister(Hint))
     85     Hint = getPhys(Hint);
     86   return getPhys(VirtReg) == Hint;
     87 }
     88 
     89 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
     90   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
     91   if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
     92     return true;
     93   if (TargetRegisterInfo::isVirtualRegister(Hint.second))
     94     return hasPhys(Hint.second);
     95   return false;
     96 }
     97 
     98 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
     99   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
    100   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
    101          "attempt to assign stack slot to already spilled register");
    102   const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
    103   return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
    104 }
    105 
    106 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
    107   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
    108   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
    109          "attempt to assign stack slot to already spilled register");
    110   assert((SS >= 0 ||
    111           (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
    112          "illegal fixed frame index");
    113   Virt2StackSlotMap[virtReg] = SS;
    114 }
    115 
    116 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
    117   OS << "********** REGISTER MAP **********\n";
    118   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
    119     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
    120     if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
    121       OS << '[' << PrintReg(Reg, TRI) << " -> "
    122          << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
    123          << MRI->getRegClass(Reg)->getName() << "\n";
    124     }
    125   }
    126 
    127   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
    128     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
    129     if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
    130       OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
    131          << "] " << MRI->getRegClass(Reg)->getName() << "\n";
    132     }
    133   }
    134   OS << '\n';
    135 }
    136 
    137 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
    138 void VirtRegMap::dump() const {
    139   print(dbgs());
    140 }
    141 #endif
    142 
    143 //===----------------------------------------------------------------------===//
    144 //                              VirtRegRewriter
    145 //===----------------------------------------------------------------------===//
    146 //
    147 // The VirtRegRewriter is the last of the register allocator passes.
    148 // It rewrites virtual registers to physical registers as specified in the
    149 // VirtRegMap analysis. It also updates live-in information on basic blocks
    150 // according to LiveIntervals.
    151 //
    152 namespace {
    153 class VirtRegRewriter : public MachineFunctionPass {
    154   MachineFunction *MF;
    155   const TargetMachine *TM;
    156   const TargetRegisterInfo *TRI;
    157   const TargetInstrInfo *TII;
    158   MachineRegisterInfo *MRI;
    159   SlotIndexes *Indexes;
    160   LiveIntervals *LIS;
    161   VirtRegMap *VRM;
    162 
    163   void rewrite();
    164   void addMBBLiveIns();
    165 public:
    166   static char ID;
    167   VirtRegRewriter() : MachineFunctionPass(ID) {}
    168 
    169   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
    170 
    171   virtual bool runOnMachineFunction(MachineFunction&);
    172 };
    173 } // end anonymous namespace
    174 
    175 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
    176 
    177 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
    178                       "Virtual Register Rewriter", false, false)
    179 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
    180 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
    181 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
    182 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
    183 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
    184 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
    185                     "Virtual Register Rewriter", false, false)
    186 
    187 char VirtRegRewriter::ID = 0;
    188 
    189 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
    190   AU.setPreservesCFG();
    191   AU.addRequired<LiveIntervals>();
    192   AU.addRequired<SlotIndexes>();
    193   AU.addPreserved<SlotIndexes>();
    194   AU.addRequired<LiveDebugVariables>();
    195   AU.addRequired<LiveStacks>();
    196   AU.addPreserved<LiveStacks>();
    197   AU.addRequired<VirtRegMap>();
    198   MachineFunctionPass::getAnalysisUsage(AU);
    199 }
    200 
    201 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
    202   MF = &fn;
    203   TM = &MF->getTarget();
    204   TRI = TM->getRegisterInfo();
    205   TII = TM->getInstrInfo();
    206   MRI = &MF->getRegInfo();
    207   Indexes = &getAnalysis<SlotIndexes>();
    208   LIS = &getAnalysis<LiveIntervals>();
    209   VRM = &getAnalysis<VirtRegMap>();
    210   DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
    211                << "********** Function: "
    212                << MF->getName() << '\n');
    213   DEBUG(VRM->dump());
    214 
    215   // Add kill flags while we still have virtual registers.
    216   LIS->addKillFlags(VRM);
    217 
    218   // Live-in lists on basic blocks are required for physregs.
    219   addMBBLiveIns();
    220 
    221   // Rewrite virtual registers.
    222   rewrite();
    223 
    224   // Write out new DBG_VALUE instructions.
    225   getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
    226 
    227   // All machine operands and other references to virtual registers have been
    228   // replaced. Remove the virtual registers and release all the transient data.
    229   VRM->clearAllVirt();
    230   MRI->clearVirtRegs();
    231   return true;
    232 }
    233 
    234 // Compute MBB live-in lists from virtual register live ranges and their
    235 // assignments.
    236 void VirtRegRewriter::addMBBLiveIns() {
    237   SmallVector<MachineBasicBlock*, 16> LiveIn;
    238   for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
    239     unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
    240     if (MRI->reg_nodbg_empty(VirtReg))
    241       continue;
    242     LiveInterval &LI = LIS->getInterval(VirtReg);
    243     if (LI.empty() || LIS->intervalIsInOneMBB(LI))
    244       continue;
    245     // This is a virtual register that is live across basic blocks. Its
    246     // assigned PhysReg must be marked as live-in to those blocks.
    247     unsigned PhysReg = VRM->getPhys(VirtReg);
    248     assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
    249 
    250     // Scan the segments of LI.
    251     for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I != E;
    252          ++I) {
    253       if (!Indexes->findLiveInMBBs(I->start, I->end, LiveIn))
    254         continue;
    255       for (unsigned i = 0, e = LiveIn.size(); i != e; ++i)
    256         if (!LiveIn[i]->isLiveIn(PhysReg))
    257           LiveIn[i]->addLiveIn(PhysReg);
    258       LiveIn.clear();
    259     }
    260   }
    261 }
    262 
    263 void VirtRegRewriter::rewrite() {
    264   SmallVector<unsigned, 8> SuperDeads;
    265   SmallVector<unsigned, 8> SuperDefs;
    266   SmallVector<unsigned, 8> SuperKills;
    267 
    268   for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
    269        MBBI != MBBE; ++MBBI) {
    270     DEBUG(MBBI->print(dbgs(), Indexes));
    271     for (MachineBasicBlock::instr_iterator
    272            MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
    273       MachineInstr *MI = MII;
    274       ++MII;
    275 
    276       for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
    277            MOE = MI->operands_end(); MOI != MOE; ++MOI) {
    278         MachineOperand &MO = *MOI;
    279 
    280         // Make sure MRI knows about registers clobbered by regmasks.
    281         if (MO.isRegMask())
    282           MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
    283 
    284         if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
    285           continue;
    286         unsigned VirtReg = MO.getReg();
    287         unsigned PhysReg = VRM->getPhys(VirtReg);
    288         assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
    289                "Instruction uses unmapped VirtReg");
    290         assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
    291 
    292         // Preserve semantics of sub-register operands.
    293         if (MO.getSubReg()) {
    294           // A virtual register kill refers to the whole register, so we may
    295           // have to add <imp-use,kill> operands for the super-register.  A
    296           // partial redef always kills and redefines the super-register.
    297           if (MO.readsReg() && (MO.isDef() || MO.isKill()))
    298             SuperKills.push_back(PhysReg);
    299 
    300           if (MO.isDef()) {
    301             // The <def,undef> flag only makes sense for sub-register defs, and
    302             // we are substituting a full physreg.  An <imp-use,kill> operand
    303             // from the SuperKills list will represent the partial read of the
    304             // super-register.
    305             MO.setIsUndef(false);
    306 
    307             // Also add implicit defs for the super-register.
    308             if (MO.isDead())
    309               SuperDeads.push_back(PhysReg);
    310             else
    311               SuperDefs.push_back(PhysReg);
    312           }
    313 
    314           // PhysReg operands cannot have subregister indexes.
    315           PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
    316           assert(PhysReg && "Invalid SubReg for physical register");
    317           MO.setSubReg(0);
    318         }
    319         // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
    320         // we need the inlining here.
    321         MO.setReg(PhysReg);
    322       }
    323 
    324       // Add any missing super-register kills after rewriting the whole
    325       // instruction.
    326       while (!SuperKills.empty())
    327         MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
    328 
    329       while (!SuperDeads.empty())
    330         MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
    331 
    332       while (!SuperDefs.empty())
    333         MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
    334 
    335       DEBUG(dbgs() << "> " << *MI);
    336 
    337       // Finally, remove any identity copies.
    338       if (MI->isIdentityCopy()) {
    339         ++NumIdCopies;
    340         if (MI->getNumOperands() == 2) {
    341           DEBUG(dbgs() << "Deleting identity copy.\n");
    342           if (Indexes)
    343             Indexes->removeMachineInstrFromMaps(MI);
    344           // It's safe to erase MI because MII has already been incremented.
    345           MI->eraseFromParent();
    346         } else {
    347           // Transform identity copy to a KILL to deal with subregisters.
    348           MI->setDesc(TII->get(TargetOpcode::KILL));
    349           DEBUG(dbgs() << "Identity copy: " << *MI);
    350         }
    351       }
    352     }
    353   }
    354 
    355   // Tell MRI about physical registers in use.
    356   for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
    357     if (!MRI->reg_nodbg_empty(Reg))
    358       MRI->setPhysRegUsed(Reg);
    359 }
    360