| /external/llvm/lib/CodeGen/ |
| LiveRegMatrix.cpp | 72 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
75 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
76 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
80 Matrix[*Units].unify(VirtReg);
86 void LiveRegMatrix::unassign(LiveInterval &VirtReg) {
87 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
90 VRM->clearVirt(VirtReg.reg)
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| LiveIntervalUnion.cpp | 28 void LiveIntervalUnion::unify(LiveInterval &VirtReg) {
29 if (VirtReg.empty())
34 LiveInterval::iterator RegPos = VirtReg.begin();
35 LiveInterval::iterator RegEnd = VirtReg.end();
39 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
49 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
51 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
55 void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
56 if (VirtReg.empty())
61 LiveInterval::iterator RegPos = VirtReg.begin()
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| RegAllocBase.cpp | 84 while (LiveInterval *VirtReg = dequeue()) {
85 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
88 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
89 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
90 LIS->removeInterval(VirtReg->reg);
101 << MRI->getRegClass(VirtReg->reg)->getName()
102 << ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n');
105 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
112 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg)
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| AllocationOrder.cpp | 29 AllocationOrder::AllocationOrder(unsigned VirtReg,
35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
36 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
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| RegAllocFast.cpp | 72 unsigned VirtReg; // Virtual register number.
78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
81 return TargetRegisterInfo::virtReg2Index(VirtReg);
113 // PhysRegState - One of the RegState enums, or a virtreg.
167 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
172 void killVirtReg(unsigned VirtReg);
174 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
181 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
183 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const
[all...] |
| RegAllocBasic.cpp | 103 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
112 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
165 // that interfere with VirtReg. The newly spilled or split live intervals are
167 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
175 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
181 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
187 " interferences with " << VirtReg << "\n");
221 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
227 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
230 switch (Matrix->checkInterference(VirtReg, PhysReg))
[all...] |
| RegisterCoalescer.h | 66 /// Create a CoalescerPair representing a virtreg-to-physreg copy.
68 CoalescerPair(unsigned VirtReg, unsigned PhysReg,
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
|
| RegAllocGreedy.cpp | 135 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
136 return ExtraRegInfo[VirtReg.reg].Stage;
139 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
141 ExtraRegInfo[VirtReg.reg].Stage = Stage;
352 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
353 if (VRM->hasPhys(VirtReg)) {
354 Matrix->unassign(LIS->getInterval(VirtReg));
357 // Unassigned virtreg is probably in the priority queue.
362 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
363 if (!VRM->hasPhys(VirtReg))
[all...] |
| RegAllocBase.h | 82 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
92 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
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| VirtRegMap.cpp | 80 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
81 unsigned Hint = MRI->getSimpleHint(VirtReg);
86 return getPhys(VirtReg) == Hint;
89 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
90 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
98 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
99 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
100 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
102 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
103 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC)
[all...] |
| AllocationOrder.h | 34 /// Create a new AllocationOrder for VirtReg.
35 /// @param VirtReg Virtual register to allocate for.
38 AllocationOrder(unsigned VirtReg,
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| LiveDebugVariables.cpp | 304 /// lookupVirtReg - Find the EC leader for VirtReg or null.
305 UserValue *lookupVirtReg(unsigned VirtReg);
342 void mapVirtReg(unsigned VirtReg, UserValue *EC);
433 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) {
434 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
435 UserValue *&Leader = virtRegToEqClass[VirtReg];
439 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) {
440 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
869 unsigned VirtReg = Loc.getReg();
870 if (VRM.isAssignedReg(VirtReg) &
[all...] |
| TargetRegisterInfo.cpp | 254 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
260 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
272 // Check that Phys is a valid hint in VirtReg's register class.
278 // from VirtReg's register class if they aren't in the allocation order. The
|
| InlineSpiller.cpp | 833 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
836 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
842 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
858 markValueUsed(&VirtReg, ParentVNI);
863 // If the instruction also writes VirtReg.reg, it had better not require the
867 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
869 markValueUsed(&VirtReg, ParentVNI);
[all...] |
| PHIElimination.cpp | 196 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
198 static bool isImplicitlyDefined(unsigned VirtReg,
200 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg),
|
| PrologEpilogInserter.cpp | 819 unsigned VirtReg = 0;
839 if (Reg != VirtReg) {
845 VirtReg = Reg;
[all...] |
| MachineTraceMetrics.cpp | 532 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp)
534 assert(TargetRegisterInfo::isVirtualRegister(VirtReg));
535 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveRegMatrix.h | 98 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
102 /// Check for interference before assigning VirtReg to PhysReg.
103 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
106 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
108 /// Assign VirtReg to PhysReg.
109 /// This will mark VirtReg's live range as occupied in the LiveRegMatrix and
111 void assign(LiveInterval &VirtReg, unsigned PhysReg);
113 /// Unassign VirtReg from its PhysReg.
114 /// Assuming that VirtReg was previously assigned to a PhysReg, this undoes
116 void unassign(LiveInterval &VirtReg);
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| LiveIntervalUnion.h | 87 void unify(LiveInterval &VirtReg);
90 void extract(LiveInterval &VirtReg);
107 LiveInterval *VirtReg;
108 LiveInterval::iterator VirtRegI; // current position in VirtReg
117 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
120 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
126 VirtReg = NULL;
137 if (UserTag == UTag && VirtReg == VReg &&
144 VirtReg = VReg;
149 LiveInterval &virtReg() const
[all...] |
| VirtRegMap.h | 92 bool hasPhys(unsigned virtReg) const {
93 return getPhys(virtReg) != NO_PHYS_REG;
98 unsigned getPhys(unsigned virtReg) const {
99 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
100 return Virt2PhysMap[virtReg];
105 void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
106 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
108 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
111 Virt2PhysMap[virtReg] = physReg;
116 void clearVirt(unsigned virtReg) {
[all...] |
| ScheduleDAGInstrs.h | 34 unsigned VirtReg;
37 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
40 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 114 void getRegAllocationHints(unsigned VirtReg,
|
| ARMBaseRegisterInfo.cpp | 176 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
182 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
193 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 611 /// VirtReg. These registers are effectively moved to the front of the
614 /// The Order argument is the allocation order for VirtReg's register class
622 /// order for VirtReg. There may be target-independent hints.
623 virtual void getRegAllocationHints(unsigned VirtReg,
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