/external/llvm/lib/CodeGen/ |
TargetSchedule.cpp | 102 int TargetSchedModel::getDefLatency(const MachineInstr *DefMI, 117 return TII->defaultDefLatency(&SchedModel, DefMI); 177 const MachineInstr *DefMI, unsigned DefOperIdx, 181 int DefLatency = getDefLatency(DefMI, FindMin); 189 TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx); 192 unsigned DefClass = DefMI->getDesc().getSchedClass(); 199 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); 208 TII->defaultDefLatency(&SchedModel, DefMI)); 213 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); 214 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx) [all...] |
LiveRangeEdit.cpp | 46 const MachineInstr *DefMI, 48 assert(DefMI && "Missing instruction"); 50 if (!TII.isTriviallyReMaterializable(DefMI, aa)) 62 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); 63 if (!DefMI) 65 checkRematerializable(VNI, DefMI, aa); 162 MachineInstr *DefMI = 0, *UseMI = 0; 170 if (DefMI && DefMI != MI) 174 DefMI = MI [all...] |
TargetInstrInfo.cpp | 623 const MachineInstr *DefMI) const { 624 if (DefMI->isTransient()) 626 if (DefMI->mayLoad()) 628 if (isHighLatencyDef(DefMI->getOpcode())) 646 const MachineInstr *DefMI, 651 unsigned DefClass = DefMI->getDesc().getSchedClass(); 656 /// Both DefMI and UseMI must be valid. By default, call directly to the 660 const MachineInstr *DefMI, unsigned DefIdx, 662 unsigned DefClass = DefMI->getDesc().getSchedClass(); 671 const MachineInstr *DefMI, bool FindMin) const [all...] |
PeepholeOptimizer.cpp | 338 MachineInstr *DefMI = MRI->getVRegDef(Src); 339 if (!DefMI || !DefMI->isBitcast()) 343 NumDefs = DefMI->getDesc().getNumDefs(); 344 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs; 348 const MachineOperand &MO = DefMI->getOperand(i); 554 MachineInstr *DefMI = 0; 556 FoldAsLoadDefReg, DefMI); 558 // Update LocalMIs since we replaced MI with FoldMI and deleted DefMI. 562 LocalMIs.erase(DefMI); [all...] |
RegisterCoalescer.cpp | 592 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); 593 if (!DefMI) 595 if (!DefMI->isCommutable()) 597 // If DefMI is a two-address instruction then commuting it will change the 599 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); 602 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 605 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 614 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); 640 << *DefMI); 644 MachineBasicBlock *MBB = DefMI->getParent() [all...] |
MachineTraceMetrics.cpp | 524 const MachineInstr *DefMI; 528 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) 529 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} 537 DefMI = &*DefI; 677 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); 679 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; 682 unsigned Len = LIR.Height + Cycles[DefMI].Depth; 741 BlockInfo[Dep.DefMI->getParent()->getNumber()]; 746 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth [all...] |
InlineSpiller.cpp | 108 MachineInstr *DefMI; 119 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {} 122 bool hasDef() const { return DefByOrigPHI || DefMI; } 329 if (SVI.DefMI) 330 OS << " def: " << *SVI.DefMI; 393 DepSV.DefMI = SV.DefMI; 482 return SVI->second.DefMI; 600 SVI->second.DefMI = MI; 621 return SVI->second.DefMI; [all...] |
MachineCSE.cpp | 128 MachineInstr *DefMI = MRI->getVRegDef(Reg); 129 if (!DefMI->isCopy()) 131 unsigned SrcReg = DefMI->getOperand(1).getReg(); 134 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg()) 138 DEBUG(dbgs() << "Coalescing: " << *DefMI); 142 DefMI->eraseFromParent();
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PHIElimination.cpp | 154 MachineInstr *DefMI = *I; 155 unsigned DefReg = DefMI->getOperand(0).getReg(); 158 LIS->RemoveMachineInstrFromMaps(DefMI); 159 DefMI->eraseFromParent(); 388 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 389 if (DefMI->isImplicitDef()) 390 ImpDefs.insert(DefMI);
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EarlyIfConversion.cpp | 244 MachineInstr *DefMI = MRI->getVRegDef(Reg); 245 if (!DefMI || DefMI->getParent() != Head) 247 if (InsertAfter.insert(DefMI)) 248 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); 249 if (DefMI->isTerminator()) {
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MachineSink.cpp | 140 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 141 if (DefMI->isCopyLike()) 143 DEBUG(dbgs() << "Coalescing: " << *DefMI);
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TwoAddressInstructionPass.cpp | 400 MachineInstr *DefMI = &MI; 406 if (!isPlainlyKilled(DefMI, Reg, LIS)) 415 DefMI = &*Begin; 420 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) [all...] |
StrongPHIElimination.cpp | 253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 254 if (DefMI) 255 PHISrcDefs[DefMI->getParent()].push_back(DefMI);
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TailDuplication.cpp | 236 MachineInstr *DefMI = MRI->getVRegDef(VReg); 238 if (DefMI) { 239 DefBB = DefMI->getParent(); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, 30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); 45 MachineInstr *DefMI = LastMI; 55 DefMI = &*I; 59 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 61 hasRAWHazard(DefMI, MI, TRI))) {
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MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); 96 if (DefMI->getParent() != MBB) 98 if (DefMI->isCopyLike()) { 99 Reg = DefMI->getOperand(1).getReg(); 101 DefMI = MRI->getVRegDef(Reg); 104 } else if (DefMI->isInsertSubreg()) { 105 Reg = DefMI->getOperand(2).getReg(); 107 DefMI = MRI->getVRegDef(Reg); 113 return DefMI; 148 MachineInstr *DefMI = MRI->getVRegDef(Reg) [all...] |
ARMBaseInstrInfo.h | 217 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 225 const MachineInstr *DefMI, unsigned DefIdx, 278 const MachineInstr *DefMI, unsigned DefIdx, 281 const MachineInstr *DefMI, unsigned DefIdx) const;
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ARMBaseInstrInfo.cpp | [all...] |
ARMExpandPseudoInsts.cpp | 55 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 74 MachineInstrBuilder &DefMI) { 83 DefMI.addOperand(MO); [all...] |
/external/llvm/include/llvm/CodeGen/ |
TargetSchedule.h | 143 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, 158 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx, 165 int getDefLatency(const MachineInstr *DefMI, bool FindMin) const;
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LiveRangeEdit.h | 148 /// values if DefMI may be rematerializable. 149 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
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MachineTraceMetrics.h | 295 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
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/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 375 const MachineInstr *DefMI, unsigned DefIdx, 397 /// defined by the load we are trying to fold. DefMI returns the machine 403 MachineInstr *&DefMI) const;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 480 MachineInstr *DefMI = MRI->getVRegDef(VReg); 482 if (DefMI && 483 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && [all...] |