1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PPC implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCFrameLowering.h" 15 #include "PPCInstrBuilder.h" 16 #include "PPCInstrInfo.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineModuleInfo.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/RegisterScavenging.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Target/TargetOptions.h" 26 27 using namespace llvm; 28 29 // FIXME This disables some code that aligns the stack to a boundary bigger than 30 // the default (16 bytes on Darwin) when there is a stack local of greater 31 // alignment. This does not currently work, because the delta between old and 32 // new stack pointers is added to offsets that reference incoming parameters 33 // after the prolog is generated, and the code that does that doesn't handle a 34 // variable delta. You don't want to do that anyway; a better approach is to 35 // reserve another register that retains to the incoming stack pointer, and 36 // reference parameters relative to that. 37 #define ALIGN_STACK 0 38 39 40 /// VRRegNo - Map from a numbered VR register to its enum value. 41 /// 42 static const uint16_t VRRegNo[] = { 43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 47 }; 48 49 /// RemoveVRSaveCode - We have found that this function does not need any code 50 /// to manipulate the VRSAVE register, even though it uses vector registers. 51 /// This can happen when the only registers used are known to be live in or out 52 /// of the function. Remove all of the VRSAVE related code from the function. 53 /// FIXME: The removal of the code results in a compile failure at -O0 when the 54 /// function contains a function call, as the GPR containing original VRSAVE 55 /// contents is spilled and reloaded around the call. Without the prolog code, 56 /// the spill instruction refers to an undefined register. This code needs 57 /// to account for all uses of that GPR. 58 static void RemoveVRSaveCode(MachineInstr *MI) { 59 MachineBasicBlock *Entry = MI->getParent(); 60 MachineFunction *MF = Entry->getParent(); 61 62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 63 MachineBasicBlock::iterator MBBI = MI; 64 ++MBBI; 65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 66 MBBI->eraseFromParent(); 67 68 bool RemovedAllMTVRSAVEs = true; 69 // See if we can find and remove the MTVRSAVE instruction from all of the 70 // epilog blocks. 71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 72 // If last instruction is a return instruction, add an epilogue 73 if (!I->empty() && I->back().isReturn()) { 74 bool FoundIt = false; 75 for (MBBI = I->end(); MBBI != I->begin(); ) { 76 --MBBI; 77 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 78 MBBI->eraseFromParent(); // remove it. 79 FoundIt = true; 80 break; 81 } 82 } 83 RemovedAllMTVRSAVEs &= FoundIt; 84 } 85 } 86 87 // If we found and removed all MTVRSAVE instructions, remove the read of 88 // VRSAVE as well. 89 if (RemovedAllMTVRSAVEs) { 90 MBBI = MI; 91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 92 --MBBI; 93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 94 MBBI->eraseFromParent(); 95 } 96 97 // Finally, nuke the UPDATE_VRSAVE. 98 MI->eraseFromParent(); 99 } 100 101 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 102 // instruction selector. Based on the vector registers that have been used, 103 // transform this into the appropriate ORI instruction. 104 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 105 MachineFunction *MF = MI->getParent()->getParent(); 106 DebugLoc dl = MI->getDebugLoc(); 107 108 unsigned UsedRegMask = 0; 109 for (unsigned i = 0; i != 32; ++i) 110 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 111 UsedRegMask |= 1 << (31-i); 112 113 // Live in and live out values already must be in the mask, so don't bother 114 // marking them. 115 for (MachineRegisterInfo::livein_iterator 116 I = MF->getRegInfo().livein_begin(), 117 E = MF->getRegInfo().livein_end(); I != E; ++I) { 118 unsigned RegNo = getPPCRegisterNumbering(I->first); 119 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 120 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 121 } 122 123 // Live out registers appear as use operands on return instructions. 124 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 125 UsedRegMask != 0 && BI != BE; ++BI) { 126 const MachineBasicBlock &MBB = *BI; 127 if (MBB.empty() || !MBB.back().isReturn()) 128 continue; 129 const MachineInstr &Ret = MBB.back(); 130 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 131 const MachineOperand &MO = Ret.getOperand(I); 132 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 133 continue; 134 unsigned RegNo = getPPCRegisterNumbering(MO.getReg()); 135 UsedRegMask &= ~(1 << (31-RegNo)); 136 } 137 } 138 139 // If no registers are used, turn this into a copy. 140 if (UsedRegMask == 0) { 141 // Remove all VRSAVE code. 142 RemoveVRSaveCode(MI); 143 return; 144 } 145 146 unsigned SrcReg = MI->getOperand(1).getReg(); 147 unsigned DstReg = MI->getOperand(0).getReg(); 148 149 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 150 if (DstReg != SrcReg) 151 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 152 .addReg(SrcReg) 153 .addImm(UsedRegMask); 154 else 155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 156 .addReg(SrcReg, RegState::Kill) 157 .addImm(UsedRegMask); 158 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 159 if (DstReg != SrcReg) 160 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 161 .addReg(SrcReg) 162 .addImm(UsedRegMask >> 16); 163 else 164 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 165 .addReg(SrcReg, RegState::Kill) 166 .addImm(UsedRegMask >> 16); 167 } else { 168 if (DstReg != SrcReg) 169 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 170 .addReg(SrcReg) 171 .addImm(UsedRegMask >> 16); 172 else 173 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 174 .addReg(SrcReg, RegState::Kill) 175 .addImm(UsedRegMask >> 16); 176 177 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 178 .addReg(DstReg, RegState::Kill) 179 .addImm(UsedRegMask & 0xFFFF); 180 } 181 182 // Remove the old UPDATE_VRSAVE instruction. 183 MI->eraseFromParent(); 184 } 185 186 static bool spillsCR(const MachineFunction &MF) { 187 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 188 return FuncInfo->isCRSpilled(); 189 } 190 191 static bool hasSpills(const MachineFunction &MF) { 192 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 193 return FuncInfo->hasSpills(); 194 } 195 196 static bool hasNonRISpills(const MachineFunction &MF) { 197 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 198 return FuncInfo->hasNonRISpills(); 199 } 200 201 /// determineFrameLayout - Determine the size of the frame and maximum call 202 /// frame size. 203 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 204 bool UpdateMF, 205 bool UseEstimate) const { 206 MachineFrameInfo *MFI = MF.getFrameInfo(); 207 208 // Get the number of bytes to allocate from the FrameInfo 209 unsigned FrameSize = 210 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 211 212 // Get the alignments provided by the target, and the maximum alignment 213 // (if any) of the fixed frame objects. 214 unsigned MaxAlign = MFI->getMaxAlignment(); 215 unsigned TargetAlign = getStackAlignment(); 216 unsigned AlignMask = TargetAlign - 1; // 217 218 // If we are a leaf function, and use up to 224 bytes of stack space, 219 // don't have a frame pointer, calls, or dynamic alloca then we do not need 220 // to adjust the stack pointer (we fit in the Red Zone). For 64-bit 221 // SVR4, we also require a stack frame if we need to spill the CR, 222 // since this spill area is addressed relative to the stack pointer. 223 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 224 // stackless code if all local vars are reg-allocated. 225 bool DisableRedZone = MF.getFunction()->getAttributes(). 226 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone); 227 if (!DisableRedZone && 228 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 229 !Subtarget.isSVR4ABI() || // allocated locals. 230 FrameSize == 0) && 231 FrameSize <= 224 && // Fits in red zone. 232 !MFI->hasVarSizedObjects() && // No dynamic alloca. 233 !MFI->adjustsStack() && // No calls. 234 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave. 235 Subtarget.isSVR4ABI() 236 && spillsCR(MF)) && 237 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 238 // No need for frame 239 if (UpdateMF) 240 MFI->setStackSize(0); 241 return 0; 242 } 243 244 // Get the maximum call frame size of all the calls. 245 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 246 247 // Maximum call frame needs to be at least big enough for linkage and 8 args. 248 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 249 Subtarget.isDarwinABI()); 250 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 251 252 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 253 // that allocations will be aligned. 254 if (MFI->hasVarSizedObjects()) 255 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 256 257 // Update maximum call frame size. 258 if (UpdateMF) 259 MFI->setMaxCallFrameSize(maxCallFrameSize); 260 261 // Include call frame size in total. 262 FrameSize += maxCallFrameSize; 263 264 // Make sure the frame is aligned. 265 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 266 267 // Update frame info. 268 if (UpdateMF) 269 MFI->setStackSize(FrameSize); 270 271 return FrameSize; 272 } 273 274 // hasFP - Return true if the specified function actually has a dedicated frame 275 // pointer register. 276 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 277 const MachineFrameInfo *MFI = MF.getFrameInfo(); 278 // FIXME: This is pretty much broken by design: hasFP() might be called really 279 // early, before the stack layout was calculated and thus hasFP() might return 280 // true or false here depending on the time of call. 281 return (MFI->getStackSize()) && needsFP(MF); 282 } 283 284 // needsFP - Return true if the specified function should have a dedicated frame 285 // pointer register. This is true if the function has variable sized allocas or 286 // if frame pointer elimination is disabled. 287 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 288 const MachineFrameInfo *MFI = MF.getFrameInfo(); 289 290 // Naked functions have no stack frame pushed, so we don't have a frame 291 // pointer. 292 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 293 Attribute::Naked)) 294 return false; 295 296 return MF.getTarget().Options.DisableFramePointerElim(MF) || 297 MFI->hasVarSizedObjects() || 298 (MF.getTarget().Options.GuaranteedTailCallOpt && 299 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 300 } 301 302 303 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 304 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 305 MachineBasicBlock::iterator MBBI = MBB.begin(); 306 MachineFrameInfo *MFI = MF.getFrameInfo(); 307 const PPCInstrInfo &TII = 308 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 309 310 MachineModuleInfo &MMI = MF.getMMI(); 311 DebugLoc dl; 312 bool needsFrameMoves = MMI.hasDebugInfo() || 313 MF.getFunction()->needsUnwindTableEntry(); 314 315 // Prepare for frame info. 316 MCSymbol *FrameLabel = 0; 317 318 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 319 // process it. 320 if (!Subtarget.isSVR4ABI()) 321 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 322 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 323 HandleVRSaveUpdate(MBBI, TII); 324 break; 325 } 326 } 327 328 // Move MBBI back to the beginning of the function. 329 MBBI = MBB.begin(); 330 331 // Work out frame sizes. 332 unsigned FrameSize = determineFrameLayout(MF); 333 int NegFrameSize = -FrameSize; 334 335 // Get processor type. 336 bool isPPC64 = Subtarget.isPPC64(); 337 // Get operating system 338 bool isDarwinABI = Subtarget.isDarwinABI(); 339 // Check if the link register (LR) must be saved. 340 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 341 bool MustSaveLR = FI->mustSaveLR(); 342 // Do we have a frame pointer for this function? 343 bool HasFP = hasFP(MF); 344 345 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 346 347 int FPOffset = 0; 348 if (HasFP) { 349 if (Subtarget.isSVR4ABI()) { 350 MachineFrameInfo *FFI = MF.getFrameInfo(); 351 int FPIndex = FI->getFramePointerSaveIndex(); 352 assert(FPIndex && "No Frame Pointer Save Slot!"); 353 FPOffset = FFI->getObjectOffset(FPIndex); 354 } else { 355 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 356 } 357 } 358 359 if (isPPC64) { 360 if (MustSaveLR) 361 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 362 363 if (HasFP) 364 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 365 .addReg(PPC::X31) 366 .addImm(FPOffset/4) 367 .addReg(PPC::X1); 368 369 if (MustSaveLR) 370 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 371 .addReg(PPC::X0) 372 .addImm(LROffset / 4) 373 .addReg(PPC::X1); 374 } else { 375 if (MustSaveLR) 376 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 377 378 if (HasFP) 379 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative 380 // offsets of R1 is not allowed. 381 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 382 .addReg(PPC::R31) 383 .addImm(FPOffset) 384 .addReg(PPC::R1); 385 386 if (MustSaveLR) 387 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 388 .addReg(PPC::R0) 389 .addImm(LROffset) 390 .addReg(PPC::R1); 391 } 392 393 // Skip if a leaf routine. 394 if (!FrameSize) return; 395 396 // Get stack alignments. 397 unsigned TargetAlign = getStackAlignment(); 398 unsigned MaxAlign = MFI->getMaxAlignment(); 399 400 // Adjust stack pointer: r1 += NegFrameSize. 401 // If there is a preferred stack alignment, align R1 now 402 if (!isPPC64) { 403 // PPC32. 404 if (ALIGN_STACK && MaxAlign > TargetAlign) { 405 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 406 "Invalid alignment!"); 407 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 408 409 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 410 .addReg(PPC::R1) 411 .addImm(0) 412 .addImm(32 - Log2_32(MaxAlign)) 413 .addImm(31); 414 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 415 .addReg(PPC::R0, RegState::Kill) 416 .addImm(NegFrameSize); 417 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 418 .addReg(PPC::R1, RegState::Kill) 419 .addReg(PPC::R1) 420 .addReg(PPC::R0); 421 } else if (isInt<16>(NegFrameSize)) { 422 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 423 .addReg(PPC::R1) 424 .addImm(NegFrameSize) 425 .addReg(PPC::R1); 426 } else { 427 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 428 .addImm(NegFrameSize >> 16); 429 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 430 .addReg(PPC::R0, RegState::Kill) 431 .addImm(NegFrameSize & 0xFFFF); 432 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 433 .addReg(PPC::R1, RegState::Kill) 434 .addReg(PPC::R1) 435 .addReg(PPC::R0); 436 } 437 } else { // PPC64. 438 if (ALIGN_STACK && MaxAlign > TargetAlign) { 439 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 440 "Invalid alignment!"); 441 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 442 443 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 444 .addReg(PPC::X1) 445 .addImm(0) 446 .addImm(64 - Log2_32(MaxAlign)); 447 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 448 .addReg(PPC::X0) 449 .addImm(NegFrameSize); 450 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 451 .addReg(PPC::X1, RegState::Kill) 452 .addReg(PPC::X1) 453 .addReg(PPC::X0); 454 } else if (isInt<16>(NegFrameSize)) { 455 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 456 .addReg(PPC::X1) 457 .addImm(NegFrameSize / 4) 458 .addReg(PPC::X1); 459 } else { 460 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 461 .addImm(NegFrameSize >> 16); 462 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 463 .addReg(PPC::X0, RegState::Kill) 464 .addImm(NegFrameSize & 0xFFFF); 465 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 466 .addReg(PPC::X1, RegState::Kill) 467 .addReg(PPC::X1) 468 .addReg(PPC::X0); 469 } 470 } 471 472 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 473 474 // Add the "machine moves" for the instructions we generated above, but in 475 // reverse order. 476 if (needsFrameMoves) { 477 // Mark effective beginning of when frame pointer becomes valid. 478 FrameLabel = MMI.getContext().CreateTempSymbol(); 479 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 480 481 // Show update of SP. 482 if (NegFrameSize) { 483 MachineLocation SPDst(MachineLocation::VirtualFP); 484 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 485 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 486 } else { 487 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 488 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 489 } 490 491 if (HasFP) { 492 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 493 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 494 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 495 } 496 497 if (MustSaveLR) { 498 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 499 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 500 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 501 } 502 } 503 504 MCSymbol *ReadyLabel = 0; 505 506 // If there is a frame pointer, copy R1 into R31 507 if (HasFP) { 508 if (!isPPC64) { 509 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 510 .addReg(PPC::R1) 511 .addReg(PPC::R1); 512 } else { 513 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 514 .addReg(PPC::X1) 515 .addReg(PPC::X1); 516 } 517 518 if (needsFrameMoves) { 519 ReadyLabel = MMI.getContext().CreateTempSymbol(); 520 521 // Mark effective beginning of when frame pointer is ready. 522 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 523 524 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 525 (isPPC64 ? PPC::X1 : PPC::R1)); 526 MachineLocation FPSrc(MachineLocation::VirtualFP); 527 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 528 } 529 } 530 531 if (needsFrameMoves) { 532 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 533 534 // Add callee saved registers to move list. 535 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 536 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 537 unsigned Reg = CSI[I].getReg(); 538 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 539 540 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 541 // subregisters of CR2. We just need to emit a move of CR2. 542 if (PPC::CRBITRCRegClass.contains(Reg)) 543 continue; 544 545 // For SVR4, don't emit a move for the CR spill slot if we haven't 546 // spilled CRs. 547 if (Subtarget.isSVR4ABI() 548 && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 549 && !spillsCR(MF)) 550 continue; 551 552 // For 64-bit SVR4 when we have spilled CRs, the spill location 553 // is SP+8, not a frame-relative slot. 554 if (Subtarget.isSVR4ABI() 555 && Subtarget.isPPC64() 556 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 557 MachineLocation CSDst(PPC::X1, 8); 558 MachineLocation CSSrc(PPC::CR2); 559 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 560 continue; 561 } 562 563 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 564 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 565 MachineLocation CSSrc(Reg); 566 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 567 } 568 } 569 } 570 571 void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 572 MachineBasicBlock &MBB) const { 573 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 574 assert(MBBI != MBB.end() && "Returning block has no terminator"); 575 const PPCInstrInfo &TII = 576 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 577 578 unsigned RetOpcode = MBBI->getOpcode(); 579 DebugLoc dl; 580 581 assert((RetOpcode == PPC::BLR || 582 RetOpcode == PPC::TCRETURNri || 583 RetOpcode == PPC::TCRETURNdi || 584 RetOpcode == PPC::TCRETURNai || 585 RetOpcode == PPC::TCRETURNri8 || 586 RetOpcode == PPC::TCRETURNdi8 || 587 RetOpcode == PPC::TCRETURNai8) && 588 "Can only insert epilog into returning blocks"); 589 590 // Get alignment info so we know how to restore r1 591 const MachineFrameInfo *MFI = MF.getFrameInfo(); 592 unsigned TargetAlign = getStackAlignment(); 593 unsigned MaxAlign = MFI->getMaxAlignment(); 594 595 // Get the number of bytes allocated from the FrameInfo. 596 int FrameSize = MFI->getStackSize(); 597 598 // Get processor type. 599 bool isPPC64 = Subtarget.isPPC64(); 600 // Get operating system 601 bool isDarwinABI = Subtarget.isDarwinABI(); 602 // Check if the link register (LR) has been saved. 603 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 604 bool MustSaveLR = FI->mustSaveLR(); 605 // Do we have a frame pointer for this function? 606 bool HasFP = hasFP(MF); 607 608 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 609 610 int FPOffset = 0; 611 if (HasFP) { 612 if (Subtarget.isSVR4ABI()) { 613 MachineFrameInfo *FFI = MF.getFrameInfo(); 614 int FPIndex = FI->getFramePointerSaveIndex(); 615 assert(FPIndex && "No Frame Pointer Save Slot!"); 616 FPOffset = FFI->getObjectOffset(FPIndex); 617 } else { 618 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 619 } 620 } 621 622 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 623 RetOpcode == PPC::TCRETURNdi || 624 RetOpcode == PPC::TCRETURNai || 625 RetOpcode == PPC::TCRETURNri8 || 626 RetOpcode == PPC::TCRETURNdi8 || 627 RetOpcode == PPC::TCRETURNai8; 628 629 if (UsesTCRet) { 630 int MaxTCRetDelta = FI->getTailCallSPDelta(); 631 MachineOperand &StackAdjust = MBBI->getOperand(1); 632 assert(StackAdjust.isImm() && "Expecting immediate value."); 633 // Adjust stack pointer. 634 int StackAdj = StackAdjust.getImm(); 635 int Delta = StackAdj - MaxTCRetDelta; 636 assert((Delta >= 0) && "Delta must be positive"); 637 if (MaxTCRetDelta>0) 638 FrameSize += (StackAdj +Delta); 639 else 640 FrameSize += StackAdj; 641 } 642 643 if (FrameSize) { 644 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 645 // on entry to the function. Add this offset back now. 646 if (!isPPC64) { 647 // If this function contained a fastcc call and GuaranteedTailCallOpt is 648 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 649 // call which invalidates the stack pointer value in SP(0). So we use the 650 // value of R31 in this case. 651 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 652 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 653 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 654 .addReg(PPC::R31).addImm(FrameSize); 655 } else if(FI->hasFastCall()) { 656 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 657 .addImm(FrameSize >> 16); 658 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 659 .addReg(PPC::R0, RegState::Kill) 660 .addImm(FrameSize & 0xFFFF); 661 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 662 .addReg(PPC::R1) 663 .addReg(PPC::R31) 664 .addReg(PPC::R0); 665 } else if (isInt<16>(FrameSize) && 666 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 667 !MFI->hasVarSizedObjects()) { 668 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 669 .addReg(PPC::R1).addImm(FrameSize); 670 } else { 671 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 672 .addImm(0).addReg(PPC::R1); 673 } 674 } else { 675 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 676 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 677 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 678 .addReg(PPC::X31).addImm(FrameSize); 679 } else if(FI->hasFastCall()) { 680 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 681 .addImm(FrameSize >> 16); 682 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 683 .addReg(PPC::X0, RegState::Kill) 684 .addImm(FrameSize & 0xFFFF); 685 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 686 .addReg(PPC::X1) 687 .addReg(PPC::X31) 688 .addReg(PPC::X0); 689 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 690 !MFI->hasVarSizedObjects()) { 691 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 692 .addReg(PPC::X1).addImm(FrameSize); 693 } else { 694 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 695 .addImm(0).addReg(PPC::X1); 696 } 697 } 698 } 699 700 if (isPPC64) { 701 if (MustSaveLR) 702 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 703 .addImm(LROffset/4).addReg(PPC::X1); 704 705 if (HasFP) 706 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 707 .addImm(FPOffset/4).addReg(PPC::X1); 708 709 if (MustSaveLR) 710 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 711 } else { 712 if (MustSaveLR) 713 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 714 .addImm(LROffset).addReg(PPC::R1); 715 716 if (HasFP) 717 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 718 .addImm(FPOffset).addReg(PPC::R1); 719 720 if (MustSaveLR) 721 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 722 } 723 724 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 725 // call optimization 726 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 727 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 728 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 729 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 730 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 731 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 732 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 733 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 734 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 735 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 736 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 737 738 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 739 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 740 .addReg(StackReg).addImm(CallerAllocatedAmt); 741 } else { 742 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 743 .addImm(CallerAllocatedAmt >> 16); 744 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 745 .addReg(TmpReg, RegState::Kill) 746 .addImm(CallerAllocatedAmt & 0xFFFF); 747 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 748 .addReg(StackReg) 749 .addReg(FPReg) 750 .addReg(TmpReg); 751 } 752 } else if (RetOpcode == PPC::TCRETURNdi) { 753 MBBI = MBB.getLastNonDebugInstr(); 754 MachineOperand &JumpTarget = MBBI->getOperand(0); 755 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 756 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 757 } else if (RetOpcode == PPC::TCRETURNri) { 758 MBBI = MBB.getLastNonDebugInstr(); 759 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 760 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 761 } else if (RetOpcode == PPC::TCRETURNai) { 762 MBBI = MBB.getLastNonDebugInstr(); 763 MachineOperand &JumpTarget = MBBI->getOperand(0); 764 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 765 } else if (RetOpcode == PPC::TCRETURNdi8) { 766 MBBI = MBB.getLastNonDebugInstr(); 767 MachineOperand &JumpTarget = MBBI->getOperand(0); 768 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 769 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 770 } else if (RetOpcode == PPC::TCRETURNri8) { 771 MBBI = MBB.getLastNonDebugInstr(); 772 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 773 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 774 } else if (RetOpcode == PPC::TCRETURNai8) { 775 MBBI = MBB.getLastNonDebugInstr(); 776 MachineOperand &JumpTarget = MBBI->getOperand(0); 777 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 778 } 779 } 780 781 /// MustSaveLR - Return true if this function requires that we save the LR 782 /// register onto the stack in the prolog and restore it in the epilog of the 783 /// function. 784 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 785 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 786 787 // We need a save/restore of LR if there is any def of LR (which is 788 // defined by calls, including the PIC setup sequence), or if there is 789 // some use of the LR stack slot (e.g. for builtin_return_address). 790 // (LR comes in 32 and 64 bit versions.) 791 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 792 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 793 } 794 795 void 796 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 797 RegScavenger *) const { 798 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 799 800 // Save and clear the LR state. 801 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 802 unsigned LR = RegInfo->getRARegister(); 803 FI->setMustSaveLR(MustSaveLR(MF, LR)); 804 MachineRegisterInfo &MRI = MF.getRegInfo(); 805 MRI.setPhysRegUnused(LR); 806 807 // Save R31 if necessary 808 int FPSI = FI->getFramePointerSaveIndex(); 809 bool isPPC64 = Subtarget.isPPC64(); 810 bool isDarwinABI = Subtarget.isDarwinABI(); 811 MachineFrameInfo *MFI = MF.getFrameInfo(); 812 813 // If the frame pointer save index hasn't been defined yet. 814 if (!FPSI && needsFP(MF)) { 815 // Find out what the fix offset of the frame pointer save area. 816 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 817 // Allocate the frame index for frame pointer save area. 818 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 819 // Save the result. 820 FI->setFramePointerSaveIndex(FPSI); 821 } 822 823 // Reserve stack space to move the linkage area to in case of a tail call. 824 int TCSPDelta = 0; 825 if (MF.getTarget().Options.GuaranteedTailCallOpt && 826 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 827 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 828 } 829 830 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 831 // function uses CR 2, 3, or 4. 832 if (!isPPC64 && !isDarwinABI && 833 (MRI.isPhysRegUsed(PPC::CR2) || 834 MRI.isPhysRegUsed(PPC::CR3) || 835 MRI.isPhysRegUsed(PPC::CR4))) { 836 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 837 FI->setCRSpillFrameIndex(FrameIdx); 838 } 839 } 840 841 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 842 RegScavenger *RS) const { 843 // Early exit if not using the SVR4 ABI. 844 if (!Subtarget.isSVR4ABI()) { 845 addScavengingSpillSlot(MF, RS); 846 return; 847 } 848 849 // Get callee saved register information. 850 MachineFrameInfo *FFI = MF.getFrameInfo(); 851 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 852 853 // Early exit if no callee saved registers are modified! 854 if (CSI.empty() && !needsFP(MF)) { 855 addScavengingSpillSlot(MF, RS); 856 return; 857 } 858 859 unsigned MinGPR = PPC::R31; 860 unsigned MinG8R = PPC::X31; 861 unsigned MinFPR = PPC::F31; 862 unsigned MinVR = PPC::V31; 863 864 bool HasGPSaveArea = false; 865 bool HasG8SaveArea = false; 866 bool HasFPSaveArea = false; 867 bool HasVRSAVESaveArea = false; 868 bool HasVRSaveArea = false; 869 870 SmallVector<CalleeSavedInfo, 18> GPRegs; 871 SmallVector<CalleeSavedInfo, 18> G8Regs; 872 SmallVector<CalleeSavedInfo, 18> FPRegs; 873 SmallVector<CalleeSavedInfo, 18> VRegs; 874 875 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 876 unsigned Reg = CSI[i].getReg(); 877 if (PPC::GPRCRegClass.contains(Reg)) { 878 HasGPSaveArea = true; 879 880 GPRegs.push_back(CSI[i]); 881 882 if (Reg < MinGPR) { 883 MinGPR = Reg; 884 } 885 } else if (PPC::G8RCRegClass.contains(Reg)) { 886 HasG8SaveArea = true; 887 888 G8Regs.push_back(CSI[i]); 889 890 if (Reg < MinG8R) { 891 MinG8R = Reg; 892 } 893 } else if (PPC::F8RCRegClass.contains(Reg)) { 894 HasFPSaveArea = true; 895 896 FPRegs.push_back(CSI[i]); 897 898 if (Reg < MinFPR) { 899 MinFPR = Reg; 900 } 901 } else if (PPC::CRBITRCRegClass.contains(Reg) || 902 PPC::CRRCRegClass.contains(Reg)) { 903 ; // do nothing, as we already know whether CRs are spilled 904 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 905 HasVRSAVESaveArea = true; 906 } else if (PPC::VRRCRegClass.contains(Reg)) { 907 HasVRSaveArea = true; 908 909 VRegs.push_back(CSI[i]); 910 911 if (Reg < MinVR) { 912 MinVR = Reg; 913 } 914 } else { 915 llvm_unreachable("Unknown RegisterClass!"); 916 } 917 } 918 919 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 920 921 int64_t LowerBound = 0; 922 923 // Take into account stack space reserved for tail calls. 924 int TCSPDelta = 0; 925 if (MF.getTarget().Options.GuaranteedTailCallOpt && 926 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 927 LowerBound = TCSPDelta; 928 } 929 930 // The Floating-point register save area is right below the back chain word 931 // of the previous stack frame. 932 if (HasFPSaveArea) { 933 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 934 int FI = FPRegs[i].getFrameIdx(); 935 936 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 937 } 938 939 LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8; 940 } 941 942 // Check whether the frame pointer register is allocated. If so, make sure it 943 // is spilled to the correct offset. 944 if (needsFP(MF)) { 945 HasGPSaveArea = true; 946 947 int FI = PFI->getFramePointerSaveIndex(); 948 assert(FI && "No Frame Pointer Save Slot!"); 949 950 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 951 } 952 953 // General register save area starts right below the Floating-point 954 // register save area. 955 if (HasGPSaveArea || HasG8SaveArea) { 956 // Move general register save area spill slots down, taking into account 957 // the size of the Floating-point register save area. 958 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 959 int FI = GPRegs[i].getFrameIdx(); 960 961 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 962 } 963 964 // Move general register save area spill slots down, taking into account 965 // the size of the Floating-point register save area. 966 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 967 int FI = G8Regs[i].getFrameIdx(); 968 969 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 970 } 971 972 unsigned MinReg = 973 std::min<unsigned>(getPPCRegisterNumbering(MinGPR), 974 getPPCRegisterNumbering(MinG8R)); 975 976 if (Subtarget.isPPC64()) { 977 LowerBound -= (31 - MinReg + 1) * 8; 978 } else { 979 LowerBound -= (31 - MinReg + 1) * 4; 980 } 981 } 982 983 // For 32-bit only, the CR save area is below the general register 984 // save area. For 64-bit SVR4, the CR save area is addressed relative 985 // to the stack pointer and hence does not need an adjustment here. 986 // Only CR2 (the first nonvolatile spilled) has an associated frame 987 // index so that we have a single uniform save area. 988 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 989 // Adjust the frame index of the CR spill slot. 990 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 991 unsigned Reg = CSI[i].getReg(); 992 993 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 994 // Leave Darwin logic as-is. 995 || (!Subtarget.isSVR4ABI() && 996 (PPC::CRBITRCRegClass.contains(Reg) || 997 PPC::CRRCRegClass.contains(Reg)))) { 998 int FI = CSI[i].getFrameIdx(); 999 1000 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1001 } 1002 } 1003 1004 LowerBound -= 4; // The CR save area is always 4 bytes long. 1005 } 1006 1007 if (HasVRSAVESaveArea) { 1008 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1009 // which have the VRSAVE register class? 1010 // Adjust the frame index of the VRSAVE spill slot. 1011 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1012 unsigned Reg = CSI[i].getReg(); 1013 1014 if (PPC::VRSAVERCRegClass.contains(Reg)) { 1015 int FI = CSI[i].getFrameIdx(); 1016 1017 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1018 } 1019 } 1020 1021 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1022 } 1023 1024 if (HasVRSaveArea) { 1025 // Insert alignment padding, we need 16-byte alignment. 1026 LowerBound = (LowerBound - 15) & ~(15); 1027 1028 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1029 int FI = VRegs[i].getFrameIdx(); 1030 1031 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1032 } 1033 } 1034 1035 addScavengingSpillSlot(MF, RS); 1036 } 1037 1038 void 1039 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1040 RegScavenger *RS) const { 1041 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1042 // a large stack, which will require scavenging a register to materialize a 1043 // large offset. 1044 1045 // We need to have a scavenger spill slot for spills if the frame size is 1046 // large. In case there is no free register for large-offset addressing, 1047 // this slot is used for the necessary emergency spill. Also, we need the 1048 // slot for dynamic stack allocations. 1049 1050 // The scavenger might be invoked if the frame offset does not fit into 1051 // the 16-bit immediate. We don't know the complete frame size here 1052 // because we've not yet computed callee-saved register spills or the 1053 // needed alignment padding. 1054 unsigned StackSize = determineFrameLayout(MF, false, true); 1055 MachineFrameInfo *MFI = MF.getFrameInfo(); 1056 if (MFI->hasVarSizedObjects() || spillsCR(MF) || hasNonRISpills(MF) || 1057 (hasSpills(MF) && !isInt<16>(StackSize))) { 1058 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1059 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1060 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1061 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1062 RC->getAlignment(), 1063 false)); 1064 } 1065 } 1066 1067 bool 1068 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1069 MachineBasicBlock::iterator MI, 1070 const std::vector<CalleeSavedInfo> &CSI, 1071 const TargetRegisterInfo *TRI) const { 1072 1073 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1074 // Return false otherwise to maintain pre-existing behavior. 1075 if (!Subtarget.isSVR4ABI()) 1076 return false; 1077 1078 MachineFunction *MF = MBB.getParent(); 1079 const PPCInstrInfo &TII = 1080 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1081 DebugLoc DL; 1082 bool CRSpilled = false; 1083 1084 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1085 unsigned Reg = CSI[i].getReg(); 1086 // CR2 through CR4 are the nonvolatile CR fields. 1087 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1088 1089 if (CRSpilled && IsCRField) 1090 continue; 1091 1092 // Add the callee-saved register as live-in; it's killed at the spill. 1093 MBB.addLiveIn(Reg); 1094 1095 // Insert the spill to the stack frame. 1096 if (IsCRField) { 1097 CRSpilled = true; 1098 // The first time we see a CR field, store the whole CR into the 1099 // save slot via GPR12 (available in the prolog for 32- and 64-bit). 1100 if (Subtarget.isPPC64()) { 1101 // 64-bit: SP+8 1102 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::X12)); 1103 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW)) 1104 .addReg(PPC::X12, 1105 getKillRegState(true)) 1106 .addImm(8) 1107 .addReg(PPC::X1)); 1108 } else { 1109 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1110 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1111 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)); 1112 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1113 .addReg(PPC::R12, 1114 getKillRegState(true)), 1115 CSI[i].getFrameIdx())); 1116 } 1117 1118 // Record that we spill the CR in this function. 1119 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1120 FuncInfo->setSpillsCR(); 1121 } else { 1122 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1123 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1124 CSI[i].getFrameIdx(), RC, TRI); 1125 } 1126 } 1127 return true; 1128 } 1129 1130 static void 1131 restoreCRs(bool isPPC64, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1132 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1133 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1134 1135 MachineFunction *MF = MBB.getParent(); 1136 const PPCInstrInfo &TII = 1137 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1138 DebugLoc DL; 1139 unsigned RestoreOp, MoveReg; 1140 1141 if (isPPC64) { 1142 // 64-bit: SP+8 1143 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ), PPC::X12) 1144 .addImm(8) 1145 .addReg(PPC::X1)); 1146 RestoreOp = PPC::MTCRF8; 1147 MoveReg = PPC::X12; 1148 } else { 1149 // 32-bit: FP-relative 1150 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1151 PPC::R12), 1152 CSI[CSIIndex].getFrameIdx())); 1153 RestoreOp = PPC::MTCRF; 1154 MoveReg = PPC::R12; 1155 } 1156 1157 if (CR2Spilled) 1158 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1159 .addReg(MoveReg)); 1160 1161 if (CR3Spilled) 1162 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1163 .addReg(MoveReg)); 1164 1165 if (CR4Spilled) 1166 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1167 .addReg(MoveReg)); 1168 } 1169 1170 void PPCFrameLowering:: 1171 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1172 MachineBasicBlock::iterator I) const { 1173 const PPCInstrInfo &TII = 1174 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 1175 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1176 I->getOpcode() == PPC::ADJCALLSTACKUP) { 1177 // Add (actually subtract) back the amount the callee popped on return. 1178 if (int CalleeAmt = I->getOperand(1).getImm()) { 1179 bool is64Bit = Subtarget.isPPC64(); 1180 CalleeAmt *= -1; 1181 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1182 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1183 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1184 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1185 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1186 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1187 MachineInstr *MI = I; 1188 DebugLoc dl = MI->getDebugLoc(); 1189 1190 if (isInt<16>(CalleeAmt)) { 1191 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1192 .addReg(StackReg, RegState::Kill) 1193 .addImm(CalleeAmt); 1194 } else { 1195 MachineBasicBlock::iterator MBBI = I; 1196 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1197 .addImm(CalleeAmt >> 16); 1198 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1199 .addReg(TmpReg, RegState::Kill) 1200 .addImm(CalleeAmt & 0xFFFF); 1201 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1202 .addReg(StackReg, RegState::Kill) 1203 .addReg(TmpReg); 1204 } 1205 } 1206 } 1207 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1208 MBB.erase(I); 1209 } 1210 1211 bool 1212 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1213 MachineBasicBlock::iterator MI, 1214 const std::vector<CalleeSavedInfo> &CSI, 1215 const TargetRegisterInfo *TRI) const { 1216 1217 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1218 // Return false otherwise to maintain pre-existing behavior. 1219 if (!Subtarget.isSVR4ABI()) 1220 return false; 1221 1222 MachineFunction *MF = MBB.getParent(); 1223 const PPCInstrInfo &TII = 1224 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1225 bool CR2Spilled = false; 1226 bool CR3Spilled = false; 1227 bool CR4Spilled = false; 1228 unsigned CSIIndex = 0; 1229 1230 // Initialize insertion-point logic; we will be restoring in reverse 1231 // order of spill. 1232 MachineBasicBlock::iterator I = MI, BeforeI = I; 1233 bool AtStart = I == MBB.begin(); 1234 1235 if (!AtStart) 1236 --BeforeI; 1237 1238 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1239 unsigned Reg = CSI[i].getReg(); 1240 1241 if (Reg == PPC::CR2) { 1242 CR2Spilled = true; 1243 // The spill slot is associated only with CR2, which is the 1244 // first nonvolatile spilled. Save it here. 1245 CSIIndex = i; 1246 continue; 1247 } else if (Reg == PPC::CR3) { 1248 CR3Spilled = true; 1249 continue; 1250 } else if (Reg == PPC::CR4) { 1251 CR4Spilled = true; 1252 continue; 1253 } else { 1254 // When we first encounter a non-CR register after seeing at 1255 // least one CR register, restore all spilled CRs together. 1256 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1257 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1258 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled, 1259 MBB, I, CSI, CSIIndex); 1260 CR2Spilled = CR3Spilled = CR4Spilled = false; 1261 } 1262 1263 // Default behavior for non-CR saves. 1264 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1265 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1266 RC, TRI); 1267 assert(I != MBB.begin() && 1268 "loadRegFromStackSlot didn't insert any code!"); 1269 } 1270 1271 // Insert in reverse order. 1272 if (AtStart) 1273 I = MBB.begin(); 1274 else { 1275 I = BeforeI; 1276 ++I; 1277 } 1278 } 1279 1280 // If we haven't yet spilled the CRs, do so now. 1281 if (CR2Spilled || CR3Spilled || CR4Spilled) 1282 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled, 1283 MBB, I, CSI, CSIIndex); 1284 1285 return true; 1286 } 1287 1288