| /external/llvm/lib/Target/Hexagon/ |
| HexagonVLIWPacketizer.cpp | 44 #include "Hexagon.h"
71 return "Hexagon Packetizer";
237 return ((MI->getOpcode() == Hexagon::CALLR) ||
238 (MI->getOpcode() == Hexagon::CALLRv3));
246 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
264 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
276 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
311 if (RC == &Hexagon::PredRegsRegClass) {
339 return (MI->getOpcode() == Hexagon::JMP);
344 case Hexagon::BARRIER
[all...] |
| HexagonInstrInfo.cpp | 1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
15 #include "Hexagon.h"
35 /// Constants for Hexagon instructions.
58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
74 case Hexagon::LDriw:
75 case Hexagon::LDrid:
76 case Hexagon::LDrih:
77 case Hexagon::LDrib
[all...] |
| HexagonRegisterInfo.cpp | 1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
16 #include "Hexagon.h"
42 : HexagonGenRegisterInfo(Hexagon::R31),
51 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
54 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19
[all...] |
| HexagonSplitTFRCondSets.cpp | 30 #include "Hexagon.h"
64 return "Hexagon Split TFRCondSets";
87 case Hexagon::TFR_condset_rr:
88 case Hexagon::TFR_condset_rr_f:
89 case Hexagon::TFR_condset_rr64_f: {
94 if (MI->getOpcode() == Hexagon::TFR_condset_rr ||
95 MI->getOpcode() == Hexagon::TFR_condset_rr_f) {
96 Opc1 = Hexagon::TFR_cPt;
97 Opc2 = Hexagon::TFR_cNotPt;
99 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f)
[all...] |
| HexagonNewValueJump.cpp | 1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
10 // This implements NewValueJump pass in Hexagon.
24 #define DEBUG_TYPE "hexagon-nvj"
25 #include "Hexagon.h"
75 return "Hexagon NewValueJump";
161 if (MII->getOpcode() == Hexagon::CALLv3)
180 // The following pseudo Hexagon instructions sets "use" and "def"
184 if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
185 MII->getOpcode() == Hexagon::TFR_condset_ii ||
186 MII->getOpcode() == Hexagon::TFR_condset_ri |
[all...] |
| HexagonVarargsCallingConvention.h | 53 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
54 Hexagon::R5
66 Hexagon::D0, Hexagon::D1, Hexagon::D2
109 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4
[all...] |
| HexagonExpandPredSpillCode.cpp | 9 // The Hexagon processor has no instructions that load or store predicate
20 #include "Hexagon.h"
56 return "Hexagon Expand Predicate Spill Code";
78 if (Opc == Hexagon::STriw_pred) {
86 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
88 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) {
89 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
91 TII->get(Hexagon::CONST32_Int_Real),
93 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
96 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd)
[all...] |
| HexagonCFGOptimizer.cpp | 10 #include "Hexagon.h"
46 return "Hexagon CFG Optimizer";
55 return (Opc == Hexagon::JMP_c) || (Opc == Hexagon::JMP_cNot)
56 || (Opc == Hexagon::JMP_cdnPt) || (Opc == Hexagon::JMP_cdnNotPt);
61 return (Opc == Hexagon::JMP);
71 case Hexagon::JMP_c:
72 NewOpcode = Hexagon::JMP_cNot;
75 case Hexagon::JMP_cNot
[all...] |
| HexagonMachineFunctionInfo.h | 1 //=- HexagonMachineFuctionInfo.h - Hexagon machine function info --*- C++ -*-=//
17 namespace Hexagon {
23 /// Hexagon target-specific information for each MachineFunction.
56 PacketInfo[MI] |= Hexagon::StartPacket;
59 PacketInfo[MI] |= Hexagon::EndPacket;
63 (PacketInfo.find(MI)->second & Hexagon::StartPacket));
67 (PacketInfo.find(MI)->second & Hexagon::EndPacket));
|
| HexagonFixupHwLoops.cpp | 25 #include "Hexagon.h"
45 const char *getPassName() const { return "Hexagon Hardware Loop Fixup"; }
73 "Hexagon Hardware Loops Fixup", false, false)
82 return MI->getOpcode() == Hexagon::LOOP0_r ||
83 MI->getOpcode() == Hexagon::LOOP0_i;
93 /// \brief For Hexagon, if the loop label is to far from the
164 unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0);
169 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
173 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFRI), Scratch
[all...] |
| HexagonPeephole.cpp | 1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
38 #define DEBUG_TYPE "hexagon-peephole"
39 #include "Hexagon.h"
60 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
68 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
72 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
89 return "Hexagon optimize redundant zero and size extends";
129 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) {
150 if (MI->getOpcode() == Hexagon::LSRd_ri) {
160 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/)
[all...] |
| Makefile | 1 ##===- lib/Target/Hexagon/Makefile -------------------------*- Makefile -*-===##
11 TARGET = Hexagon
|
| HexagonRegisterInfo.h | 1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
|
| HexagonFrameLowering.cpp | 12 #include "Hexagon.h"
40 "disable-hexagon-dealloc-ret",
42 cl::desc("Disable Dealloc Return for Hexagon target"));
108 assert((MI->getOpcode() == Hexagon::ADJDYNALLOC) &&
149 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
152 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
154 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
159 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
169 return RetOpcode == Hexagon::TCRETURNtg || RetOpcode == Hexagon::TCRETURNtext
[all...] |
| HexagonISelDAGToDAG.cpp | 1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
10 // This file defines an instruction selector for the Hexagon target.
14 #define DEBUG_TYPE "hexagon-isel"
15 #include "Hexagon.h"
42 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
47 /// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
84 return "Hexagon DAG->DAG Pattern Instruction Selection";
130 /// Hexagon-specific DAG, ready for instruction scheduling.
138 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection"
[all...] |
| HexagonHardwareLoops.cpp | 10 // This pass identifies loops where we can generate the Hexagon hardware
43 #include "Hexagon.h"
83 const char *getPassName() const { return "Hexagon Hardware Loops"; }
278 "Hexagon Hardware Loops", false, false)
282 "Hexagon Hardware Loops", false, false)
287 return MI->getOpcode() == Hexagon::LOOP0_r ||
288 MI->getOpcode() == Hexagon::LOOP0_i;
297 DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
357 bool isAdd = (UpdOpc == Hexagon::ADD_ri);
540 case Hexagon::CMPEQri
[all...] |
| HexagonISelLowering.cpp | 1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
45 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
46 cl::desc("Control jump table emission on Hexagon target"));
50 // Implement calling convention for Hexagon.
174 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4
[all...] |
| HexagonCallingConvLower.cpp | 17 #include "Hexagon.h"
98 // For Hexagon, Return small structures in registers.
101 unsigned Reg = Hexagon::R0;
107 unsigned Reg = Hexagon::D0;
|
| HexagonAsmPrinter.cpp | 1 //===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly --===//
11 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
17 #include "Hexagon.h"
61 "hexagon-align-calls", cl::Hidden, cl::init(true),
62 cl::desc("Insert falign after call instruction for Hexagon target"));
140 // Hexagon never has a prefix.
196 /// printMachineInstruction -- Print out a single Hexagon MI in Darwin syntax to
232 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCTargetDesc.cpp | 1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
10 // This file provides Hexagon specific target descriptions.
45 InitHexagonMCRegisterInfo(X, Hexagon::R0);
62 MachineLocation Src(Hexagon::R30, 0);
|
| /external/clang/include/clang/Basic/ |
| TargetBuiltins.h | 105 /// \brief Hexagon builtins
106 namespace Hexagon {
|
| /external/llvm/lib/Target/Hexagon/InstPrinter/ |
| HexagonInstPrinter.cpp | 1 //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
10 // This class prints an Hexagon MCInst to a .s file.
16 #include "Hexagon.h"
51 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
61 Nop.setOpcode (Hexagon::NOP);
|
| /external/clang/lib/Basic/ |
| Targets.cpp | [all...] |
| /external/llvm/ |
| configure | [all...] |
| /external/llvm/projects/sample/ |
| configure | [all...] |
