| /external/llvm/lib/CodeGen/ |
| DFAPacketizer.cpp | 109 MachineDominatorTree &MDT, bool IsPostRA);
116 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
118 ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
129 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
133 VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
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| UnreachableBlockElim.cpp | 128 MachineDominatorTree *MDT = getAnalysisIfAvailable<MachineDominatorTree>();
149 if (MDT && MDT->getNode(BB)) MDT->eraseNode(BB);
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| LiveDebugVariables.cpp | 224 /// @param MDT Dominator tree.
228 LiveIntervals &LIS, MachineDominatorTree &MDT,
247 LiveIntervals &LIS, MachineDominatorTree &MDT,
282 MachineDominatorTree *MDT;
492 LiveIntervals &LIS, MachineDominatorTree &MDT,
541 MDT.getNode(MBB)->getChildren();
627 MachineDominatorTree &MDT,
643 extendDef(Idx, LocNo, 0, 0, 0, LIS, MDT, UVS);
656 extendDef(Idx, LocNo, LI, VNI, &Kills, LIS, MDT, UVS);
667 extendDef(Idx, LocNo, LI, VNI, 0, LIS, MDT, UVS)
[all...] |
| PostRASchedulerList.cpp | 132 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
195 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
199 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), AA(AA),
256 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
289 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
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| SplitKit.h | 215 MachineDominatorTree &MDT;
|
| LiveRangeCalc.cpp | 23 MachineDominatorTree *MDT,
28 DomTree = MDT;
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| MachineBasicBlock.cpp | 857 if (MachineDominatorTree *MDT =
860 MachineDomTreeNode *SucccDTNode = MDT->getNode(Succ);
868 if (!MDT->dominates(SucccDTNode, MDT->getNode(PredBB))) {
875 MachineDomTreeNode *NewDTNode = MDT->addNewBlock(NMBB, this);
881 MDT->changeImmediateDominator(SucccDTNode, NewDTNode);
[all...] |
| SplitKit.cpp | 328 MachineDominatorTree &mdt)
331 MDT(mdt),
348 LRCalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
351 LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
680 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
684 MachineDomTreeNode *DefDomNode = MDT[DefMBB];
719 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
722 if (!IDom || !MDT.dominates(DefDomNode, IDom))
782 MDT.findNearestCommonDominator(Dom.first, ValMBB)
[all...] |
| InlineSpiller.cpp | 59 MachineDominatorTree &MDT;
143 MDT(pass.getAnalysis<MachineDominatorTree>()),
440 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
[all...] |
| MachineScheduler.cpp | 73 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
198 MDT = &getAnalysis<MachineDominatorTree>();
[all...] |
| ScheduleDAGInstrs.cpp | 47 const MachineDominatorTree &mdt,
50 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis),
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| DFAPacketizer.h | 111 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
|
| MachineScheduler.h | 53 const MachineDominatorTree *MDT;
256 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
|
| ScheduleDAGInstrs.h | 72 const MachineDominatorTree &MDT;
143 const MachineDominatorTree &mdt,
|
| /external/v8/test/mjsunit/ |
| date-parse.js | 185 // MDT = UT minus 6 hours.
187 'Sat, 01-Jan-2000 02:00:00 MDT',
188 'Sat, 01 Jan 2000 02:00:00 MDT',
189 'Saturday, 01-Jan-00 02:00:00 MDT',
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 66 MachineDominatorTree *MDT;
303 MDT = &getAnalysis<MachineDominatorTree>();
600 if (!MDT->properlyDominates(DefBB, Header))
607 if (!MDT->properlyDominates(DefBB, Header))
[all...] |
| HexagonVLIWPacketizer.cpp | 102 MachineDominatorTree &MDT);
158 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
159 : VLIWPacketizerList(MF, MLI, MDT, true){
165 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
168 HexagonPacketizerList Packetizer(Fn, MLI, MDT);
[all...] |
