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Searched
refs:ResultReg
(Results
1 - 3
of
3
) sorted by null
/external/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp
391
unsigned
ResultReg
= FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
394
if (
ResultReg
== 0) return false;
397
UpdateValueMap(I,
ResultReg
);
427
unsigned
ResultReg
= FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
429
if (
ResultReg
== 0) return false;
432
UpdateValueMap(I,
ResultReg
);
438
unsigned
ResultReg
= FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
440
if (
ResultReg
!= 0) {
442
UpdateValueMap(I,
ResultReg
);
455
unsigned
ResultReg
= FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT()
[
all
...]
/external/llvm/lib/Target/X86/
X86FastISel.cpp
91
unsigned &
ResultReg
);
181
unsigned &
ResultReg
) {
228
ResultReg
= createResultReg(RC);
230
DL, TII.get(Opc),
ResultReg
), AM);
328
unsigned &
ResultReg
) {
334
ResultReg
= RR;
852
unsigned
ResultReg
= 0;
853
if (X86FastEmitLoad(VT, AM,
ResultReg
)) {
854
UpdateValueMap(I,
ResultReg
);
937
unsigned
ResultReg
= createResultReg(&X86::GR8RegClass)
[
all
...]
/external/llvm/lib/Target/ARM/
ARMFastISel.cpp
182
bool ARMEmitLoad(MVT VT, unsigned &
ResultReg
, Address &Addr,
295
unsigned
ResultReg
= createResultReg(RC);
298
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II,
ResultReg
));
299
return
ResultReg
;
305
unsigned
ResultReg
= createResultReg(RC);
309
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II,
ResultReg
)
315
TII.get(TargetOpcode::COPY),
ResultReg
)
318
return
ResultReg
;
325
unsigned
ResultReg
= createResultReg(RC);
329
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II,
ResultReg
)
[
all
...]
Completed in 71 milliseconds