| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerProxy.h | 80 int Rd, int Rn,
83 int Rd, int Rm, int Rs, int Rn);
97 virtual void BX(int cc, int Rn);
105 int Rn, uint32_t offset = __immed12_pre(0));
107 int Rn, uint32_t offset = __immed12_pre(0));
109 int Rn, uint32_t offset = __immed12_pre(0));
111 int Rn, uint32_t offset = __immed12_pre(0));
113 int Rn, uint32_t offset = __immed8_pre(0));
115 int Rn, uint32_t offset = __immed8_pre(0));
117 int Rn, uint32_t offset = __immed8_pre(0))
[all...] |
| ARMAssemblerInterface.h | 123 int Rd, int Rn,
128 int Rd, int Rm, int Rs, int Rn) = 0;
143 virtual void BX(int cc, int Rn) = 0;
154 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
156 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
158 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
160 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
163 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
165 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
167 int Rn, uint32_t offset = __immed8_pre(0)) = 0
[all...] |
| ARMAssemblerProxy.cpp | 161 int Rd, int Rn, uint32_t Op2)
163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2);
166 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) {
167 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn);
195 void ARMAssemblerProxy::BX(int cc, int Rn) {
196 mTarget->BX(cc, Rn);
212 void ARMAssemblerProxy::LDR(int cc, int Rd, int Rn, uint32_t offset) {
213 mTarget->LDR(cc, Rd, Rn, offset);
215 void ARMAssemblerProxy::LDRB(int cc, int Rd, int Rn, uint32_t offset) {
216 mTarget->LDRB(cc, Rd, Rn, offset)
[all...] |
| ARMAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
108 virtual void BX(int cc, int Rn);
116 int Rn, uint32_t offset = __immed12_pre(0));
118 int Rn, uint32_t offset = __immed12_pre(0));
120 int Rn, uint32_t offset = __immed12_pre(0));
122 int Rn, uint32_t offset = __immed12_pre(0));
124 int Rn, uint32_t offset = __immed8_pre(0));
126 int Rn, uint32_t offset = __immed8_pre(0));
128 int Rn, uint32_t offset = __immed8_pre(0))
[all...] |
| ARMAssembler.cpp | 217 int s, int Rd, int Rn, uint32_t Op2)
219 *mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2;
229 int Rd, int Rm, int Rs, int Rn) {
231 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
233 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
288 void ARMAssembler::BX(int cc, int Rn)
290 *mPC++ = (cc<<28) | 0x12FFF10 | Rn;
299 void ARMAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset) {
300 *mPC++ = (cc<<28) | (1<<26) | (1<<20) | (Rn<<16) | (Rd<<12) | offset;
302 void ARMAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
[all...] |
| MIPSAssembler.cpp | 418 int s, int Rd, int Rn, uint32_t Op2)
435 mMips->AND(Rd, Rn, src);
437 mMips->ANDI(Rd, Rn, src);
444 mMips->ADDU(Rd, Rn, src);
446 mMips->ADDIU(Rd, Rn, src);
453 mMips->SUBU(Rd, Rn, src);
455 mMips->SUBIU(Rd, Rn, src);
461 mMips->XOR(Rd, Rn, src);
463 mMips->XORI(Rd, Rn, src);
469 mMips->OR(Rd, Rn, src)
[all...] |
| MIPSAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
108 virtual void BX(int cc, int Rn);
116 int Rn, uint32_t offset = 0);
118 int Rn, uint32_t offset = 0);
120 int Rn, uint32_t offset = 0);
122 int Rn, uint32_t offset = 0);
124 int Rn, uint32_t offset = 0);
126 int Rn, uint32_t offset = 0);
128 int Rn, uint32_t offset = 0)
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/qemu/ |
| trace.c | 896 int Rn = (insn >> 12) & 15;
899 result += _interlock_use(Rn);
901 if (Rn != 0) /* UNDEFINED */
934 int Rn = (insn >> 16) & 15;
936 result += _interlock_use(Rn) + _interlock_use(Rm);
943 int Rn = (insn >> 16) & 15;
945 result += _interlock_use(Rn);
957 int Rn = (insn >> 16) & 15;
959 result += _interlock_use(Rn) + _interlock_use(Rm);
970 int Rn = (insn >> 16) & 15
[all...] |
| arm-dis.c | 1742 int rn = (given >> 16) & 0xf; local
2071 const char *rn = arm_regnames [(given >> 16) & 0xf]; local
2284 int rn = ((given >> 16) & 0xf); local
2314 int rn = ((given >> 16) & 0xf); local
2389 int rn = ((given >> 16) & 0xf); local
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 458 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
478 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
483 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
552 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
557 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
560 DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder);
576 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
589 // Rn_wb, Rt, Rt2, Rn, Imm
590 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
599 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 722 // [Rn, Rm]
724 // {2-0} = Rn
727 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
729 return (Rm << 3) | Rn;
744 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
824 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/v8/src/arm/ |
| disasm-arm.cc | 324 if (format[1] == 'n') { // 'rn: Rn register
692 // Rn field to encode it.
693 Format(instr, "mul'cond's 'rn, 'rm, 'rs");
696 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
697 // Rn field to encode the Rd register and the Rd field to encode
698 // the Rn register.
699 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
703 // when referring to the target registers. They are mapped to the Rn
706 // RdHi == Rn fiel
[all...] |
| /external/valgrind/main/none/tests/arm/ |
| vfp.stdout.exp | [all...] |
| v6intThumb.stdout.exp | 2 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
3 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
4 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
5 cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
6 cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
7 cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
8 cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
9 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
10 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
11 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
