| /external/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 28 /// should be pointing where the caller wants code generated, e.g. at the srem
44 // ; %srem = sub i32 %xored, %dividend_sgn
53 Value *SRem = Builder.CreateSub(Xored, DividendSign);
58 return SRem;
335 assert((Rem->getOpcode() == Instruction::SRem ||
342 if (Rem->getOpcode() == Instruction::SRem) {
430 assert((Rem->getOpcode() == Instruction::SRem ||
456 if (Rem->getOpcode() == Instruction::SRem) {
|
| BypassSlowDivision.cpp | 233 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem;
235 Opcode == Instruction::SRem;
|
| SimplifyIndVar.cpp | 244 bool IsSigned = Rem->getOpcode() == Instruction::SRem;
|
| /external/llvm/unittests/Transforms/Utils/ |
| IntegerDivision.cpp | 82 TEST(IntegerDivision, SRem) {
101 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem);
|
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 116 case Instruction::SRem:
|
| ValueTracking.cpp | 546 case Instruction::SRem:
553 // The low bits of the first operand are unchanged by the srem.
[all...] |
| InstructionSimplify.cpp | [all...] |
| /external/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCUtil.cpp | 207 case Instruction::SRem: case Instruction::URem: case Instruction::FRem:
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCompares.cpp | [all...] |
| InstCombineSimplifyDemanded.cpp | 715 case Instruction::SRem:
723 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
732 // The low bits of LHS are unchanged by the srem.
[all...] |
| /external/llvm/lib/IR/ |
| ConstantFold.cpp | [all...] |
| Instruction.cpp | 208 case SRem: return "srem";
|
| Constants.cpp | 264 case Instruction::SRem:
[all...] |
| /external/llvm/include/llvm/Support/ |
| PatternMatch.h | 454 inline BinaryOp_match<LHS, RHS, Instruction::SRem>
456 return BinaryOp_match<LHS, RHS, Instruction::SRem>(L, R);
|
| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | 697 case Instruction::SRem:
715 case Instruction::SRem:GV.IntVal = LHS.IntVal.srem(RHS.IntVal); break;
[all...] |
| /external/llvm/lib/Target/CppBackend/ |
| CPPBackend.cpp | 867 case Instruction::SRem: Out << "getSRem("; break;
[all...] |
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | 540 case Instruction::SRem: R.IntVal = Src1.IntVal.srem(Src2.IntVal); break;
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | 227 case Instruction::SRem:
240 case Instruction::SRem: return MCBinaryExpr::CreateMod(LHS, RHS, Ctx);
[all...] |
| /external/llvm/lib/AsmParser/ |
| LLLexer.cpp | 642 INSTKEYWORD(urem, URem); INSTKEYWORD(srem, SRem); INSTKEYWORD(frem, FRem);
|
| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 345 case 5:{Op = (isFloat?Instruction::FRem : Instruction::SRem); break; }
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | [all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| LoopVectorize.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 769 case ISD::SREM:
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 179 I->getOpcode() == Instruction::SRem ||
[all...] |
