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      1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
     11 // machine basic blocks. For each instruction I in BB, the packetizer consults
     12 // the DFA to see if machine resources are available to execute I. If so, the
     13 // packetizer checks if I depends on any instruction J in the current packet.
     14 // If no dependency is found, I is added to current packet and machine resource
     15 // is marked as taken. If any dependency is found, a target API call is made to
     16 // prune the dependence.
     17 //
     18 //===----------------------------------------------------------------------===//
     19 #define DEBUG_TYPE "packets"
     20 #include "llvm/CodeGen/DFAPacketizer.h"
     21 #include "llvm/CodeGen/Passes.h"
     22 #include "llvm/CodeGen/MachineDominators.h"
     23 #include "llvm/CodeGen/MachineFunctionPass.h"
     24 #include "llvm/CodeGen/MachineLoopInfo.h"
     25 #include "llvm/CodeGen/ScheduleDAG.h"
     26 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
     27 #include "llvm/CodeGen/LatencyPriorityQueue.h"
     28 #include "llvm/CodeGen/SchedulerRegistry.h"
     29 #include "llvm/CodeGen/MachineFrameInfo.h"
     30 #include "llvm/CodeGen/MachineInstrBuilder.h"
     31 #include "llvm/CodeGen/MachineRegisterInfo.h"
     32 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
     33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
     34 #include "llvm/Target/TargetMachine.h"
     35 #include "llvm/Target/TargetInstrInfo.h"
     36 #include "llvm/Target/TargetRegisterInfo.h"
     37 #include "llvm/ADT/DenseMap.h"
     38 #include "llvm/ADT/Statistic.h"
     39 #include "llvm/Support/MathExtras.h"
     40 #include "llvm/MC/MCInstrItineraries.h"
     41 #include "llvm/Support/Compiler.h"
     42 #include "llvm/Support/CommandLine.h"
     43 #include "llvm/Support/Debug.h"
     44 #include "Hexagon.h"
     45 #include "HexagonTargetMachine.h"
     46 #include "HexagonRegisterInfo.h"
     47 #include "HexagonSubtarget.h"
     48 #include "HexagonMachineFunctionInfo.h"
     49 
     50 #include <map>
     51 
     52 using namespace llvm;
     53 
     54 namespace {
     55   class HexagonPacketizer : public MachineFunctionPass {
     56 
     57   public:
     58     static char ID;
     59     HexagonPacketizer() : MachineFunctionPass(ID) {}
     60 
     61     void getAnalysisUsage(AnalysisUsage &AU) const {
     62       AU.setPreservesCFG();
     63       AU.addRequired<MachineDominatorTree>();
     64       AU.addPreserved<MachineDominatorTree>();
     65       AU.addRequired<MachineLoopInfo>();
     66       AU.addPreserved<MachineLoopInfo>();
     67       MachineFunctionPass::getAnalysisUsage(AU);
     68     }
     69 
     70     const char *getPassName() const {
     71       return "Hexagon Packetizer";
     72     }
     73 
     74     bool runOnMachineFunction(MachineFunction &Fn);
     75   };
     76   char HexagonPacketizer::ID = 0;
     77 
     78   class HexagonPacketizerList : public VLIWPacketizerList {
     79 
     80   private:
     81 
     82     // Has the instruction been promoted to a dot-new instruction.
     83     bool PromotedToDotNew;
     84 
     85     // Has the instruction been glued to allocframe.
     86     bool GlueAllocframeStore;
     87 
     88     // Has the feeder instruction been glued to new value jump.
     89     bool GlueToNewValueJump;
     90 
     91     // Check if there is a dependence between some instruction already in this
     92     // packet and this instruction.
     93     bool Dependence;
     94 
     95     // Only check for dependence if there are resources available to
     96     // schedule this instruction.
     97     bool FoundSequentialDependence;
     98 
     99   public:
    100     // Ctor.
    101     HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
    102                           MachineDominatorTree &MDT);
    103 
    104     // initPacketizerState - initialize some internal flags.
    105     void initPacketizerState();
    106 
    107     // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
    108     bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
    109 
    110     // isSoloInstruction - return true if instruction MI can not be packetized
    111     // with any other instruction, which means that MI itself is a packet.
    112     bool isSoloInstruction(MachineInstr *MI);
    113 
    114     // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
    115     // together.
    116     bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
    117 
    118     // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
    119     // and SUJ.
    120     bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
    121 
    122     MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
    123   private:
    124     bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
    125     bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
    126                     MachineBasicBlock::iterator &MII,
    127                     const TargetRegisterClass* RC);
    128     bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
    129                     unsigned DepReg,
    130                     std::map <MachineInstr*, SUnit*> MIToSUnit,
    131                     MachineBasicBlock::iterator &MII,
    132                     const TargetRegisterClass* RC);
    133     bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
    134                     unsigned DepReg,
    135                     std::map <MachineInstr*, SUnit*> MIToSUnit,
    136                     MachineBasicBlock::iterator &MII);
    137     bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
    138                     unsigned DepReg,
    139                     std::map <MachineInstr*, SUnit*> MIToSUnit);
    140     bool DemoteToDotOld(MachineInstr* MI);
    141     bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
    142                     std::map <MachineInstr*, SUnit*> MIToSUnit);
    143     bool RestrictingDepExistInPacket(MachineInstr*,
    144                     unsigned, std::map <MachineInstr*, SUnit*>);
    145     bool isNewifiable(MachineInstr* MI);
    146     bool isCondInst(MachineInstr* MI);
    147     bool IsNewifyStore (MachineInstr* MI);
    148     bool tryAllocateResourcesForConstExt(MachineInstr* MI);
    149     bool canReserveResourcesForConstExt(MachineInstr *MI);
    150     void reserveResourcesForConstExt(MachineInstr* MI);
    151     bool isNewValueInst(MachineInstr* MI);
    152     bool isDotNewInst(MachineInstr* MI);
    153   };
    154 }
    155 
    156 // HexagonPacketizerList Ctor.
    157 HexagonPacketizerList::HexagonPacketizerList(
    158   MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
    159   : VLIWPacketizerList(MF, MLI, MDT, true){
    160 }
    161 
    162 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
    163   const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
    164   MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
    165   MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
    166 
    167   // Instantiate the packetizer.
    168   HexagonPacketizerList Packetizer(Fn, MLI, MDT);
    169 
    170   // DFA state table should not be empty.
    171   assert(Packetizer.getResourceTracker() && "Empty DFA table!");
    172 
    173   //
    174   // Loop over all basic blocks and remove KILL pseudo-instructions
    175   // These instructions confuse the dependence analysis. Consider:
    176   // D0 = ...   (Insn 0)
    177   // R0 = KILL R0, D0 (Insn 1)
    178   // R0 = ... (Insn 2)
    179   // Here, Insn 1 will result in the dependence graph not emitting an output
    180   // dependence between Insn 0 and Insn 2. This can lead to incorrect
    181   // packetization
    182   //
    183   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
    184        MBB != MBBe; ++MBB) {
    185     MachineBasicBlock::iterator End = MBB->end();
    186     MachineBasicBlock::iterator MI = MBB->begin();
    187     while (MI != End) {
    188       if (MI->isKill()) {
    189         MachineBasicBlock::iterator DeleteMI = MI;
    190         ++MI;
    191         MBB->erase(DeleteMI);
    192         End = MBB->end();
    193         continue;
    194       }
    195       ++MI;
    196     }
    197   }
    198 
    199   // Loop over all of the basic blocks.
    200   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
    201        MBB != MBBe; ++MBB) {
    202     // Find scheduling regions and schedule / packetize each region.
    203     unsigned RemainingCount = MBB->size();
    204     for(MachineBasicBlock::iterator RegionEnd = MBB->end();
    205         RegionEnd != MBB->begin();) {
    206       // The next region starts above the previous region. Look backward in the
    207       // instruction stream until we find the nearest boundary.
    208       MachineBasicBlock::iterator I = RegionEnd;
    209       for(;I != MBB->begin(); --I, --RemainingCount) {
    210         if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
    211           break;
    212       }
    213       I = MBB->begin();
    214 
    215       // Skip empty scheduling regions.
    216       if (I == RegionEnd) {
    217         RegionEnd = llvm::prior(RegionEnd);
    218         --RemainingCount;
    219         continue;
    220       }
    221       // Skip regions with one instruction.
    222       if (I == llvm::prior(RegionEnd)) {
    223         RegionEnd = llvm::prior(RegionEnd);
    224         continue;
    225       }
    226 
    227       Packetizer.PacketizeMIs(MBB, I, RegionEnd);
    228       RegionEnd = I;
    229     }
    230   }
    231 
    232   return true;
    233 }
    234 
    235 
    236 static bool IsIndirectCall(MachineInstr* MI) {
    237   return ((MI->getOpcode() == Hexagon::CALLR) ||
    238           (MI->getOpcode() == Hexagon::CALLRv3));
    239 }
    240 
    241 // Reserve resources for constant extender. Trigure an assertion if
    242 // reservation fail.
    243 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
    244   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
    245   MachineFunction *MF = MI->getParent()->getParent();
    246   MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
    247                                                   MI->getDebugLoc());
    248 
    249   if (ResourceTracker->canReserveResources(PseudoMI)) {
    250     ResourceTracker->reserveResources(PseudoMI);
    251     MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
    252   } else {
    253     MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
    254     llvm_unreachable("can not reserve resources for constant extender.");
    255   }
    256   return;
    257 }
    258 
    259 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
    260   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
    261   assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
    262          "Should only be called for constant extended instructions");
    263   MachineFunction *MF = MI->getParent()->getParent();
    264   MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
    265                                                   MI->getDebugLoc());
    266   bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
    267   MF->DeleteMachineInstr(PseudoMI);
    268   return CanReserve;
    269 }
    270 
    271 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
    272 // true, otherwise, return false.
    273 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
    274   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
    275   MachineFunction *MF = MI->getParent()->getParent();
    276   MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
    277                                                   MI->getDebugLoc());
    278 
    279   if (ResourceTracker->canReserveResources(PseudoMI)) {
    280     ResourceTracker->reserveResources(PseudoMI);
    281     MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
    282     return true;
    283   } else {
    284     MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
    285     return false;
    286   }
    287 }
    288 
    289 
    290 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
    291                                           SDep::Kind DepType,
    292                                           unsigned DepReg) {
    293 
    294   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
    295   const HexagonRegisterInfo* QRI =
    296               (const HexagonRegisterInfo *) TM.getRegisterInfo();
    297 
    298   // Check for lr dependence
    299   if (DepReg == QRI->getRARegister()) {
    300     return true;
    301   }
    302 
    303   if (QII->isDeallocRet(MI)) {
    304     if (DepReg == QRI->getFrameRegister() ||
    305         DepReg == QRI->getStackRegister())
    306       return true;
    307   }
    308 
    309   // Check if this is a predicate dependence
    310   const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
    311   if (RC == &Hexagon::PredRegsRegClass) {
    312     return true;
    313   }
    314 
    315   //
    316   // Lastly check for an operand used in an indirect call
    317   // If we had an attribute for checking if an instruction is an indirect call,
    318   // then we could have avoided this relatively brittle implementation of
    319   // IsIndirectCall()
    320   //
    321   // Assumes that the first operand of the CALLr is the function address
    322   //
    323   if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
    324     MachineOperand MO = MI->getOperand(0);
    325     if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
    326       return true;
    327     }
    328   }
    329 
    330   return false;
    331 }
    332 
    333 static bool IsRegDependence(const SDep::Kind DepType) {
    334   return (DepType == SDep::Data || DepType == SDep::Anti ||
    335           DepType == SDep::Output);
    336 }
    337 
    338 static bool IsDirectJump(MachineInstr* MI) {
    339   return (MI->getOpcode() == Hexagon::JMP);
    340 }
    341 
    342 static bool IsSchedBarrier(MachineInstr* MI) {
    343   switch (MI->getOpcode()) {
    344   case Hexagon::BARRIER:
    345     return true;
    346   }
    347   return false;
    348 }
    349 
    350 static bool IsControlFlow(MachineInstr* MI) {
    351   return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
    352 }
    353 
    354 // Function returns true if an instruction can be promoted to the new-value
    355 // store. It will always return false for v2 and v3.
    356 // It lists all the conditional and unconditional stores that can be promoted
    357 // to the new-value stores.
    358 
    359 bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
    360   const HexagonRegisterInfo* QRI =
    361                           (const HexagonRegisterInfo *) TM.getRegisterInfo();
    362   switch (MI->getOpcode())
    363   {
    364     // store byte
    365     case Hexagon::STrib:
    366     case Hexagon::STrib_indexed:
    367     case Hexagon::STrib_indexed_shl_V4:
    368     case Hexagon::STrib_shl_V4:
    369     case Hexagon::STb_GP_V4:
    370     case Hexagon::POST_STbri:
    371     case Hexagon::STrib_cPt:
    372     case Hexagon::STrib_cdnPt_V4:
    373     case Hexagon::STrib_cNotPt:
    374     case Hexagon::STrib_cdnNotPt_V4:
    375     case Hexagon::STrib_indexed_cPt:
    376     case Hexagon::STrib_indexed_cdnPt_V4:
    377     case Hexagon::STrib_indexed_cNotPt:
    378     case Hexagon::STrib_indexed_cdnNotPt_V4:
    379     case Hexagon::STrib_indexed_shl_cPt_V4:
    380     case Hexagon::STrib_indexed_shl_cdnPt_V4:
    381     case Hexagon::STrib_indexed_shl_cNotPt_V4:
    382     case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
    383     case Hexagon::POST_STbri_cPt:
    384     case Hexagon::POST_STbri_cdnPt_V4:
    385     case Hexagon::POST_STbri_cNotPt:
    386     case Hexagon::POST_STbri_cdnNotPt_V4:
    387     case Hexagon::STb_GP_cPt_V4:
    388     case Hexagon::STb_GP_cNotPt_V4:
    389     case Hexagon::STb_GP_cdnPt_V4:
    390     case Hexagon::STb_GP_cdnNotPt_V4:
    391 
    392     // store halfword
    393     case Hexagon::STrih:
    394     case Hexagon::STrih_indexed:
    395     case Hexagon::STrih_indexed_shl_V4:
    396     case Hexagon::STrih_shl_V4:
    397     case Hexagon::STh_GP_V4:
    398     case Hexagon::POST_SThri:
    399     case Hexagon::STrih_cPt:
    400     case Hexagon::STrih_cdnPt_V4:
    401     case Hexagon::STrih_cNotPt:
    402     case Hexagon::STrih_cdnNotPt_V4:
    403     case Hexagon::STrih_indexed_cPt:
    404     case Hexagon::STrih_indexed_cdnPt_V4:
    405     case Hexagon::STrih_indexed_cNotPt:
    406     case Hexagon::STrih_indexed_cdnNotPt_V4:
    407     case Hexagon::STrih_indexed_shl_cPt_V4:
    408     case Hexagon::STrih_indexed_shl_cdnPt_V4:
    409     case Hexagon::STrih_indexed_shl_cNotPt_V4:
    410     case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
    411     case Hexagon::POST_SThri_cPt:
    412     case Hexagon::POST_SThri_cdnPt_V4:
    413     case Hexagon::POST_SThri_cNotPt:
    414     case Hexagon::POST_SThri_cdnNotPt_V4:
    415     case Hexagon::STh_GP_cPt_V4:
    416     case Hexagon::STh_GP_cNotPt_V4:
    417     case Hexagon::STh_GP_cdnPt_V4:
    418     case Hexagon::STh_GP_cdnNotPt_V4:
    419 
    420     // store word
    421     case Hexagon::STriw:
    422     case Hexagon::STriw_indexed:
    423     case Hexagon::STriw_indexed_shl_V4:
    424     case Hexagon::STriw_shl_V4:
    425     case Hexagon::STw_GP_V4:
    426     case Hexagon::POST_STwri:
    427     case Hexagon::STriw_cPt:
    428     case Hexagon::STriw_cdnPt_V4:
    429     case Hexagon::STriw_cNotPt:
    430     case Hexagon::STriw_cdnNotPt_V4:
    431     case Hexagon::STriw_indexed_cPt:
    432     case Hexagon::STriw_indexed_cdnPt_V4:
    433     case Hexagon::STriw_indexed_cNotPt:
    434     case Hexagon::STriw_indexed_cdnNotPt_V4:
    435     case Hexagon::STriw_indexed_shl_cPt_V4:
    436     case Hexagon::STriw_indexed_shl_cdnPt_V4:
    437     case Hexagon::STriw_indexed_shl_cNotPt_V4:
    438     case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
    439     case Hexagon::POST_STwri_cPt:
    440     case Hexagon::POST_STwri_cdnPt_V4:
    441     case Hexagon::POST_STwri_cNotPt:
    442     case Hexagon::POST_STwri_cdnNotPt_V4:
    443     case Hexagon::STw_GP_cPt_V4:
    444     case Hexagon::STw_GP_cNotPt_V4:
    445     case Hexagon::STw_GP_cdnPt_V4:
    446     case Hexagon::STw_GP_cdnNotPt_V4:
    447         return QRI->Subtarget.hasV4TOps();
    448   }
    449   return false;
    450 }
    451 
    452 static bool IsLoopN(MachineInstr *MI) {
    453   return (MI->getOpcode() == Hexagon::LOOP0_i ||
    454           MI->getOpcode() == Hexagon::LOOP0_r);
    455 }
    456 
    457 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
    458 /// callee-saved register.
    459 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
    460                                      const TargetRegisterInfo *TRI) {
    461   for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
    462     unsigned CalleeSavedReg = *CSR;
    463     if (MI->modifiesRegister(CalleeSavedReg, TRI))
    464       return true;
    465   }
    466   return false;
    467 }
    468 
    469 // Return the new value instruction for a given store.
    470 static int GetDotNewOp(const int opc) {
    471   switch (opc) {
    472   default: llvm_unreachable("Unknown .new type");
    473   // store new value byte
    474   case Hexagon::STrib:
    475     return Hexagon::STrib_nv_V4;
    476 
    477   case Hexagon::STrib_indexed:
    478     return Hexagon::STrib_indexed_nv_V4;
    479 
    480   case Hexagon::STrib_indexed_shl_V4:
    481     return Hexagon::STrib_indexed_shl_nv_V4;
    482 
    483   case Hexagon::STrib_shl_V4:
    484     return Hexagon::STrib_shl_nv_V4;
    485 
    486   case Hexagon::STb_GP_V4:
    487     return Hexagon::STb_GP_nv_V4;
    488 
    489   case Hexagon::POST_STbri:
    490     return Hexagon::POST_STbri_nv_V4;
    491 
    492   case Hexagon::STrib_cPt:
    493     return Hexagon::STrib_cPt_nv_V4;
    494 
    495   case Hexagon::STrib_cdnPt_V4:
    496     return Hexagon::STrib_cdnPt_nv_V4;
    497 
    498   case Hexagon::STrib_cNotPt:
    499     return Hexagon::STrib_cNotPt_nv_V4;
    500 
    501   case Hexagon::STrib_cdnNotPt_V4:
    502     return Hexagon::STrib_cdnNotPt_nv_V4;
    503 
    504   case Hexagon::STrib_indexed_cPt:
    505     return Hexagon::STrib_indexed_cPt_nv_V4;
    506 
    507   case Hexagon::STrib_indexed_cdnPt_V4:
    508     return Hexagon::STrib_indexed_cdnPt_nv_V4;
    509 
    510   case Hexagon::STrib_indexed_cNotPt:
    511     return Hexagon::STrib_indexed_cNotPt_nv_V4;
    512 
    513   case Hexagon::STrib_indexed_cdnNotPt_V4:
    514     return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
    515 
    516   case Hexagon::STrib_indexed_shl_cPt_V4:
    517     return Hexagon::STrib_indexed_shl_cPt_nv_V4;
    518 
    519   case Hexagon::STrib_indexed_shl_cdnPt_V4:
    520     return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
    521 
    522   case Hexagon::STrib_indexed_shl_cNotPt_V4:
    523     return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
    524 
    525   case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
    526     return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
    527 
    528   case Hexagon::POST_STbri_cPt:
    529     return Hexagon::POST_STbri_cPt_nv_V4;
    530 
    531   case Hexagon::POST_STbri_cdnPt_V4:
    532     return Hexagon::POST_STbri_cdnPt_nv_V4;
    533 
    534   case Hexagon::POST_STbri_cNotPt:
    535     return Hexagon::POST_STbri_cNotPt_nv_V4;
    536 
    537   case Hexagon::POST_STbri_cdnNotPt_V4:
    538     return Hexagon::POST_STbri_cdnNotPt_nv_V4;
    539 
    540   case Hexagon::STb_GP_cPt_V4:
    541     return Hexagon::STb_GP_cPt_nv_V4;
    542 
    543   case Hexagon::STb_GP_cNotPt_V4:
    544     return Hexagon::STb_GP_cNotPt_nv_V4;
    545 
    546   case Hexagon::STb_GP_cdnPt_V4:
    547     return Hexagon::STb_GP_cdnPt_nv_V4;
    548 
    549   case Hexagon::STb_GP_cdnNotPt_V4:
    550     return Hexagon::STb_GP_cdnNotPt_nv_V4;
    551 
    552   // store new value halfword
    553   case Hexagon::STrih:
    554     return Hexagon::STrih_nv_V4;
    555 
    556   case Hexagon::STrih_indexed:
    557     return Hexagon::STrih_indexed_nv_V4;
    558 
    559   case Hexagon::STrih_indexed_shl_V4:
    560     return Hexagon::STrih_indexed_shl_nv_V4;
    561 
    562   case Hexagon::STrih_shl_V4:
    563     return Hexagon::STrih_shl_nv_V4;
    564 
    565   case Hexagon::STh_GP_V4:
    566     return Hexagon::STh_GP_nv_V4;
    567 
    568   case Hexagon::POST_SThri:
    569     return Hexagon::POST_SThri_nv_V4;
    570 
    571   case Hexagon::STrih_cPt:
    572     return Hexagon::STrih_cPt_nv_V4;
    573 
    574   case Hexagon::STrih_cdnPt_V4:
    575     return Hexagon::STrih_cdnPt_nv_V4;
    576 
    577   case Hexagon::STrih_cNotPt:
    578     return Hexagon::STrih_cNotPt_nv_V4;
    579 
    580   case Hexagon::STrih_cdnNotPt_V4:
    581     return Hexagon::STrih_cdnNotPt_nv_V4;
    582 
    583   case Hexagon::STrih_indexed_cPt:
    584     return Hexagon::STrih_indexed_cPt_nv_V4;
    585 
    586   case Hexagon::STrih_indexed_cdnPt_V4:
    587     return Hexagon::STrih_indexed_cdnPt_nv_V4;
    588 
    589   case Hexagon::STrih_indexed_cNotPt:
    590     return Hexagon::STrih_indexed_cNotPt_nv_V4;
    591 
    592   case Hexagon::STrih_indexed_cdnNotPt_V4:
    593     return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
    594 
    595   case Hexagon::STrih_indexed_shl_cPt_V4:
    596     return Hexagon::STrih_indexed_shl_cPt_nv_V4;
    597 
    598   case Hexagon::STrih_indexed_shl_cdnPt_V4:
    599     return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
    600 
    601   case Hexagon::STrih_indexed_shl_cNotPt_V4:
    602     return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
    603 
    604   case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
    605     return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
    606 
    607   case Hexagon::POST_SThri_cPt:
    608     return Hexagon::POST_SThri_cPt_nv_V4;
    609 
    610   case Hexagon::POST_SThri_cdnPt_V4:
    611     return Hexagon::POST_SThri_cdnPt_nv_V4;
    612 
    613   case Hexagon::POST_SThri_cNotPt:
    614     return Hexagon::POST_SThri_cNotPt_nv_V4;
    615 
    616   case Hexagon::POST_SThri_cdnNotPt_V4:
    617     return Hexagon::POST_SThri_cdnNotPt_nv_V4;
    618 
    619   case Hexagon::STh_GP_cPt_V4:
    620     return Hexagon::STh_GP_cPt_nv_V4;
    621 
    622   case Hexagon::STh_GP_cNotPt_V4:
    623     return Hexagon::STh_GP_cNotPt_nv_V4;
    624 
    625   case Hexagon::STh_GP_cdnPt_V4:
    626     return Hexagon::STh_GP_cdnPt_nv_V4;
    627 
    628   case Hexagon::STh_GP_cdnNotPt_V4:
    629     return Hexagon::STh_GP_cdnNotPt_nv_V4;
    630 
    631   // store new value word
    632   case Hexagon::STriw:
    633     return Hexagon::STriw_nv_V4;
    634 
    635   case Hexagon::STriw_indexed:
    636     return Hexagon::STriw_indexed_nv_V4;
    637 
    638   case Hexagon::STriw_indexed_shl_V4:
    639     return Hexagon::STriw_indexed_shl_nv_V4;
    640 
    641   case Hexagon::STriw_shl_V4:
    642     return Hexagon::STriw_shl_nv_V4;
    643 
    644   case Hexagon::STw_GP_V4:
    645     return Hexagon::STw_GP_nv_V4;
    646 
    647   case Hexagon::POST_STwri:
    648     return Hexagon::POST_STwri_nv_V4;
    649 
    650   case Hexagon::STriw_cPt:
    651     return Hexagon::STriw_cPt_nv_V4;
    652 
    653   case Hexagon::STriw_cdnPt_V4:
    654     return Hexagon::STriw_cdnPt_nv_V4;
    655 
    656   case Hexagon::STriw_cNotPt:
    657     return Hexagon::STriw_cNotPt_nv_V4;
    658 
    659   case Hexagon::STriw_cdnNotPt_V4:
    660     return Hexagon::STriw_cdnNotPt_nv_V4;
    661 
    662   case Hexagon::STriw_indexed_cPt:
    663     return Hexagon::STriw_indexed_cPt_nv_V4;
    664 
    665   case Hexagon::STriw_indexed_cdnPt_V4:
    666     return Hexagon::STriw_indexed_cdnPt_nv_V4;
    667 
    668   case Hexagon::STriw_indexed_cNotPt:
    669     return Hexagon::STriw_indexed_cNotPt_nv_V4;
    670 
    671   case Hexagon::STriw_indexed_cdnNotPt_V4:
    672     return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
    673 
    674   case Hexagon::STriw_indexed_shl_cPt_V4:
    675     return Hexagon::STriw_indexed_shl_cPt_nv_V4;
    676 
    677   case Hexagon::STriw_indexed_shl_cdnPt_V4:
    678     return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
    679 
    680   case Hexagon::STriw_indexed_shl_cNotPt_V4:
    681     return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
    682 
    683   case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
    684     return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
    685 
    686   case Hexagon::POST_STwri_cPt:
    687     return Hexagon::POST_STwri_cPt_nv_V4;
    688 
    689   case Hexagon::POST_STwri_cdnPt_V4:
    690     return Hexagon::POST_STwri_cdnPt_nv_V4;
    691 
    692   case Hexagon::POST_STwri_cNotPt:
    693     return Hexagon::POST_STwri_cNotPt_nv_V4;
    694 
    695   case Hexagon::POST_STwri_cdnNotPt_V4:
    696     return Hexagon::POST_STwri_cdnNotPt_nv_V4;
    697 
    698   case Hexagon::STw_GP_cPt_V4:
    699     return Hexagon::STw_GP_cPt_nv_V4;
    700 
    701   case Hexagon::STw_GP_cNotPt_V4:
    702     return Hexagon::STw_GP_cNotPt_nv_V4;
    703 
    704   case Hexagon::STw_GP_cdnPt_V4:
    705     return Hexagon::STw_GP_cdnPt_nv_V4;
    706 
    707   case Hexagon::STw_GP_cdnNotPt_V4:
    708     return Hexagon::STw_GP_cdnNotPt_nv_V4;
    709 
    710   }
    711 }
    712 
    713 // Return .new predicate version for an instruction
    714 static int GetDotNewPredOp(const int opc) {
    715   switch (opc) {
    716   default: llvm_unreachable("Unknown .new type");
    717   // Conditional stores
    718   // Store byte conditionally
    719   case Hexagon::STrib_cPt :
    720     return Hexagon::STrib_cdnPt_V4;
    721 
    722   case Hexagon::STrib_cNotPt :
    723     return Hexagon::STrib_cdnNotPt_V4;
    724 
    725   case Hexagon::STrib_indexed_cPt :
    726     return Hexagon::STrib_indexed_cdnPt_V4;
    727 
    728   case Hexagon::STrib_indexed_cNotPt :
    729     return Hexagon::STrib_indexed_cdnNotPt_V4;
    730 
    731   case Hexagon::STrib_imm_cPt_V4 :
    732     return Hexagon::STrib_imm_cdnPt_V4;
    733 
    734   case Hexagon::STrib_imm_cNotPt_V4 :
    735     return Hexagon::STrib_imm_cdnNotPt_V4;
    736 
    737   case Hexagon::POST_STbri_cPt :
    738     return Hexagon::POST_STbri_cdnPt_V4;
    739 
    740   case Hexagon::POST_STbri_cNotPt :
    741     return Hexagon::POST_STbri_cdnNotPt_V4;
    742 
    743   case Hexagon::STrib_indexed_shl_cPt_V4 :
    744     return Hexagon::STrib_indexed_shl_cdnPt_V4;
    745 
    746   case Hexagon::STrib_indexed_shl_cNotPt_V4 :
    747     return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
    748 
    749   case Hexagon::STb_GP_cPt_V4 :
    750     return Hexagon::STb_GP_cdnPt_V4;
    751 
    752   case Hexagon::STb_GP_cNotPt_V4 :
    753     return Hexagon::STb_GP_cdnNotPt_V4;
    754 
    755   // Store doubleword conditionally
    756   case Hexagon::STrid_cPt :
    757     return Hexagon::STrid_cdnPt_V4;
    758 
    759   case Hexagon::STrid_cNotPt :
    760     return Hexagon::STrid_cdnNotPt_V4;
    761 
    762   case Hexagon::STrid_indexed_cPt :
    763     return Hexagon::STrid_indexed_cdnPt_V4;
    764 
    765   case Hexagon::STrid_indexed_cNotPt :
    766     return Hexagon::STrid_indexed_cdnNotPt_V4;
    767 
    768   case Hexagon::STrid_indexed_shl_cPt_V4 :
    769     return Hexagon::STrid_indexed_shl_cdnPt_V4;
    770 
    771   case Hexagon::STrid_indexed_shl_cNotPt_V4 :
    772     return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
    773 
    774   case Hexagon::POST_STdri_cPt :
    775     return Hexagon::POST_STdri_cdnPt_V4;
    776 
    777   case Hexagon::POST_STdri_cNotPt :
    778     return Hexagon::POST_STdri_cdnNotPt_V4;
    779 
    780   case Hexagon::STd_GP_cPt_V4 :
    781     return Hexagon::STd_GP_cdnPt_V4;
    782 
    783   case Hexagon::STd_GP_cNotPt_V4 :
    784     return Hexagon::STd_GP_cdnNotPt_V4;
    785 
    786   // Store halfword conditionally
    787   case Hexagon::STrih_cPt :
    788     return Hexagon::STrih_cdnPt_V4;
    789 
    790   case Hexagon::STrih_cNotPt :
    791     return Hexagon::STrih_cdnNotPt_V4;
    792 
    793   case Hexagon::STrih_indexed_cPt :
    794     return Hexagon::STrih_indexed_cdnPt_V4;
    795 
    796   case Hexagon::STrih_indexed_cNotPt :
    797     return Hexagon::STrih_indexed_cdnNotPt_V4;
    798 
    799   case Hexagon::STrih_imm_cPt_V4 :
    800     return Hexagon::STrih_imm_cdnPt_V4;
    801 
    802   case Hexagon::STrih_imm_cNotPt_V4 :
    803     return Hexagon::STrih_imm_cdnNotPt_V4;
    804 
    805   case Hexagon::STrih_indexed_shl_cPt_V4 :
    806     return Hexagon::STrih_indexed_shl_cdnPt_V4;
    807 
    808   case Hexagon::STrih_indexed_shl_cNotPt_V4 :
    809     return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
    810 
    811   case Hexagon::POST_SThri_cPt :
    812     return Hexagon::POST_SThri_cdnPt_V4;
    813 
    814   case Hexagon::POST_SThri_cNotPt :
    815     return Hexagon::POST_SThri_cdnNotPt_V4;
    816 
    817   case Hexagon::STh_GP_cPt_V4 :
    818     return Hexagon::STh_GP_cdnPt_V4;
    819 
    820   case Hexagon::STh_GP_cNotPt_V4 :
    821     return Hexagon::STh_GP_cdnNotPt_V4;
    822 
    823   // Store word conditionally
    824   case Hexagon::STriw_cPt :
    825     return Hexagon::STriw_cdnPt_V4;
    826 
    827   case Hexagon::STriw_cNotPt :
    828     return Hexagon::STriw_cdnNotPt_V4;
    829 
    830   case Hexagon::STriw_indexed_cPt :
    831     return Hexagon::STriw_indexed_cdnPt_V4;
    832 
    833   case Hexagon::STriw_indexed_cNotPt :
    834     return Hexagon::STriw_indexed_cdnNotPt_V4;
    835 
    836   case Hexagon::STriw_imm_cPt_V4 :
    837     return Hexagon::STriw_imm_cdnPt_V4;
    838 
    839   case Hexagon::STriw_imm_cNotPt_V4 :
    840     return Hexagon::STriw_imm_cdnNotPt_V4;
    841 
    842   case Hexagon::STriw_indexed_shl_cPt_V4 :
    843     return Hexagon::STriw_indexed_shl_cdnPt_V4;
    844 
    845   case Hexagon::STriw_indexed_shl_cNotPt_V4 :
    846     return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
    847 
    848   case Hexagon::POST_STwri_cPt :
    849     return Hexagon::POST_STwri_cdnPt_V4;
    850 
    851   case Hexagon::POST_STwri_cNotPt :
    852     return Hexagon::POST_STwri_cdnNotPt_V4;
    853 
    854   case Hexagon::STw_GP_cPt_V4 :
    855     return Hexagon::STw_GP_cdnPt_V4;
    856 
    857   case Hexagon::STw_GP_cNotPt_V4 :
    858     return Hexagon::STw_GP_cdnNotPt_V4;
    859 
    860   // Condtional Jumps
    861   case Hexagon::JMP_c:
    862     return Hexagon::JMP_cdnPt;
    863 
    864   case Hexagon::JMP_cNot:
    865     return Hexagon::JMP_cdnNotPt;
    866 
    867   case Hexagon::JMPR_cPt:
    868     return Hexagon::JMPR_cdnPt_V3;
    869 
    870   case Hexagon::JMPR_cNotPt:
    871     return Hexagon::JMPR_cdnNotPt_V3;
    872 
    873   // Conditional Transfers
    874   case Hexagon::TFR_cPt:
    875     return Hexagon::TFR_cdnPt;
    876 
    877   case Hexagon::TFR_cNotPt:
    878     return Hexagon::TFR_cdnNotPt;
    879 
    880   case Hexagon::TFRI_cPt:
    881     return Hexagon::TFRI_cdnPt;
    882 
    883   case Hexagon::TFRI_cNotPt:
    884     return Hexagon::TFRI_cdnNotPt;
    885 
    886   // Load double word
    887   case Hexagon::LDrid_cPt :
    888     return Hexagon::LDrid_cdnPt;
    889 
    890   case Hexagon::LDrid_cNotPt :
    891     return Hexagon::LDrid_cdnNotPt;
    892 
    893   case Hexagon::LDrid_indexed_cPt :
    894     return Hexagon::LDrid_indexed_cdnPt;
    895 
    896   case Hexagon::LDrid_indexed_cNotPt :
    897     return Hexagon::LDrid_indexed_cdnNotPt;
    898 
    899   case Hexagon::POST_LDrid_cPt :
    900     return Hexagon::POST_LDrid_cdnPt_V4;
    901 
    902   case Hexagon::POST_LDrid_cNotPt :
    903     return Hexagon::POST_LDrid_cdnNotPt_V4;
    904 
    905   // Load word
    906   case Hexagon::LDriw_cPt :
    907     return Hexagon::LDriw_cdnPt;
    908 
    909   case Hexagon::LDriw_cNotPt :
    910     return Hexagon::LDriw_cdnNotPt;
    911 
    912   case Hexagon::LDriw_indexed_cPt :
    913     return Hexagon::LDriw_indexed_cdnPt;
    914 
    915   case Hexagon::LDriw_indexed_cNotPt :
    916     return Hexagon::LDriw_indexed_cdnNotPt;
    917 
    918   case Hexagon::POST_LDriw_cPt :
    919     return Hexagon::POST_LDriw_cdnPt_V4;
    920 
    921   case Hexagon::POST_LDriw_cNotPt :
    922     return Hexagon::POST_LDriw_cdnNotPt_V4;
    923 
    924   // Load halfword
    925   case Hexagon::LDrih_cPt :
    926     return Hexagon::LDrih_cdnPt;
    927 
    928   case Hexagon::LDrih_cNotPt :
    929     return Hexagon::LDrih_cdnNotPt;
    930 
    931   case Hexagon::LDrih_indexed_cPt :
    932     return Hexagon::LDrih_indexed_cdnPt;
    933 
    934   case Hexagon::LDrih_indexed_cNotPt :
    935     return Hexagon::LDrih_indexed_cdnNotPt;
    936 
    937   case Hexagon::POST_LDrih_cPt :
    938     return Hexagon::POST_LDrih_cdnPt_V4;
    939 
    940   case Hexagon::POST_LDrih_cNotPt :
    941     return Hexagon::POST_LDrih_cdnNotPt_V4;
    942 
    943   // Load byte
    944   case Hexagon::LDrib_cPt :
    945     return Hexagon::LDrib_cdnPt;
    946 
    947   case Hexagon::LDrib_cNotPt :
    948     return Hexagon::LDrib_cdnNotPt;
    949 
    950   case Hexagon::LDrib_indexed_cPt :
    951     return Hexagon::LDrib_indexed_cdnPt;
    952 
    953   case Hexagon::LDrib_indexed_cNotPt :
    954     return Hexagon::LDrib_indexed_cdnNotPt;
    955 
    956   case Hexagon::POST_LDrib_cPt :
    957     return Hexagon::POST_LDrib_cdnPt_V4;
    958 
    959   case Hexagon::POST_LDrib_cNotPt :
    960     return Hexagon::POST_LDrib_cdnNotPt_V4;
    961 
    962   // Load unsigned halfword
    963   case Hexagon::LDriuh_cPt :
    964     return Hexagon::LDriuh_cdnPt;
    965 
    966   case Hexagon::LDriuh_cNotPt :
    967     return Hexagon::LDriuh_cdnNotPt;
    968 
    969   case Hexagon::LDriuh_indexed_cPt :
    970     return Hexagon::LDriuh_indexed_cdnPt;
    971 
    972   case Hexagon::LDriuh_indexed_cNotPt :
    973     return Hexagon::LDriuh_indexed_cdnNotPt;
    974 
    975   case Hexagon::POST_LDriuh_cPt :
    976     return Hexagon::POST_LDriuh_cdnPt_V4;
    977 
    978   case Hexagon::POST_LDriuh_cNotPt :
    979     return Hexagon::POST_LDriuh_cdnNotPt_V4;
    980 
    981   // Load unsigned byte
    982   case Hexagon::LDriub_cPt :
    983     return Hexagon::LDriub_cdnPt;
    984 
    985   case Hexagon::LDriub_cNotPt :
    986     return Hexagon::LDriub_cdnNotPt;
    987 
    988   case Hexagon::LDriub_indexed_cPt :
    989     return Hexagon::LDriub_indexed_cdnPt;
    990 
    991   case Hexagon::LDriub_indexed_cNotPt :
    992     return Hexagon::LDriub_indexed_cdnNotPt;
    993 
    994   case Hexagon::POST_LDriub_cPt :
    995     return Hexagon::POST_LDriub_cdnPt_V4;
    996 
    997   case Hexagon::POST_LDriub_cNotPt :
    998     return Hexagon::POST_LDriub_cdnNotPt_V4;
    999 
   1000   // V4 indexed+scaled load
   1001 
   1002   case Hexagon::LDrid_indexed_shl_cPt_V4 :
   1003     return Hexagon::LDrid_indexed_shl_cdnPt_V4;
   1004 
   1005   case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
   1006     return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
   1007 
   1008   case Hexagon::LDrib_indexed_shl_cPt_V4 :
   1009     return Hexagon::LDrib_indexed_shl_cdnPt_V4;
   1010 
   1011   case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
   1012     return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
   1013 
   1014   case Hexagon::LDriub_indexed_shl_cPt_V4 :
   1015     return Hexagon::LDriub_indexed_shl_cdnPt_V4;
   1016 
   1017   case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
   1018     return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
   1019 
   1020   case Hexagon::LDrih_indexed_shl_cPt_V4 :
   1021     return Hexagon::LDrih_indexed_shl_cdnPt_V4;
   1022 
   1023   case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
   1024     return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
   1025 
   1026   case Hexagon::LDriuh_indexed_shl_cPt_V4 :
   1027     return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
   1028 
   1029   case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
   1030     return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
   1031 
   1032   case Hexagon::LDriw_indexed_shl_cPt_V4 :
   1033     return Hexagon::LDriw_indexed_shl_cdnPt_V4;
   1034 
   1035   case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
   1036     return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
   1037 
   1038   // V4 global address load
   1039 
   1040   case Hexagon::LDd_GP_cPt_V4:
   1041     return Hexagon::LDd_GP_cdnPt_V4;
   1042 
   1043   case Hexagon::LDd_GP_cNotPt_V4:
   1044     return Hexagon::LDd_GP_cdnNotPt_V4;
   1045 
   1046   case Hexagon::LDb_GP_cPt_V4:
   1047     return Hexagon::LDb_GP_cdnPt_V4;
   1048 
   1049   case Hexagon::LDb_GP_cNotPt_V4:
   1050     return Hexagon::LDb_GP_cdnNotPt_V4;
   1051 
   1052   case Hexagon::LDub_GP_cPt_V4:
   1053     return Hexagon::LDub_GP_cdnPt_V4;
   1054 
   1055   case Hexagon::LDub_GP_cNotPt_V4:
   1056     return Hexagon::LDub_GP_cdnNotPt_V4;
   1057 
   1058   case Hexagon::LDh_GP_cPt_V4:
   1059     return Hexagon::LDh_GP_cdnPt_V4;
   1060 
   1061   case Hexagon::LDh_GP_cNotPt_V4:
   1062     return Hexagon::LDh_GP_cdnNotPt_V4;
   1063 
   1064   case Hexagon::LDuh_GP_cPt_V4:
   1065     return Hexagon::LDuh_GP_cdnPt_V4;
   1066 
   1067   case Hexagon::LDuh_GP_cNotPt_V4:
   1068     return Hexagon::LDuh_GP_cdnNotPt_V4;
   1069 
   1070   case Hexagon::LDw_GP_cPt_V4:
   1071     return Hexagon::LDw_GP_cdnPt_V4;
   1072 
   1073   case Hexagon::LDw_GP_cNotPt_V4:
   1074     return Hexagon::LDw_GP_cdnNotPt_V4;
   1075 
   1076   // Conditional store new-value byte
   1077   case Hexagon::STrib_cPt_nv_V4 :
   1078     return Hexagon::STrib_cdnPt_nv_V4;
   1079   case Hexagon::STrib_cNotPt_nv_V4 :
   1080     return Hexagon::STrib_cdnNotPt_nv_V4;
   1081 
   1082   case Hexagon::STrib_indexed_cPt_nv_V4 :
   1083     return Hexagon::STrib_indexed_cdnPt_nv_V4;
   1084   case Hexagon::STrib_indexed_cNotPt_nv_V4 :
   1085     return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
   1086 
   1087   case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
   1088     return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
   1089   case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
   1090     return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
   1091 
   1092   case Hexagon::POST_STbri_cPt_nv_V4 :
   1093     return Hexagon::POST_STbri_cdnPt_nv_V4;
   1094   case Hexagon::POST_STbri_cNotPt_nv_V4 :
   1095     return Hexagon::POST_STbri_cdnNotPt_nv_V4;
   1096 
   1097   case Hexagon::STb_GP_cPt_nv_V4 :
   1098     return Hexagon::STb_GP_cdnPt_nv_V4;
   1099 
   1100   case Hexagon::STb_GP_cNotPt_nv_V4 :
   1101     return Hexagon::STb_GP_cdnNotPt_nv_V4;
   1102 
   1103   // Conditional store new-value halfword
   1104   case Hexagon::STrih_cPt_nv_V4 :
   1105     return Hexagon::STrih_cdnPt_nv_V4;
   1106   case Hexagon::STrih_cNotPt_nv_V4 :
   1107     return Hexagon::STrih_cdnNotPt_nv_V4;
   1108 
   1109   case Hexagon::STrih_indexed_cPt_nv_V4 :
   1110     return Hexagon::STrih_indexed_cdnPt_nv_V4;
   1111   case Hexagon::STrih_indexed_cNotPt_nv_V4 :
   1112     return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
   1113 
   1114   case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
   1115     return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
   1116   case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
   1117     return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
   1118 
   1119   case Hexagon::POST_SThri_cPt_nv_V4 :
   1120     return Hexagon::POST_SThri_cdnPt_nv_V4;
   1121   case Hexagon::POST_SThri_cNotPt_nv_V4 :
   1122     return Hexagon::POST_SThri_cdnNotPt_nv_V4;
   1123 
   1124   case Hexagon::STh_GP_cPt_nv_V4 :
   1125     return Hexagon::STh_GP_cdnPt_nv_V4;
   1126 
   1127   case Hexagon::STh_GP_cNotPt_nv_V4 :
   1128     return Hexagon::STh_GP_cdnNotPt_nv_V4;
   1129 
   1130   // Conditional store new-value word
   1131   case Hexagon::STriw_cPt_nv_V4 :
   1132     return  Hexagon::STriw_cdnPt_nv_V4;
   1133   case Hexagon::STriw_cNotPt_nv_V4 :
   1134     return Hexagon::STriw_cdnNotPt_nv_V4;
   1135 
   1136   case Hexagon::STriw_indexed_cPt_nv_V4 :
   1137     return Hexagon::STriw_indexed_cdnPt_nv_V4;
   1138   case Hexagon::STriw_indexed_cNotPt_nv_V4 :
   1139     return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
   1140 
   1141   case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
   1142     return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
   1143   case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
   1144     return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
   1145 
   1146   case Hexagon::POST_STwri_cPt_nv_V4 :
   1147     return Hexagon::POST_STwri_cdnPt_nv_V4;
   1148   case Hexagon::POST_STwri_cNotPt_nv_V4:
   1149     return Hexagon::POST_STwri_cdnNotPt_nv_V4;
   1150 
   1151   case Hexagon::STw_GP_cPt_nv_V4 :
   1152     return Hexagon::STw_GP_cdnPt_nv_V4;
   1153 
   1154   case Hexagon::STw_GP_cNotPt_nv_V4 :
   1155     return Hexagon::STw_GP_cdnNotPt_nv_V4;
   1156 
   1157   // Conditional add
   1158   case Hexagon::ADD_ri_cPt :
   1159     return Hexagon::ADD_ri_cdnPt;
   1160   case Hexagon::ADD_ri_cNotPt :
   1161     return Hexagon::ADD_ri_cdnNotPt;
   1162 
   1163   case Hexagon::ADD_rr_cPt :
   1164     return Hexagon::ADD_rr_cdnPt;
   1165   case Hexagon::ADD_rr_cNotPt :
   1166     return Hexagon::ADD_rr_cdnNotPt;
   1167 
   1168   // Conditional logical Operations
   1169   case Hexagon::XOR_rr_cPt :
   1170     return Hexagon::XOR_rr_cdnPt;
   1171   case Hexagon::XOR_rr_cNotPt :
   1172     return Hexagon::XOR_rr_cdnNotPt;
   1173 
   1174   case Hexagon::AND_rr_cPt :
   1175     return Hexagon::AND_rr_cdnPt;
   1176   case Hexagon::AND_rr_cNotPt :
   1177     return Hexagon::AND_rr_cdnNotPt;
   1178 
   1179   case Hexagon::OR_rr_cPt :
   1180     return Hexagon::OR_rr_cdnPt;
   1181   case Hexagon::OR_rr_cNotPt :
   1182     return Hexagon::OR_rr_cdnNotPt;
   1183 
   1184   // Conditional Subtract
   1185   case Hexagon::SUB_rr_cPt :
   1186     return Hexagon::SUB_rr_cdnPt;
   1187   case Hexagon::SUB_rr_cNotPt :
   1188     return Hexagon::SUB_rr_cdnNotPt;
   1189 
   1190   // Conditional combine
   1191   case Hexagon::COMBINE_rr_cPt :
   1192     return Hexagon::COMBINE_rr_cdnPt;
   1193   case Hexagon::COMBINE_rr_cNotPt :
   1194     return Hexagon::COMBINE_rr_cdnNotPt;
   1195 
   1196   case Hexagon::ASLH_cPt_V4 :
   1197     return Hexagon::ASLH_cdnPt_V4;
   1198   case Hexagon::ASLH_cNotPt_V4 :
   1199     return Hexagon::ASLH_cdnNotPt_V4;
   1200 
   1201   case Hexagon::ASRH_cPt_V4 :
   1202     return Hexagon::ASRH_cdnPt_V4;
   1203   case Hexagon::ASRH_cNotPt_V4 :
   1204     return Hexagon::ASRH_cdnNotPt_V4;
   1205 
   1206   case Hexagon::SXTB_cPt_V4 :
   1207     return Hexagon::SXTB_cdnPt_V4;
   1208   case Hexagon::SXTB_cNotPt_V4 :
   1209     return Hexagon::SXTB_cdnNotPt_V4;
   1210 
   1211   case Hexagon::SXTH_cPt_V4 :
   1212     return Hexagon::SXTH_cdnPt_V4;
   1213   case Hexagon::SXTH_cNotPt_V4 :
   1214     return Hexagon::SXTH_cdnNotPt_V4;
   1215 
   1216   case Hexagon::ZXTB_cPt_V4 :
   1217     return Hexagon::ZXTB_cdnPt_V4;
   1218   case Hexagon::ZXTB_cNotPt_V4 :
   1219     return Hexagon::ZXTB_cdnNotPt_V4;
   1220 
   1221   case Hexagon::ZXTH_cPt_V4 :
   1222     return Hexagon::ZXTH_cdnPt_V4;
   1223   case Hexagon::ZXTH_cNotPt_V4 :
   1224     return Hexagon::ZXTH_cdnNotPt_V4;
   1225   }
   1226 }
   1227 
   1228 // Returns true if an instruction can be promoted to .new predicate
   1229 // or new-value store.
   1230 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
   1231   if ( isCondInst(MI) || IsNewifyStore(MI))
   1232     return true;
   1233   else
   1234     return false;
   1235 }
   1236 
   1237 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
   1238   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   1239   const MCInstrDesc& TID = MI->getDesc();
   1240                                     // bug 5670: until that is fixed,
   1241                                     // this portion is disabled.
   1242   if (   TID.isConditionalBranch()  // && !IsRegisterJump(MI)) ||
   1243       || QII->isConditionalTransfer(MI)
   1244       || QII->isConditionalALU32(MI)
   1245       || QII->isConditionalLoad(MI)
   1246       || QII->isConditionalStore(MI)) {
   1247     return true;
   1248   }
   1249   return false;
   1250 }
   1251 
   1252 
   1253 // Promote an instructiont to its .new form.
   1254 // At this time, we have already made a call to CanPromoteToDotNew
   1255 // and made sure that it can *indeed* be promoted.
   1256 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
   1257                         SDep::Kind DepType, MachineBasicBlock::iterator &MII,
   1258                         const TargetRegisterClass* RC) {
   1259 
   1260   assert (DepType == SDep::Data);
   1261   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   1262 
   1263   int NewOpcode;
   1264   if (RC == &Hexagon::PredRegsRegClass)
   1265     NewOpcode = GetDotNewPredOp(MI->getOpcode());
   1266   else
   1267     NewOpcode = GetDotNewOp(MI->getOpcode());
   1268   MI->setDesc(QII->get(NewOpcode));
   1269 
   1270   return true;
   1271 }
   1272 
   1273 // Returns the most basic instruction for the .new predicated instructions and
   1274 // new-value stores.
   1275 // For example, all of the following instructions will be converted back to the
   1276 // same instruction:
   1277 // 1) if (p0.new) memw(R0+#0) = R1.new  --->
   1278 // 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
   1279 // 3) if (p0.new) memw(R0+#0) = R1      --->
   1280 //
   1281 // To understand the translation of instruction 1 to its original form, consider
   1282 // a packet with 3 instructions.
   1283 // { p0 = cmp.eq(R0,R1)
   1284 //   if (p0.new) R2 = add(R3, R4)
   1285 //   R5 = add (R3, R1)
   1286 //   }
   1287 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
   1288 //
   1289 // This instruction can be part of the previous packet only if both p0 and R2
   1290 // are promoted to .new values. This promotion happens in steps, first
   1291 // predicate register is promoted to .new and in the next iteration R2 is
   1292 // promoted. Therefore, in case of dependence check failure (due to R5) during
   1293 // next iteration, it should be converted back to its most basic form.
   1294 
   1295 static int GetDotOldOp(const int opc) {
   1296   switch (opc) {
   1297   default: llvm_unreachable("Unknown .old type");
   1298   case Hexagon::TFR_cdnPt:
   1299     return Hexagon::TFR_cPt;
   1300 
   1301   case Hexagon::TFR_cdnNotPt:
   1302     return Hexagon::TFR_cNotPt;
   1303 
   1304   case Hexagon::TFRI_cdnPt:
   1305     return Hexagon::TFRI_cPt;
   1306 
   1307   case Hexagon::TFRI_cdnNotPt:
   1308     return Hexagon::TFRI_cNotPt;
   1309 
   1310   case Hexagon::JMP_cdnPt:
   1311     return Hexagon::JMP_c;
   1312 
   1313   case Hexagon::JMP_cdnNotPt:
   1314     return Hexagon::JMP_cNot;
   1315 
   1316   case Hexagon::JMPR_cdnPt_V3:
   1317     return Hexagon::JMPR_cPt;
   1318 
   1319   case Hexagon::JMPR_cdnNotPt_V3:
   1320     return Hexagon::JMPR_cNotPt;
   1321 
   1322   // Load double word
   1323 
   1324   case Hexagon::LDrid_cdnPt :
   1325     return Hexagon::LDrid_cPt;
   1326 
   1327   case Hexagon::LDrid_cdnNotPt :
   1328     return Hexagon::LDrid_cNotPt;
   1329 
   1330   case Hexagon::LDrid_indexed_cdnPt :
   1331     return Hexagon::LDrid_indexed_cPt;
   1332 
   1333   case Hexagon::LDrid_indexed_cdnNotPt :
   1334     return Hexagon::LDrid_indexed_cNotPt;
   1335 
   1336   case Hexagon::POST_LDrid_cdnPt_V4 :
   1337     return Hexagon::POST_LDrid_cPt;
   1338 
   1339   case Hexagon::POST_LDrid_cdnNotPt_V4 :
   1340     return Hexagon::POST_LDrid_cNotPt;
   1341 
   1342   // Load word
   1343 
   1344   case Hexagon::LDriw_cdnPt :
   1345     return Hexagon::LDriw_cPt;
   1346 
   1347   case Hexagon::LDriw_cdnNotPt :
   1348     return Hexagon::LDriw_cNotPt;
   1349 
   1350   case Hexagon::LDriw_indexed_cdnPt :
   1351     return Hexagon::LDriw_indexed_cPt;
   1352 
   1353   case Hexagon::LDriw_indexed_cdnNotPt :
   1354     return Hexagon::LDriw_indexed_cNotPt;
   1355 
   1356   case Hexagon::POST_LDriw_cdnPt_V4 :
   1357     return Hexagon::POST_LDriw_cPt;
   1358 
   1359   case Hexagon::POST_LDriw_cdnNotPt_V4 :
   1360     return Hexagon::POST_LDriw_cNotPt;
   1361 
   1362   // Load half
   1363 
   1364   case Hexagon::LDrih_cdnPt :
   1365     return Hexagon::LDrih_cPt;
   1366 
   1367   case Hexagon::LDrih_cdnNotPt :
   1368     return Hexagon::LDrih_cNotPt;
   1369 
   1370   case Hexagon::LDrih_indexed_cdnPt :
   1371     return Hexagon::LDrih_indexed_cPt;
   1372 
   1373   case Hexagon::LDrih_indexed_cdnNotPt :
   1374     return Hexagon::LDrih_indexed_cNotPt;
   1375 
   1376   case Hexagon::POST_LDrih_cdnPt_V4 :
   1377     return Hexagon::POST_LDrih_cPt;
   1378 
   1379   case Hexagon::POST_LDrih_cdnNotPt_V4 :
   1380     return Hexagon::POST_LDrih_cNotPt;
   1381 
   1382   // Load byte
   1383 
   1384   case Hexagon::LDrib_cdnPt :
   1385     return Hexagon::LDrib_cPt;
   1386 
   1387   case Hexagon::LDrib_cdnNotPt :
   1388     return Hexagon::LDrib_cNotPt;
   1389 
   1390   case Hexagon::LDrib_indexed_cdnPt :
   1391     return Hexagon::LDrib_indexed_cPt;
   1392 
   1393   case Hexagon::LDrib_indexed_cdnNotPt :
   1394     return Hexagon::LDrib_indexed_cNotPt;
   1395 
   1396   case Hexagon::POST_LDrib_cdnPt_V4 :
   1397     return Hexagon::POST_LDrib_cPt;
   1398 
   1399   case Hexagon::POST_LDrib_cdnNotPt_V4 :
   1400     return Hexagon::POST_LDrib_cNotPt;
   1401 
   1402   // Load unsigned half
   1403 
   1404   case Hexagon::LDriuh_cdnPt :
   1405     return Hexagon::LDriuh_cPt;
   1406 
   1407   case Hexagon::LDriuh_cdnNotPt :
   1408     return Hexagon::LDriuh_cNotPt;
   1409 
   1410   case Hexagon::LDriuh_indexed_cdnPt :
   1411     return Hexagon::LDriuh_indexed_cPt;
   1412 
   1413   case Hexagon::LDriuh_indexed_cdnNotPt :
   1414     return Hexagon::LDriuh_indexed_cNotPt;
   1415 
   1416   case Hexagon::POST_LDriuh_cdnPt_V4 :
   1417     return Hexagon::POST_LDriuh_cPt;
   1418 
   1419   case Hexagon::POST_LDriuh_cdnNotPt_V4 :
   1420     return Hexagon::POST_LDriuh_cNotPt;
   1421 
   1422   // Load unsigned byte
   1423   case Hexagon::LDriub_cdnPt :
   1424     return Hexagon::LDriub_cPt;
   1425 
   1426   case Hexagon::LDriub_cdnNotPt :
   1427     return Hexagon::LDriub_cNotPt;
   1428 
   1429   case Hexagon::LDriub_indexed_cdnPt :
   1430     return Hexagon::LDriub_indexed_cPt;
   1431 
   1432   case Hexagon::LDriub_indexed_cdnNotPt :
   1433     return Hexagon::LDriub_indexed_cNotPt;
   1434 
   1435   case Hexagon::POST_LDriub_cdnPt_V4 :
   1436     return Hexagon::POST_LDriub_cPt;
   1437 
   1438   case Hexagon::POST_LDriub_cdnNotPt_V4 :
   1439     return Hexagon::POST_LDriub_cNotPt;
   1440 
   1441   // V4 indexed+scaled Load
   1442 
   1443   case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
   1444     return Hexagon::LDrid_indexed_shl_cPt_V4;
   1445 
   1446   case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
   1447     return Hexagon::LDrid_indexed_shl_cNotPt_V4;
   1448 
   1449   case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
   1450     return Hexagon::LDrib_indexed_shl_cPt_V4;
   1451 
   1452   case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
   1453     return Hexagon::LDrib_indexed_shl_cNotPt_V4;
   1454 
   1455   case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
   1456     return Hexagon::LDriub_indexed_shl_cPt_V4;
   1457 
   1458   case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
   1459     return Hexagon::LDriub_indexed_shl_cNotPt_V4;
   1460 
   1461   case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
   1462     return Hexagon::LDrih_indexed_shl_cPt_V4;
   1463 
   1464   case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
   1465     return Hexagon::LDrih_indexed_shl_cNotPt_V4;
   1466 
   1467   case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
   1468     return Hexagon::LDriuh_indexed_shl_cPt_V4;
   1469 
   1470   case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
   1471     return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
   1472 
   1473   case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
   1474     return Hexagon::LDriw_indexed_shl_cPt_V4;
   1475 
   1476   case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
   1477     return Hexagon::LDriw_indexed_shl_cNotPt_V4;
   1478 
   1479   // V4 global address load
   1480 
   1481   case Hexagon::LDd_GP_cdnPt_V4:
   1482     return Hexagon::LDd_GP_cPt_V4;
   1483 
   1484   case Hexagon::LDd_GP_cdnNotPt_V4:
   1485     return Hexagon::LDd_GP_cNotPt_V4;
   1486 
   1487   case Hexagon::LDb_GP_cdnPt_V4:
   1488     return Hexagon::LDb_GP_cPt_V4;
   1489 
   1490   case Hexagon::LDb_GP_cdnNotPt_V4:
   1491     return Hexagon::LDb_GP_cNotPt_V4;
   1492 
   1493   case Hexagon::LDub_GP_cdnPt_V4:
   1494     return Hexagon::LDub_GP_cPt_V4;
   1495 
   1496   case Hexagon::LDub_GP_cdnNotPt_V4:
   1497     return Hexagon::LDub_GP_cNotPt_V4;
   1498 
   1499   case Hexagon::LDh_GP_cdnPt_V4:
   1500     return Hexagon::LDh_GP_cPt_V4;
   1501 
   1502   case Hexagon::LDh_GP_cdnNotPt_V4:
   1503     return Hexagon::LDh_GP_cNotPt_V4;
   1504 
   1505   case Hexagon::LDuh_GP_cdnPt_V4:
   1506     return Hexagon::LDuh_GP_cPt_V4;
   1507 
   1508   case Hexagon::LDuh_GP_cdnNotPt_V4:
   1509     return Hexagon::LDuh_GP_cNotPt_V4;
   1510 
   1511   case Hexagon::LDw_GP_cdnPt_V4:
   1512     return Hexagon::LDw_GP_cPt_V4;
   1513 
   1514   case Hexagon::LDw_GP_cdnNotPt_V4:
   1515     return Hexagon::LDw_GP_cNotPt_V4;
   1516 
   1517   // Conditional add
   1518 
   1519   case Hexagon::ADD_ri_cdnPt :
   1520     return Hexagon::ADD_ri_cPt;
   1521   case Hexagon::ADD_ri_cdnNotPt :
   1522     return Hexagon::ADD_ri_cNotPt;
   1523 
   1524   case Hexagon::ADD_rr_cdnPt :
   1525     return Hexagon::ADD_rr_cPt;
   1526   case Hexagon::ADD_rr_cdnNotPt:
   1527     return Hexagon::ADD_rr_cNotPt;
   1528 
   1529   // Conditional logical Operations
   1530 
   1531   case Hexagon::XOR_rr_cdnPt :
   1532     return Hexagon::XOR_rr_cPt;
   1533   case Hexagon::XOR_rr_cdnNotPt :
   1534     return Hexagon::XOR_rr_cNotPt;
   1535 
   1536   case Hexagon::AND_rr_cdnPt :
   1537     return Hexagon::AND_rr_cPt;
   1538   case Hexagon::AND_rr_cdnNotPt :
   1539     return Hexagon::AND_rr_cNotPt;
   1540 
   1541   case Hexagon::OR_rr_cdnPt :
   1542     return Hexagon::OR_rr_cPt;
   1543   case Hexagon::OR_rr_cdnNotPt :
   1544     return Hexagon::OR_rr_cNotPt;
   1545 
   1546   // Conditional Subtract
   1547 
   1548   case Hexagon::SUB_rr_cdnPt :
   1549     return Hexagon::SUB_rr_cPt;
   1550   case Hexagon::SUB_rr_cdnNotPt :
   1551     return Hexagon::SUB_rr_cNotPt;
   1552 
   1553   // Conditional combine
   1554 
   1555   case Hexagon::COMBINE_rr_cdnPt :
   1556     return Hexagon::COMBINE_rr_cPt;
   1557   case Hexagon::COMBINE_rr_cdnNotPt :
   1558     return Hexagon::COMBINE_rr_cNotPt;
   1559 
   1560 // Conditional shift operations
   1561 
   1562   case Hexagon::ASLH_cdnPt_V4 :
   1563     return Hexagon::ASLH_cPt_V4;
   1564   case Hexagon::ASLH_cdnNotPt_V4 :
   1565     return Hexagon::ASLH_cNotPt_V4;
   1566 
   1567   case Hexagon::ASRH_cdnPt_V4 :
   1568     return Hexagon::ASRH_cPt_V4;
   1569   case Hexagon::ASRH_cdnNotPt_V4 :
   1570     return Hexagon::ASRH_cNotPt_V4;
   1571 
   1572   case Hexagon::SXTB_cdnPt_V4 :
   1573     return Hexagon::SXTB_cPt_V4;
   1574   case Hexagon::SXTB_cdnNotPt_V4 :
   1575     return Hexagon::SXTB_cNotPt_V4;
   1576 
   1577   case Hexagon::SXTH_cdnPt_V4 :
   1578     return Hexagon::SXTH_cPt_V4;
   1579   case Hexagon::SXTH_cdnNotPt_V4 :
   1580     return Hexagon::SXTH_cNotPt_V4;
   1581 
   1582   case Hexagon::ZXTB_cdnPt_V4 :
   1583     return Hexagon::ZXTB_cPt_V4;
   1584   case Hexagon::ZXTB_cdnNotPt_V4 :
   1585     return Hexagon::ZXTB_cNotPt_V4;
   1586 
   1587   case Hexagon::ZXTH_cdnPt_V4 :
   1588     return Hexagon::ZXTH_cPt_V4;
   1589   case Hexagon::ZXTH_cdnNotPt_V4 :
   1590     return Hexagon::ZXTH_cNotPt_V4;
   1591 
   1592   // Store byte
   1593 
   1594   case Hexagon::STrib_imm_cdnPt_V4 :
   1595     return Hexagon::STrib_imm_cPt_V4;
   1596 
   1597   case Hexagon::STrib_imm_cdnNotPt_V4 :
   1598     return Hexagon::STrib_imm_cNotPt_V4;
   1599 
   1600   case Hexagon::STrib_cdnPt_nv_V4 :
   1601   case Hexagon::STrib_cPt_nv_V4 :
   1602   case Hexagon::STrib_cdnPt_V4 :
   1603     return Hexagon::STrib_cPt;
   1604 
   1605   case Hexagon::STrib_cdnNotPt_nv_V4 :
   1606   case Hexagon::STrib_cNotPt_nv_V4 :
   1607   case Hexagon::STrib_cdnNotPt_V4 :
   1608     return Hexagon::STrib_cNotPt;
   1609 
   1610   case Hexagon::STrib_indexed_cdnPt_V4 :
   1611   case Hexagon::STrib_indexed_cPt_nv_V4 :
   1612   case Hexagon::STrib_indexed_cdnPt_nv_V4 :
   1613     return Hexagon::STrib_indexed_cPt;
   1614 
   1615   case Hexagon::STrib_indexed_cdnNotPt_V4 :
   1616   case Hexagon::STrib_indexed_cNotPt_nv_V4 :
   1617   case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
   1618     return Hexagon::STrib_indexed_cNotPt;
   1619 
   1620   case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
   1621   case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
   1622   case Hexagon::STrib_indexed_shl_cdnPt_V4 :
   1623     return Hexagon::STrib_indexed_shl_cPt_V4;
   1624 
   1625   case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
   1626   case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
   1627   case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
   1628     return Hexagon::STrib_indexed_shl_cNotPt_V4;
   1629 
   1630   case Hexagon::POST_STbri_cdnPt_nv_V4 :
   1631   case Hexagon::POST_STbri_cPt_nv_V4 :
   1632   case Hexagon::POST_STbri_cdnPt_V4 :
   1633     return Hexagon::POST_STbri_cPt;
   1634 
   1635   case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
   1636   case Hexagon::POST_STbri_cNotPt_nv_V4:
   1637   case Hexagon::POST_STbri_cdnNotPt_V4 :
   1638     return Hexagon::POST_STbri_cNotPt;
   1639 
   1640   case Hexagon::STb_GP_cdnPt_nv_V4:
   1641   case Hexagon::STb_GP_cdnPt_V4:
   1642   case Hexagon::STb_GP_cPt_nv_V4:
   1643     return Hexagon::STb_GP_cPt_V4;
   1644 
   1645   case Hexagon::STb_GP_cdnNotPt_nv_V4:
   1646   case Hexagon::STb_GP_cdnNotPt_V4:
   1647   case Hexagon::STb_GP_cNotPt_nv_V4:
   1648     return Hexagon::STb_GP_cNotPt_V4;
   1649 
   1650   // Store new-value byte - unconditional
   1651   case Hexagon::STrib_nv_V4:
   1652     return Hexagon::STrib;
   1653 
   1654   case Hexagon::STrib_indexed_nv_V4:
   1655     return Hexagon::STrib_indexed;
   1656 
   1657   case Hexagon::STrib_indexed_shl_nv_V4:
   1658     return Hexagon::STrib_indexed_shl_V4;
   1659 
   1660   case Hexagon::STrib_shl_nv_V4:
   1661     return Hexagon::STrib_shl_V4;
   1662 
   1663   case Hexagon::STb_GP_nv_V4:
   1664     return Hexagon::STb_GP_V4;
   1665 
   1666   case Hexagon::POST_STbri_nv_V4:
   1667     return Hexagon::POST_STbri;
   1668 
   1669   // Store halfword
   1670   case Hexagon::STrih_imm_cdnPt_V4 :
   1671     return Hexagon::STrih_imm_cPt_V4;
   1672 
   1673   case Hexagon::STrih_imm_cdnNotPt_V4 :
   1674     return Hexagon::STrih_imm_cNotPt_V4;
   1675 
   1676   case Hexagon::STrih_cdnPt_nv_V4 :
   1677   case Hexagon::STrih_cPt_nv_V4 :
   1678   case Hexagon::STrih_cdnPt_V4 :
   1679     return Hexagon::STrih_cPt;
   1680 
   1681   case Hexagon::STrih_cdnNotPt_nv_V4 :
   1682   case Hexagon::STrih_cNotPt_nv_V4 :
   1683   case Hexagon::STrih_cdnNotPt_V4 :
   1684     return Hexagon::STrih_cNotPt;
   1685 
   1686   case Hexagon::STrih_indexed_cdnPt_nv_V4:
   1687   case Hexagon::STrih_indexed_cPt_nv_V4 :
   1688   case Hexagon::STrih_indexed_cdnPt_V4 :
   1689     return Hexagon::STrih_indexed_cPt;
   1690 
   1691   case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
   1692   case Hexagon::STrih_indexed_cNotPt_nv_V4 :
   1693   case Hexagon::STrih_indexed_cdnNotPt_V4 :
   1694     return Hexagon::STrih_indexed_cNotPt;
   1695 
   1696   case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
   1697   case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
   1698   case Hexagon::STrih_indexed_shl_cdnPt_V4 :
   1699     return Hexagon::STrih_indexed_shl_cPt_V4;
   1700 
   1701   case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
   1702   case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
   1703   case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
   1704     return Hexagon::STrih_indexed_shl_cNotPt_V4;
   1705 
   1706   case Hexagon::POST_SThri_cdnPt_nv_V4 :
   1707   case Hexagon::POST_SThri_cPt_nv_V4 :
   1708   case Hexagon::POST_SThri_cdnPt_V4 :
   1709     return Hexagon::POST_SThri_cPt;
   1710 
   1711   case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
   1712   case Hexagon::POST_SThri_cNotPt_nv_V4 :
   1713   case Hexagon::POST_SThri_cdnNotPt_V4 :
   1714     return Hexagon::POST_SThri_cNotPt;
   1715 
   1716   case Hexagon::STh_GP_cdnPt_nv_V4:
   1717   case Hexagon::STh_GP_cdnPt_V4:
   1718   case Hexagon::STh_GP_cPt_nv_V4:
   1719     return Hexagon::STh_GP_cPt_V4;
   1720 
   1721   case Hexagon::STh_GP_cdnNotPt_nv_V4:
   1722   case Hexagon::STh_GP_cdnNotPt_V4:
   1723   case Hexagon::STh_GP_cNotPt_nv_V4:
   1724     return Hexagon::STh_GP_cNotPt_V4;
   1725 
   1726   // Store new-value halfword - unconditional
   1727 
   1728   case Hexagon::STrih_nv_V4:
   1729     return Hexagon::STrih;
   1730 
   1731   case Hexagon::STrih_indexed_nv_V4:
   1732     return Hexagon::STrih_indexed;
   1733 
   1734   case Hexagon::STrih_indexed_shl_nv_V4:
   1735     return Hexagon::STrih_indexed_shl_V4;
   1736 
   1737   case Hexagon::STrih_shl_nv_V4:
   1738     return Hexagon::STrih_shl_V4;
   1739 
   1740   case Hexagon::STh_GP_nv_V4:
   1741     return Hexagon::STh_GP_V4;
   1742 
   1743   case Hexagon::POST_SThri_nv_V4:
   1744     return Hexagon::POST_SThri;
   1745 
   1746    // Store word
   1747 
   1748    case Hexagon::STriw_imm_cdnPt_V4 :
   1749     return Hexagon::STriw_imm_cPt_V4;
   1750 
   1751   case Hexagon::STriw_imm_cdnNotPt_V4 :
   1752     return Hexagon::STriw_imm_cNotPt_V4;
   1753 
   1754   case Hexagon::STriw_cdnPt_nv_V4 :
   1755   case Hexagon::STriw_cPt_nv_V4 :
   1756   case Hexagon::STriw_cdnPt_V4 :
   1757     return Hexagon::STriw_cPt;
   1758 
   1759   case Hexagon::STriw_cdnNotPt_nv_V4 :
   1760   case Hexagon::STriw_cNotPt_nv_V4 :
   1761   case Hexagon::STriw_cdnNotPt_V4 :
   1762     return Hexagon::STriw_cNotPt;
   1763 
   1764   case Hexagon::STriw_indexed_cdnPt_nv_V4 :
   1765   case Hexagon::STriw_indexed_cPt_nv_V4 :
   1766   case Hexagon::STriw_indexed_cdnPt_V4 :
   1767     return Hexagon::STriw_indexed_cPt;
   1768 
   1769   case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
   1770   case Hexagon::STriw_indexed_cNotPt_nv_V4 :
   1771   case Hexagon::STriw_indexed_cdnNotPt_V4 :
   1772     return Hexagon::STriw_indexed_cNotPt;
   1773 
   1774   case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
   1775   case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
   1776   case Hexagon::STriw_indexed_shl_cdnPt_V4 :
   1777     return Hexagon::STriw_indexed_shl_cPt_V4;
   1778 
   1779   case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
   1780   case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
   1781   case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
   1782     return Hexagon::STriw_indexed_shl_cNotPt_V4;
   1783 
   1784   case Hexagon::POST_STwri_cdnPt_nv_V4 :
   1785   case Hexagon::POST_STwri_cPt_nv_V4 :
   1786   case Hexagon::POST_STwri_cdnPt_V4 :
   1787     return Hexagon::POST_STwri_cPt;
   1788 
   1789   case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
   1790   case Hexagon::POST_STwri_cNotPt_nv_V4 :
   1791   case Hexagon::POST_STwri_cdnNotPt_V4 :
   1792     return Hexagon::POST_STwri_cNotPt;
   1793 
   1794   case Hexagon::STw_GP_cdnPt_nv_V4:
   1795   case Hexagon::STw_GP_cdnPt_V4:
   1796   case Hexagon::STw_GP_cPt_nv_V4:
   1797     return Hexagon::STw_GP_cPt_V4;
   1798 
   1799   case Hexagon::STw_GP_cdnNotPt_nv_V4:
   1800   case Hexagon::STw_GP_cdnNotPt_V4:
   1801   case Hexagon::STw_GP_cNotPt_nv_V4:
   1802     return Hexagon::STw_GP_cNotPt_V4;
   1803 
   1804   // Store new-value word - unconditional
   1805 
   1806   case Hexagon::STriw_nv_V4:
   1807     return Hexagon::STriw;
   1808 
   1809   case Hexagon::STriw_indexed_nv_V4:
   1810     return Hexagon::STriw_indexed;
   1811 
   1812   case Hexagon::STriw_indexed_shl_nv_V4:
   1813     return Hexagon::STriw_indexed_shl_V4;
   1814 
   1815   case Hexagon::STriw_shl_nv_V4:
   1816     return Hexagon::STriw_shl_V4;
   1817 
   1818   case Hexagon::STw_GP_nv_V4:
   1819     return Hexagon::STw_GP_V4;
   1820 
   1821   case Hexagon::POST_STwri_nv_V4:
   1822     return Hexagon::POST_STwri;
   1823 
   1824  // Store doubleword
   1825 
   1826   case Hexagon::STrid_cdnPt_V4 :
   1827     return Hexagon::STrid_cPt;
   1828 
   1829   case Hexagon::STrid_cdnNotPt_V4 :
   1830     return Hexagon::STrid_cNotPt;
   1831 
   1832   case Hexagon::STrid_indexed_cdnPt_V4 :
   1833     return Hexagon::STrid_indexed_cPt;
   1834 
   1835   case Hexagon::STrid_indexed_cdnNotPt_V4 :
   1836     return Hexagon::STrid_indexed_cNotPt;
   1837 
   1838   case Hexagon::STrid_indexed_shl_cdnPt_V4 :
   1839     return Hexagon::STrid_indexed_shl_cPt_V4;
   1840 
   1841   case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
   1842     return Hexagon::STrid_indexed_shl_cNotPt_V4;
   1843 
   1844   case Hexagon::POST_STdri_cdnPt_V4 :
   1845     return Hexagon::POST_STdri_cPt;
   1846 
   1847   case Hexagon::POST_STdri_cdnNotPt_V4 :
   1848     return Hexagon::POST_STdri_cNotPt;
   1849 
   1850   case Hexagon::STd_GP_cdnPt_V4 :
   1851     return Hexagon::STd_GP_cPt_V4;
   1852 
   1853   case Hexagon::STd_GP_cdnNotPt_V4 :
   1854     return Hexagon::STd_GP_cNotPt_V4;
   1855 
   1856   }
   1857 }
   1858 
   1859 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
   1860   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   1861   int NewOpcode = GetDotOldOp(MI->getOpcode());
   1862   MI->setDesc(QII->get(NewOpcode));
   1863   return true;
   1864 }
   1865 
   1866 // Returns true if an instruction is predicated on p0 and false if it's
   1867 // predicated on !p0.
   1868 
   1869 static bool GetPredicateSense(MachineInstr* MI,
   1870                               const HexagonInstrInfo *QII) {
   1871 
   1872   switch (MI->getOpcode()) {
   1873   default: llvm_unreachable("Unknown predicate sense of the instruction");
   1874   case Hexagon::TFR_cPt:
   1875   case Hexagon::TFR_cdnPt:
   1876   case Hexagon::TFRI_cPt:
   1877   case Hexagon::TFRI_cdnPt:
   1878   case Hexagon::STrib_cPt :
   1879   case Hexagon::STrib_cdnPt_V4 :
   1880   case Hexagon::STrib_indexed_cPt :
   1881   case Hexagon::STrib_indexed_cdnPt_V4 :
   1882   case Hexagon::STrib_indexed_shl_cPt_V4 :
   1883   case Hexagon::STrib_indexed_shl_cdnPt_V4 :
   1884   case Hexagon::POST_STbri_cPt :
   1885   case Hexagon::POST_STbri_cdnPt_V4 :
   1886   case Hexagon::STrih_cPt :
   1887   case Hexagon::STrih_cdnPt_V4 :
   1888   case Hexagon::STrih_indexed_cPt :
   1889   case Hexagon::STrih_indexed_cdnPt_V4 :
   1890   case Hexagon::STrih_indexed_shl_cPt_V4 :
   1891   case Hexagon::STrih_indexed_shl_cdnPt_V4 :
   1892   case Hexagon::POST_SThri_cPt :
   1893   case Hexagon::POST_SThri_cdnPt_V4 :
   1894   case Hexagon::STriw_cPt :
   1895   case Hexagon::STriw_cdnPt_V4 :
   1896   case Hexagon::STriw_indexed_cPt :
   1897   case Hexagon::STriw_indexed_cdnPt_V4 :
   1898   case Hexagon::STriw_indexed_shl_cPt_V4 :
   1899   case Hexagon::STriw_indexed_shl_cdnPt_V4 :
   1900   case Hexagon::POST_STwri_cPt :
   1901   case Hexagon::POST_STwri_cdnPt_V4 :
   1902   case Hexagon::STrib_imm_cPt_V4 :
   1903   case Hexagon::STrib_imm_cdnPt_V4 :
   1904   case Hexagon::STrid_cPt :
   1905   case Hexagon::STrid_cdnPt_V4 :
   1906   case Hexagon::STrid_indexed_cPt :
   1907   case Hexagon::STrid_indexed_cdnPt_V4 :
   1908   case Hexagon::STrid_indexed_shl_cPt_V4 :
   1909   case Hexagon::STrid_indexed_shl_cdnPt_V4 :
   1910   case Hexagon::POST_STdri_cPt :
   1911   case Hexagon::POST_STdri_cdnPt_V4 :
   1912   case Hexagon::STrih_imm_cPt_V4 :
   1913   case Hexagon::STrih_imm_cdnPt_V4 :
   1914   case Hexagon::STriw_imm_cPt_V4 :
   1915   case Hexagon::STriw_imm_cdnPt_V4 :
   1916   case Hexagon::JMP_cdnPt :
   1917   case Hexagon::LDrid_cPt :
   1918   case Hexagon::LDrid_cdnPt :
   1919   case Hexagon::LDrid_indexed_cPt :
   1920   case Hexagon::LDrid_indexed_cdnPt :
   1921   case Hexagon::POST_LDrid_cPt :
   1922   case Hexagon::POST_LDrid_cdnPt_V4 :
   1923   case Hexagon::LDriw_cPt :
   1924   case Hexagon::LDriw_cdnPt :
   1925   case Hexagon::LDriw_indexed_cPt :
   1926   case Hexagon::LDriw_indexed_cdnPt :
   1927   case Hexagon::POST_LDriw_cPt :
   1928   case Hexagon::POST_LDriw_cdnPt_V4 :
   1929   case Hexagon::LDrih_cPt :
   1930   case Hexagon::LDrih_cdnPt :
   1931   case Hexagon::LDrih_indexed_cPt :
   1932   case Hexagon::LDrih_indexed_cdnPt :
   1933   case Hexagon::POST_LDrih_cPt :
   1934   case Hexagon::POST_LDrih_cdnPt_V4 :
   1935   case Hexagon::LDrib_cPt :
   1936   case Hexagon::LDrib_cdnPt :
   1937   case Hexagon::LDrib_indexed_cPt :
   1938   case Hexagon::LDrib_indexed_cdnPt :
   1939   case Hexagon::POST_LDrib_cPt :
   1940   case Hexagon::POST_LDrib_cdnPt_V4 :
   1941   case Hexagon::LDriuh_cPt :
   1942   case Hexagon::LDriuh_cdnPt :
   1943   case Hexagon::LDriuh_indexed_cPt :
   1944   case Hexagon::LDriuh_indexed_cdnPt :
   1945   case Hexagon::POST_LDriuh_cPt :
   1946   case Hexagon::POST_LDriuh_cdnPt_V4 :
   1947   case Hexagon::LDriub_cPt :
   1948   case Hexagon::LDriub_cdnPt :
   1949   case Hexagon::LDriub_indexed_cPt :
   1950   case Hexagon::LDriub_indexed_cdnPt :
   1951   case Hexagon::POST_LDriub_cPt :
   1952   case Hexagon::POST_LDriub_cdnPt_V4 :
   1953   case Hexagon::LDrid_indexed_shl_cPt_V4 :
   1954   case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
   1955   case Hexagon::LDrib_indexed_shl_cPt_V4 :
   1956   case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
   1957   case Hexagon::LDriub_indexed_shl_cPt_V4 :
   1958   case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
   1959   case Hexagon::LDrih_indexed_shl_cPt_V4 :
   1960   case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
   1961   case Hexagon::LDriuh_indexed_shl_cPt_V4 :
   1962   case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
   1963   case Hexagon::LDriw_indexed_shl_cPt_V4 :
   1964   case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
   1965   case Hexagon::ADD_ri_cPt :
   1966   case Hexagon::ADD_ri_cdnPt :
   1967   case Hexagon::ADD_rr_cPt :
   1968   case Hexagon::ADD_rr_cdnPt :
   1969   case Hexagon::XOR_rr_cPt :
   1970   case Hexagon::XOR_rr_cdnPt :
   1971   case Hexagon::AND_rr_cPt :
   1972   case Hexagon::AND_rr_cdnPt :
   1973   case Hexagon::OR_rr_cPt :
   1974   case Hexagon::OR_rr_cdnPt :
   1975   case Hexagon::SUB_rr_cPt :
   1976   case Hexagon::SUB_rr_cdnPt :
   1977   case Hexagon::COMBINE_rr_cPt :
   1978   case Hexagon::COMBINE_rr_cdnPt :
   1979   case Hexagon::ASLH_cPt_V4 :
   1980   case Hexagon::ASLH_cdnPt_V4 :
   1981   case Hexagon::ASRH_cPt_V4 :
   1982   case Hexagon::ASRH_cdnPt_V4 :
   1983   case Hexagon::SXTB_cPt_V4 :
   1984   case Hexagon::SXTB_cdnPt_V4 :
   1985   case Hexagon::SXTH_cPt_V4 :
   1986   case Hexagon::SXTH_cdnPt_V4 :
   1987   case Hexagon::ZXTB_cPt_V4 :
   1988   case Hexagon::ZXTB_cdnPt_V4 :
   1989   case Hexagon::ZXTH_cPt_V4 :
   1990   case Hexagon::ZXTH_cdnPt_V4 :
   1991   case Hexagon::LDd_GP_cPt_V4 :
   1992   case Hexagon::LDb_GP_cPt_V4 :
   1993   case Hexagon::LDub_GP_cPt_V4 :
   1994   case Hexagon::LDh_GP_cPt_V4 :
   1995   case Hexagon::LDuh_GP_cPt_V4 :
   1996   case Hexagon::LDw_GP_cPt_V4 :
   1997   case Hexagon::STd_GP_cPt_V4 :
   1998   case Hexagon::STb_GP_cPt_V4 :
   1999   case Hexagon::STh_GP_cPt_V4 :
   2000   case Hexagon::STw_GP_cPt_V4 :
   2001   case Hexagon::LDd_GP_cdnPt_V4 :
   2002   case Hexagon::LDb_GP_cdnPt_V4 :
   2003   case Hexagon::LDub_GP_cdnPt_V4 :
   2004   case Hexagon::LDh_GP_cdnPt_V4 :
   2005   case Hexagon::LDuh_GP_cdnPt_V4 :
   2006   case Hexagon::LDw_GP_cdnPt_V4 :
   2007   case Hexagon::STd_GP_cdnPt_V4 :
   2008   case Hexagon::STb_GP_cdnPt_V4 :
   2009   case Hexagon::STh_GP_cdnPt_V4 :
   2010   case Hexagon::STw_GP_cdnPt_V4 :
   2011     return true;
   2012 
   2013   case Hexagon::TFR_cNotPt:
   2014   case Hexagon::TFR_cdnNotPt:
   2015   case Hexagon::TFRI_cNotPt:
   2016   case Hexagon::TFRI_cdnNotPt:
   2017   case Hexagon::STrib_cNotPt :
   2018   case Hexagon::STrib_cdnNotPt_V4 :
   2019   case Hexagon::STrib_indexed_cNotPt :
   2020   case Hexagon::STrib_indexed_cdnNotPt_V4 :
   2021   case Hexagon::STrib_indexed_shl_cNotPt_V4 :
   2022   case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
   2023   case Hexagon::POST_STbri_cNotPt :
   2024   case Hexagon::POST_STbri_cdnNotPt_V4 :
   2025   case Hexagon::STrih_cNotPt :
   2026   case Hexagon::STrih_cdnNotPt_V4 :
   2027   case Hexagon::STrih_indexed_cNotPt :
   2028   case Hexagon::STrih_indexed_cdnNotPt_V4 :
   2029   case Hexagon::STrih_indexed_shl_cNotPt_V4 :
   2030   case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
   2031   case Hexagon::POST_SThri_cNotPt :
   2032   case Hexagon::POST_SThri_cdnNotPt_V4 :
   2033   case Hexagon::STriw_cNotPt :
   2034   case Hexagon::STriw_cdnNotPt_V4 :
   2035   case Hexagon::STriw_indexed_cNotPt :
   2036   case Hexagon::STriw_indexed_cdnNotPt_V4 :
   2037   case Hexagon::STriw_indexed_shl_cNotPt_V4 :
   2038   case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
   2039   case Hexagon::POST_STwri_cNotPt :
   2040   case Hexagon::POST_STwri_cdnNotPt_V4 :
   2041   case Hexagon::STrib_imm_cNotPt_V4 :
   2042   case Hexagon::STrib_imm_cdnNotPt_V4 :
   2043   case Hexagon::STrid_cNotPt :
   2044   case Hexagon::STrid_cdnNotPt_V4 :
   2045   case Hexagon::STrid_indexed_cdnNotPt_V4 :
   2046   case Hexagon::STrid_indexed_cNotPt :
   2047   case Hexagon::STrid_indexed_shl_cNotPt_V4 :
   2048   case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
   2049   case Hexagon::POST_STdri_cNotPt :
   2050   case Hexagon::POST_STdri_cdnNotPt_V4 :
   2051   case Hexagon::STrih_imm_cNotPt_V4 :
   2052   case Hexagon::STrih_imm_cdnNotPt_V4 :
   2053   case Hexagon::STriw_imm_cNotPt_V4 :
   2054   case Hexagon::STriw_imm_cdnNotPt_V4 :
   2055   case Hexagon::JMP_cdnNotPt :
   2056   case Hexagon::LDrid_cNotPt :
   2057   case Hexagon::LDrid_cdnNotPt :
   2058   case Hexagon::LDrid_indexed_cNotPt :
   2059   case Hexagon::LDrid_indexed_cdnNotPt :
   2060   case Hexagon::POST_LDrid_cNotPt :
   2061   case Hexagon::POST_LDrid_cdnNotPt_V4 :
   2062   case Hexagon::LDriw_cNotPt :
   2063   case Hexagon::LDriw_cdnNotPt :
   2064   case Hexagon::LDriw_indexed_cNotPt :
   2065   case Hexagon::LDriw_indexed_cdnNotPt :
   2066   case Hexagon::POST_LDriw_cNotPt :
   2067   case Hexagon::POST_LDriw_cdnNotPt_V4 :
   2068   case Hexagon::LDrih_cNotPt :
   2069   case Hexagon::LDrih_cdnNotPt :
   2070   case Hexagon::LDrih_indexed_cNotPt :
   2071   case Hexagon::LDrih_indexed_cdnNotPt :
   2072   case Hexagon::POST_LDrih_cNotPt :
   2073   case Hexagon::POST_LDrih_cdnNotPt_V4 :
   2074   case Hexagon::LDrib_cNotPt :
   2075   case Hexagon::LDrib_cdnNotPt :
   2076   case Hexagon::LDrib_indexed_cNotPt :
   2077   case Hexagon::LDrib_indexed_cdnNotPt :
   2078   case Hexagon::POST_LDrib_cNotPt :
   2079   case Hexagon::POST_LDrib_cdnNotPt_V4 :
   2080   case Hexagon::LDriuh_cNotPt :
   2081   case Hexagon::LDriuh_cdnNotPt :
   2082   case Hexagon::LDriuh_indexed_cNotPt :
   2083   case Hexagon::LDriuh_indexed_cdnNotPt :
   2084   case Hexagon::POST_LDriuh_cNotPt :
   2085   case Hexagon::POST_LDriuh_cdnNotPt_V4 :
   2086   case Hexagon::LDriub_cNotPt :
   2087   case Hexagon::LDriub_cdnNotPt :
   2088   case Hexagon::LDriub_indexed_cNotPt :
   2089   case Hexagon::LDriub_indexed_cdnNotPt :
   2090   case Hexagon::POST_LDriub_cNotPt :
   2091   case Hexagon::POST_LDriub_cdnNotPt_V4 :
   2092   case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
   2093   case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
   2094   case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
   2095   case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
   2096   case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
   2097   case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
   2098   case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
   2099   case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
   2100   case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
   2101   case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
   2102   case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
   2103   case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
   2104   case Hexagon::ADD_ri_cNotPt :
   2105   case Hexagon::ADD_ri_cdnNotPt :
   2106   case Hexagon::ADD_rr_cNotPt :
   2107   case Hexagon::ADD_rr_cdnNotPt :
   2108   case Hexagon::XOR_rr_cNotPt :
   2109   case Hexagon::XOR_rr_cdnNotPt :
   2110   case Hexagon::AND_rr_cNotPt :
   2111   case Hexagon::AND_rr_cdnNotPt :
   2112   case Hexagon::OR_rr_cNotPt :
   2113   case Hexagon::OR_rr_cdnNotPt :
   2114   case Hexagon::SUB_rr_cNotPt :
   2115   case Hexagon::SUB_rr_cdnNotPt :
   2116   case Hexagon::COMBINE_rr_cNotPt :
   2117   case Hexagon::COMBINE_rr_cdnNotPt :
   2118   case Hexagon::ASLH_cNotPt_V4 :
   2119   case Hexagon::ASLH_cdnNotPt_V4 :
   2120   case Hexagon::ASRH_cNotPt_V4 :
   2121   case Hexagon::ASRH_cdnNotPt_V4 :
   2122   case Hexagon::SXTB_cNotPt_V4 :
   2123   case Hexagon::SXTB_cdnNotPt_V4 :
   2124   case Hexagon::SXTH_cNotPt_V4 :
   2125   case Hexagon::SXTH_cdnNotPt_V4 :
   2126   case Hexagon::ZXTB_cNotPt_V4 :
   2127   case Hexagon::ZXTB_cdnNotPt_V4 :
   2128   case Hexagon::ZXTH_cNotPt_V4 :
   2129   case Hexagon::ZXTH_cdnNotPt_V4 :
   2130 
   2131   case Hexagon::LDd_GP_cNotPt_V4 :
   2132   case Hexagon::LDb_GP_cNotPt_V4 :
   2133   case Hexagon::LDub_GP_cNotPt_V4 :
   2134   case Hexagon::LDh_GP_cNotPt_V4 :
   2135   case Hexagon::LDuh_GP_cNotPt_V4 :
   2136   case Hexagon::LDw_GP_cNotPt_V4 :
   2137   case Hexagon::STd_GP_cNotPt_V4 :
   2138   case Hexagon::STb_GP_cNotPt_V4 :
   2139   case Hexagon::STh_GP_cNotPt_V4 :
   2140   case Hexagon::STw_GP_cNotPt_V4 :
   2141   case Hexagon::LDd_GP_cdnNotPt_V4 :
   2142   case Hexagon::LDb_GP_cdnNotPt_V4 :
   2143   case Hexagon::LDub_GP_cdnNotPt_V4 :
   2144   case Hexagon::LDh_GP_cdnNotPt_V4 :
   2145   case Hexagon::LDuh_GP_cdnNotPt_V4 :
   2146   case Hexagon::LDw_GP_cdnNotPt_V4 :
   2147   case Hexagon::STd_GP_cdnNotPt_V4 :
   2148   case Hexagon::STb_GP_cdnNotPt_V4 :
   2149   case Hexagon::STh_GP_cdnNotPt_V4 :
   2150   case Hexagon::STw_GP_cdnNotPt_V4 :
   2151     return false;
   2152   }
   2153   // return *some value* to avoid compiler warning
   2154   return false;
   2155 }
   2156 
   2157 bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
   2158   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   2159   if (QII->isNewValueInst(MI))
   2160     return true;
   2161 
   2162   switch (MI->getOpcode()) {
   2163   case Hexagon::TFR_cdnNotPt:
   2164   case Hexagon::TFR_cdnPt:
   2165   case Hexagon::TFRI_cdnNotPt:
   2166   case Hexagon::TFRI_cdnPt:
   2167   case Hexagon::LDrid_cdnPt :
   2168   case Hexagon::LDrid_cdnNotPt :
   2169   case Hexagon::LDrid_indexed_cdnPt :
   2170   case Hexagon::LDrid_indexed_cdnNotPt :
   2171   case Hexagon::POST_LDrid_cdnPt_V4 :
   2172   case Hexagon::POST_LDrid_cdnNotPt_V4 :
   2173   case Hexagon::LDriw_cdnPt :
   2174   case Hexagon::LDriw_cdnNotPt :
   2175   case Hexagon::LDriw_indexed_cdnPt :
   2176   case Hexagon::LDriw_indexed_cdnNotPt :
   2177   case Hexagon::POST_LDriw_cdnPt_V4 :
   2178   case Hexagon::POST_LDriw_cdnNotPt_V4 :
   2179   case Hexagon::LDrih_cdnPt :
   2180   case Hexagon::LDrih_cdnNotPt :
   2181   case Hexagon::LDrih_indexed_cdnPt :
   2182   case Hexagon::LDrih_indexed_cdnNotPt :
   2183   case Hexagon::POST_LDrih_cdnPt_V4 :
   2184   case Hexagon::POST_LDrih_cdnNotPt_V4 :
   2185   case Hexagon::LDrib_cdnPt :
   2186   case Hexagon::LDrib_cdnNotPt :
   2187   case Hexagon::LDrib_indexed_cdnPt :
   2188   case Hexagon::LDrib_indexed_cdnNotPt :
   2189   case Hexagon::POST_LDrib_cdnPt_V4 :
   2190   case Hexagon::POST_LDrib_cdnNotPt_V4 :
   2191   case Hexagon::LDriuh_cdnPt :
   2192   case Hexagon::LDriuh_cdnNotPt :
   2193   case Hexagon::LDriuh_indexed_cdnPt :
   2194   case Hexagon::LDriuh_indexed_cdnNotPt :
   2195   case Hexagon::POST_LDriuh_cdnPt_V4 :
   2196   case Hexagon::POST_LDriuh_cdnNotPt_V4 :
   2197   case Hexagon::LDriub_cdnPt :
   2198   case Hexagon::LDriub_cdnNotPt :
   2199   case Hexagon::LDriub_indexed_cdnPt :
   2200   case Hexagon::LDriub_indexed_cdnNotPt :
   2201   case Hexagon::POST_LDriub_cdnPt_V4 :
   2202   case Hexagon::POST_LDriub_cdnNotPt_V4 :
   2203 
   2204   case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
   2205   case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
   2206   case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
   2207   case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
   2208   case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
   2209   case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
   2210   case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
   2211   case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
   2212   case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
   2213   case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
   2214   case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
   2215   case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
   2216 
   2217 // Coditional add
   2218   case Hexagon::ADD_ri_cdnPt:
   2219   case Hexagon::ADD_ri_cdnNotPt:
   2220   case Hexagon::ADD_rr_cdnPt:
   2221   case Hexagon::ADD_rr_cdnNotPt:
   2222 
   2223   // Conditional logical operations
   2224   case Hexagon::XOR_rr_cdnPt :
   2225   case Hexagon::XOR_rr_cdnNotPt :
   2226   case Hexagon::AND_rr_cdnPt :
   2227   case Hexagon::AND_rr_cdnNotPt :
   2228   case Hexagon::OR_rr_cdnPt :
   2229   case Hexagon::OR_rr_cdnNotPt :
   2230 
   2231   // Conditonal subtract
   2232   case Hexagon::SUB_rr_cdnPt :
   2233   case Hexagon::SUB_rr_cdnNotPt :
   2234 
   2235   // Conditional combine
   2236   case Hexagon::COMBINE_rr_cdnPt :
   2237   case Hexagon::COMBINE_rr_cdnNotPt :
   2238 
   2239   // Conditional shift operations
   2240   case Hexagon::ASLH_cdnPt_V4:
   2241   case Hexagon::ASLH_cdnNotPt_V4:
   2242   case Hexagon::ASRH_cdnPt_V4:
   2243   case Hexagon::ASRH_cdnNotPt_V4:
   2244   case Hexagon::SXTB_cdnPt_V4:
   2245   case Hexagon::SXTB_cdnNotPt_V4:
   2246   case Hexagon::SXTH_cdnPt_V4:
   2247   case Hexagon::SXTH_cdnNotPt_V4:
   2248   case Hexagon::ZXTB_cdnPt_V4:
   2249   case Hexagon::ZXTB_cdnNotPt_V4:
   2250   case Hexagon::ZXTH_cdnPt_V4:
   2251   case Hexagon::ZXTH_cdnNotPt_V4:
   2252 
   2253   // Conditional stores
   2254   case Hexagon::STrib_imm_cdnPt_V4 :
   2255   case Hexagon::STrib_imm_cdnNotPt_V4 :
   2256   case Hexagon::STrib_cdnPt_V4 :
   2257   case Hexagon::STrib_cdnNotPt_V4 :
   2258   case Hexagon::STrib_indexed_cdnPt_V4 :
   2259   case Hexagon::STrib_indexed_cdnNotPt_V4 :
   2260   case Hexagon::POST_STbri_cdnPt_V4 :
   2261   case Hexagon::POST_STbri_cdnNotPt_V4 :
   2262   case Hexagon::STrib_indexed_shl_cdnPt_V4 :
   2263   case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
   2264 
   2265   // Store doubleword conditionally
   2266   case Hexagon::STrid_indexed_cdnPt_V4 :
   2267   case Hexagon::STrid_indexed_cdnNotPt_V4 :
   2268   case Hexagon::STrid_indexed_shl_cdnPt_V4 :
   2269   case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
   2270   case Hexagon::POST_STdri_cdnPt_V4 :
   2271   case Hexagon::POST_STdri_cdnNotPt_V4 :
   2272 
   2273   // Store halfword conditionally
   2274   case Hexagon::STrih_cdnPt_V4 :
   2275   case Hexagon::STrih_cdnNotPt_V4 :
   2276   case Hexagon::STrih_indexed_cdnPt_V4 :
   2277   case Hexagon::STrih_indexed_cdnNotPt_V4 :
   2278   case Hexagon::STrih_imm_cdnPt_V4 :
   2279   case Hexagon::STrih_imm_cdnNotPt_V4 :
   2280   case Hexagon::STrih_indexed_shl_cdnPt_V4 :
   2281   case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
   2282   case Hexagon::POST_SThri_cdnPt_V4 :
   2283   case Hexagon::POST_SThri_cdnNotPt_V4 :
   2284 
   2285   // Store word conditionally
   2286   case Hexagon::STriw_cdnPt_V4 :
   2287   case Hexagon::STriw_cdnNotPt_V4 :
   2288   case Hexagon::STriw_indexed_cdnPt_V4 :
   2289   case Hexagon::STriw_indexed_cdnNotPt_V4 :
   2290   case Hexagon::STriw_imm_cdnPt_V4 :
   2291   case Hexagon::STriw_imm_cdnNotPt_V4 :
   2292   case Hexagon::STriw_indexed_shl_cdnPt_V4 :
   2293   case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
   2294   case Hexagon::POST_STwri_cdnPt_V4 :
   2295   case Hexagon::POST_STwri_cdnNotPt_V4 :
   2296 
   2297   case Hexagon::LDd_GP_cdnPt_V4:
   2298   case Hexagon::LDd_GP_cdnNotPt_V4:
   2299   case Hexagon::LDb_GP_cdnPt_V4:
   2300   case Hexagon::LDb_GP_cdnNotPt_V4:
   2301   case Hexagon::LDub_GP_cdnPt_V4:
   2302   case Hexagon::LDub_GP_cdnNotPt_V4:
   2303   case Hexagon::LDh_GP_cdnPt_V4:
   2304   case Hexagon::LDh_GP_cdnNotPt_V4:
   2305   case Hexagon::LDuh_GP_cdnPt_V4:
   2306   case Hexagon::LDuh_GP_cdnNotPt_V4:
   2307   case Hexagon::LDw_GP_cdnPt_V4:
   2308   case Hexagon::LDw_GP_cdnNotPt_V4:
   2309 
   2310   case Hexagon::STd_GP_cdnPt_V4:
   2311   case Hexagon::STd_GP_cdnNotPt_V4:
   2312   case Hexagon::STb_GP_cdnPt_V4:
   2313   case Hexagon::STb_GP_cdnNotPt_V4:
   2314   case Hexagon::STh_GP_cdnPt_V4:
   2315   case Hexagon::STh_GP_cdnNotPt_V4:
   2316   case Hexagon::STw_GP_cdnPt_V4:
   2317   case Hexagon::STw_GP_cdnNotPt_V4:
   2318     return true;
   2319   }
   2320   return false;
   2321 }
   2322 
   2323 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
   2324                                                const HexagonInstrInfo *QII) {
   2325   assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
   2326 #ifndef NDEBUG
   2327   // Post Increment means duplicates. Use dense map to find duplicates in the
   2328   // list. Caution: Densemap initializes with the minimum of 64 buckets,
   2329   // whereas there are at most 5 operands in the post increment.
   2330   DenseMap<unsigned,  unsigned> DefRegsSet;
   2331   for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
   2332     if (MI->getOperand(opNum).isReg() &&
   2333         MI->getOperand(opNum).isDef()) {
   2334       DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
   2335     }
   2336 
   2337   for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
   2338     if (MI->getOperand(opNum).isReg() &&
   2339         MI->getOperand(opNum).isUse()) {
   2340       if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
   2341         return MI->getOperand(opNum);
   2342       }
   2343     }
   2344 #else
   2345   if (MI->getDesc().mayLoad()) {
   2346     // The 2nd operand is always the post increment operand in load.
   2347     assert(MI->getOperand(1).isReg() &&
   2348                 "Post increment operand has be to a register.");
   2349     return (MI->getOperand(1));
   2350   }
   2351   if (MI->getDesc().mayStore()) {
   2352     // The 1st operand is always the post increment operand in store.
   2353     assert(MI->getOperand(0).isReg() &&
   2354                 "Post increment operand has be to a register.");
   2355     return (MI->getOperand(0));
   2356   }
   2357 #endif
   2358   // we should never come here.
   2359   llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
   2360 }
   2361 
   2362 // get the value being stored
   2363 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
   2364   // value being stored is always the last operand.
   2365   return (MI->getOperand(MI->getNumOperands()-1));
   2366 }
   2367 
   2368 // can be new value store?
   2369 // Following restrictions are to be respected in convert a store into
   2370 // a new value store.
   2371 // 1. If an instruction uses auto-increment, its address register cannot
   2372 //    be a new-value register. Arch Spec 5.4.2.1
   2373 // 2. If an instruction uses absolute-set addressing mode,
   2374 //    its address register cannot be a new-value register.
   2375 //    Arch Spec 5.4.2.1.TODO: This is not enabled as
   2376 //    as absolute-set address mode patters are not implemented.
   2377 // 3. If an instruction produces a 64-bit result, its registers cannot be used
   2378 //    as new-value registers. Arch Spec 5.4.2.2.
   2379 // 4. If the instruction that sets a new-value register is conditional, then
   2380 //    the instruction that uses the new-value register must also be conditional,
   2381 //    and both must always have their predicates evaluate identically.
   2382 //    Arch Spec 5.4.2.3.
   2383 // 5. There is an implied restriction of a packet can not have another store,
   2384 //    if there is a  new value store in the packet. Corollary, if there is
   2385 //    already a store in a packet, there can not be a new value store.
   2386 //    Arch Spec: 3.4.4.2
   2387 bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
   2388                 MachineInstr *PacketMI, unsigned DepReg,
   2389                 std::map <MachineInstr*, SUnit*> MIToSUnit)
   2390 {
   2391   // Make sure we are looking at the store
   2392   if (!IsNewifyStore(MI))
   2393     return false;
   2394 
   2395   // Make sure there is dependency and can be new value'ed
   2396   if (GetStoreValueOperand(MI).isReg() &&
   2397       GetStoreValueOperand(MI).getReg() != DepReg)
   2398     return false;
   2399 
   2400   const HexagonRegisterInfo* QRI =
   2401                             (const HexagonRegisterInfo *) TM.getRegisterInfo();
   2402   const MCInstrDesc& MCID = PacketMI->getDesc();
   2403   // first operand is always the result
   2404 
   2405   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   2406   const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
   2407 
   2408   // if there is already an store in the packet, no can do new value store
   2409   // Arch Spec 3.4.4.2.
   2410   for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
   2411          VE = CurrentPacketMIs.end();
   2412        (VI != VE); ++VI) {
   2413     SUnit* PacketSU = MIToSUnit[*VI];
   2414     if (PacketSU->getInstr()->getDesc().mayStore() ||
   2415         // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
   2416         // then we don't need this
   2417         PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
   2418         PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
   2419       return false;
   2420   }
   2421 
   2422   if (PacketRC == &Hexagon::DoubleRegsRegClass) {
   2423     // new value store constraint: double regs can not feed into new value store
   2424     // arch spec section: 5.4.2.2
   2425     return false;
   2426   }
   2427 
   2428   // Make sure it's NOT the post increment register that we are going to
   2429   // new value.
   2430   if (QII->isPostIncrement(MI) &&
   2431       MI->getDesc().mayStore() &&
   2432       GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
   2433     return false;
   2434   }
   2435 
   2436   if (QII->isPostIncrement(PacketMI) &&
   2437       PacketMI->getDesc().mayLoad() &&
   2438       GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
   2439     // if source is post_inc, or absolute-set addressing,
   2440     // it can not feed into new value store
   2441     //  r3 = memw(r2++#4)
   2442     //  memw(r30 + #-1404) = r2.new -> can not be new value store
   2443     // arch spec section: 5.4.2.1
   2444     return false;
   2445   }
   2446 
   2447   // If the source that feeds the store is predicated, new value store must
   2448   // also be also predicated.
   2449   if (QII->isPredicated(PacketMI)) {
   2450     if (!QII->isPredicated(MI))
   2451       return false;
   2452 
   2453     // Check to make sure that they both will have their predicates
   2454     // evaluate identically
   2455     unsigned predRegNumSrc = 0;
   2456     unsigned predRegNumDst = 0;
   2457     const TargetRegisterClass* predRegClass = NULL;
   2458 
   2459     // Get predicate register used in the source instruction
   2460     for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
   2461       if ( PacketMI->getOperand(opNum).isReg())
   2462       predRegNumSrc = PacketMI->getOperand(opNum).getReg();
   2463       predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
   2464       if (predRegClass == &Hexagon::PredRegsRegClass) {
   2465         break;
   2466       }
   2467     }
   2468     assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
   2469         ("predicate register not found in a predicated PacketMI instruction"));
   2470 
   2471     // Get predicate register used in new-value store instruction
   2472     for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
   2473       if ( MI->getOperand(opNum).isReg())
   2474       predRegNumDst = MI->getOperand(opNum).getReg();
   2475       predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
   2476       if (predRegClass == &Hexagon::PredRegsRegClass) {
   2477         break;
   2478       }
   2479     }
   2480     assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
   2481             ("predicate register not found in a predicated MI instruction"));
   2482 
   2483     // New-value register producer and user (store) need to satisfy these
   2484     // constraints:
   2485     // 1) Both instructions should be predicated on the same register.
   2486     // 2) If producer of the new-value register is .new predicated then store
   2487     // should also be .new predicated and if producer is not .new predicated
   2488     // then store should not be .new predicated.
   2489     // 3) Both new-value register producer and user should have same predicate
   2490     // sense, i.e, either both should be negated or both should be none negated.
   2491 
   2492     if (( predRegNumDst != predRegNumSrc) ||
   2493           isDotNewInst(PacketMI) != isDotNewInst(MI)  ||
   2494           GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
   2495       return false;
   2496     }
   2497   }
   2498 
   2499   // Make sure that other than the new-value register no other store instruction
   2500   // register has been modified in the same packet. Predicate registers can be
   2501   // modified by they should not be modified between the producer and the store
   2502   // instruction as it will make them both conditional on different values.
   2503   // We already know this to be true for all the instructions before and
   2504   // including PacketMI. Howerver, we need to perform the check for the
   2505   // remaining instructions in the packet.
   2506 
   2507   std::vector<MachineInstr*>::iterator VI;
   2508   std::vector<MachineInstr*>::iterator VE;
   2509   unsigned StartCheck = 0;
   2510 
   2511   for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
   2512       (VI != VE); ++VI) {
   2513     SUnit* TempSU = MIToSUnit[*VI];
   2514     MachineInstr* TempMI = TempSU->getInstr();
   2515 
   2516     // Following condition is true for all the instructions until PacketMI is
   2517     // reached (StartCheck is set to 0 before the for loop).
   2518     // StartCheck flag is 1 for all the instructions after PacketMI.
   2519     if (TempMI != PacketMI && !StartCheck) // start processing only after
   2520       continue;                            // encountering PacketMI
   2521 
   2522     StartCheck = 1;
   2523     if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
   2524       continue;
   2525 
   2526     for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
   2527       if (MI->getOperand(opNum).isReg() &&
   2528           TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
   2529                                                QRI))
   2530         return false;
   2531     }
   2532   }
   2533 
   2534   // Make sure that for non POST_INC stores:
   2535   // 1. The only use of reg is DepReg and no other registers.
   2536   //    This handles V4 base+index registers.
   2537   //    The following store can not be dot new.
   2538   //    Eg.   r0 = add(r0, #3)a
   2539   //          memw(r1+r0<<#2) = r0
   2540   if (!QII->isPostIncrement(MI) &&
   2541       GetStoreValueOperand(MI).isReg() &&
   2542       GetStoreValueOperand(MI).getReg() == DepReg) {
   2543     for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
   2544       if (MI->getOperand(opNum).isReg() &&
   2545           MI->getOperand(opNum).getReg() == DepReg) {
   2546         return false;
   2547       }
   2548     }
   2549     // 2. If data definition is because of implicit definition of the register,
   2550     //    do not newify the store. Eg.
   2551     //    %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
   2552     //    STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
   2553     for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
   2554       if (PacketMI->getOperand(opNum).isReg() &&
   2555           PacketMI->getOperand(opNum).getReg() == DepReg &&
   2556           PacketMI->getOperand(opNum).isDef() &&
   2557           PacketMI->getOperand(opNum).isImplicit()) {
   2558         return false;
   2559       }
   2560     }
   2561   }
   2562 
   2563   // Can be dot new store.
   2564   return true;
   2565 }
   2566 
   2567 // can this MI to promoted to either
   2568 // new value store or new value jump
   2569 bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
   2570                 SUnit *PacketSU, unsigned DepReg,
   2571                 std::map <MachineInstr*, SUnit*> MIToSUnit,
   2572                 MachineBasicBlock::iterator &MII)
   2573 {
   2574 
   2575   const HexagonRegisterInfo* QRI =
   2576                             (const HexagonRegisterInfo *) TM.getRegisterInfo();
   2577   if (!QRI->Subtarget.hasV4TOps() ||
   2578       !IsNewifyStore(MI))
   2579     return false;
   2580 
   2581   MachineInstr *PacketMI = PacketSU->getInstr();
   2582 
   2583   // Check to see the store can be new value'ed.
   2584   if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
   2585     return true;
   2586 
   2587   // Check to see the compare/jump can be new value'ed.
   2588   // This is done as a pass on its own. Don't need to check it here.
   2589   return false;
   2590 }
   2591 
   2592 // Check to see if an instruction can be dot new
   2593 // There are three kinds.
   2594 // 1. dot new on predicate - V2/V3/V4
   2595 // 2. dot new on stores NV/ST - V4
   2596 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
   2597 bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
   2598                               SUnit *PacketSU, unsigned DepReg,
   2599                               std::map <MachineInstr*, SUnit*> MIToSUnit,
   2600                               MachineBasicBlock::iterator &MII,
   2601                               const TargetRegisterClass* RC )
   2602 {
   2603   // already a dot new instruction
   2604   if (isDotNewInst(MI) && !IsNewifyStore(MI))
   2605     return false;
   2606 
   2607   if (!isNewifiable(MI))
   2608     return false;
   2609 
   2610   // predicate .new
   2611   if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
   2612       return true;
   2613   else if (RC != &Hexagon::PredRegsRegClass &&
   2614       !IsNewifyStore(MI)) // MI is not a new-value store
   2615     return false;
   2616   else {
   2617     // Create a dot new machine instruction to see if resources can be
   2618     // allocated. If not, bail out now.
   2619     const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   2620     int NewOpcode = GetDotNewOp(MI->getOpcode());
   2621     const MCInstrDesc &desc = QII->get(NewOpcode);
   2622     DebugLoc dl;
   2623     MachineInstr *NewMI =
   2624                     MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
   2625     bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
   2626     MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
   2627 
   2628     if (!ResourcesAvailable)
   2629       return false;
   2630 
   2631     // new value store only
   2632     // new new value jump generated as a passes
   2633     if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
   2634       return false;
   2635     }
   2636   }
   2637   return true;
   2638 }
   2639 
   2640 // Go through the packet instructions and search for anti dependency
   2641 // between them and DepReg from MI
   2642 // Consider this case:
   2643 // Trying to add
   2644 // a) %R1<def> = TFRI_cdNotPt %P3, 2
   2645 // to this packet:
   2646 // {
   2647 //   b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
   2648 //   c) %P3<def> = TFR_PdRs %R23
   2649 //   d) %R1<def> = TFRI_cdnPt %P3, 4
   2650 //  }
   2651 // The P3 from a) and d) will be complements after
   2652 // a)'s P3 is converted to .new form
   2653 // Anti Dep between c) and b) is irrelevant for this case
   2654 bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
   2655       unsigned DepReg,
   2656       std::map <MachineInstr*, SUnit*> MIToSUnit) {
   2657 
   2658   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   2659   SUnit* PacketSUDep = MIToSUnit[MI];
   2660 
   2661   for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
   2662        VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
   2663 
   2664     // We only care for dependencies to predicated instructions
   2665     if(!QII->isPredicated(*VIN)) continue;
   2666 
   2667     // Scheduling Unit for current insn in the packet
   2668     SUnit* PacketSU = MIToSUnit[*VIN];
   2669 
   2670     // Look at dependencies between current members of the packet
   2671     // and predicate defining instruction MI.
   2672     // Make sure that dependency is on the exact register
   2673     // we care about.
   2674     if (PacketSU->isSucc(PacketSUDep)) {
   2675       for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
   2676         if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
   2677             (PacketSU->Succs[i].getKind() == SDep::Anti) &&
   2678             (PacketSU->Succs[i].getReg() == DepReg)) {
   2679           return true;
   2680         }
   2681       }
   2682     }
   2683   }
   2684 
   2685   return false;
   2686 }
   2687 
   2688 
   2689 // Given two predicated instructions, this function detects whether
   2690 // the predicates are complements
   2691 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
   2692      MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
   2693 
   2694   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   2695   // Currently can only reason about conditional transfers
   2696   if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
   2697     return false;
   2698   }
   2699 
   2700   // Scheduling unit for candidate
   2701   SUnit* SU = MIToSUnit[MI1];
   2702 
   2703   // One corner case deals with the following scenario:
   2704   // Trying to add
   2705   // a) %R24<def> = TFR_cPt %P0, %R25
   2706   // to this packet:
   2707   //
   2708   // {
   2709   //   b) %R25<def> = TFR_cNotPt %P0, %R24
   2710   //   c) %P0<def> = CMPEQri %R26, 1
   2711   // }
   2712   //
   2713   // On general check a) and b) are complements, but
   2714   // presence of c) will convert a) to .new form, and
   2715   // then it is not a complement
   2716   // We attempt to detect it by analyzing  existing
   2717   // dependencies in the packet
   2718 
   2719   // Analyze relationships between all existing members of the packet.
   2720   // Look for Anti dependecy on the same predicate reg
   2721   // as used in the candidate
   2722   for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
   2723        VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
   2724 
   2725     // Scheduling Unit for current insn in the packet
   2726     SUnit* PacketSU = MIToSUnit[*VIN];
   2727 
   2728     // If this instruction in the packet is succeeded by the candidate...
   2729     if (PacketSU->isSucc(SU)) {
   2730       for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
   2731         // The corner case exist when there is true data
   2732         // dependency between candidate and one of current
   2733         // packet members, this dep is on predicate reg, and
   2734         // there already exist anti dep on the same pred in
   2735         // the packet.
   2736         if (PacketSU->Succs[i].getSUnit() == SU &&
   2737             Hexagon::PredRegsRegClass.contains(
   2738               PacketSU->Succs[i].getReg()) &&
   2739             PacketSU->Succs[i].getKind() == SDep::Data &&
   2740             // Here I know that *VIN is predicate setting instruction
   2741             // with true data dep to candidate on the register
   2742             // we care about - c) in the above example.
   2743             // Now I need to see if there is an anti dependency
   2744             // from c) to any other instruction in the
   2745             // same packet on the pred reg of interest
   2746             RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
   2747                                         MIToSUnit)) {
   2748            return false;
   2749         }
   2750       }
   2751     }
   2752   }
   2753 
   2754   // If the above case does not apply, check regular
   2755   // complement condition.
   2756   // Check that the predicate register is the same and
   2757   // that the predicate sense is different
   2758   // We also need to differentiate .old vs. .new:
   2759   // !p0 is not complimentary to p0.new
   2760   return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
   2761           (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
   2762           (isDotNewInst(MI1) == isDotNewInst(MI2)));
   2763 }
   2764 
   2765 // initPacketizerState - Initialize packetizer flags
   2766 void HexagonPacketizerList::initPacketizerState() {
   2767 
   2768   Dependence = false;
   2769   PromotedToDotNew = false;
   2770   GlueToNewValueJump = false;
   2771   GlueAllocframeStore = false;
   2772   FoundSequentialDependence = false;
   2773 
   2774   return;
   2775 }
   2776 
   2777 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
   2778 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
   2779                                                     MachineBasicBlock *MBB) {
   2780   if (MI->isDebugValue())
   2781     return true;
   2782 
   2783   // We must print out inline assembly
   2784   if (MI->isInlineAsm())
   2785     return false;
   2786 
   2787   // We check if MI has any functional units mapped to it.
   2788   // If it doesn't, we ignore the instruction.
   2789   const MCInstrDesc& TID = MI->getDesc();
   2790   unsigned SchedClass = TID.getSchedClass();
   2791   const InstrStage* IS =
   2792                     ResourceTracker->getInstrItins()->beginStage(SchedClass);
   2793   unsigned FuncUnits = IS->getUnits();
   2794   return !FuncUnits;
   2795 }
   2796 
   2797 // isSoloInstruction: - Returns true for instructions that must be
   2798 // scheduled in their own packet.
   2799 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
   2800 
   2801   if (MI->isInlineAsm())
   2802     return true;
   2803 
   2804   if (MI->isEHLabel())
   2805     return true;
   2806 
   2807   // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
   2808   // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
   2809   // They must not be grouped with other instructions in a packet.
   2810   if (IsSchedBarrier(MI))
   2811     return true;
   2812 
   2813   return false;
   2814 }
   2815 
   2816 // isLegalToPacketizeTogether:
   2817 // SUI is the current instruction that is out side of the current packet.
   2818 // SUJ is the current instruction inside the current packet against which that
   2819 // SUI will be packetized.
   2820 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
   2821   MachineInstr *I = SUI->getInstr();
   2822   MachineInstr *J = SUJ->getInstr();
   2823   assert(I && J && "Unable to packetize null instruction!");
   2824 
   2825   const MCInstrDesc &MCIDI = I->getDesc();
   2826   const MCInstrDesc &MCIDJ = J->getDesc();
   2827 
   2828   MachineBasicBlock::iterator II = I;
   2829 
   2830   const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
   2831   const HexagonRegisterInfo* QRI =
   2832                       (const HexagonRegisterInfo *) TM.getRegisterInfo();
   2833   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   2834 
   2835   // Inline asm cannot go in the packet.
   2836   if (I->getOpcode() == Hexagon::INLINEASM)
   2837     llvm_unreachable("Should not meet inline asm here!");
   2838 
   2839   if (isSoloInstruction(I))
   2840     llvm_unreachable("Should not meet solo instr here!");
   2841 
   2842   // A save callee-save register function call can only be in a packet
   2843   // with instructions that don't write to the callee-save registers.
   2844   if ((QII->isSaveCalleeSavedRegsCall(I) &&
   2845        DoesModifyCalleeSavedReg(J, QRI)) ||
   2846       (QII->isSaveCalleeSavedRegsCall(J) &&
   2847        DoesModifyCalleeSavedReg(I, QRI))) {
   2848     Dependence = true;
   2849     return false;
   2850   }
   2851 
   2852   // Two control flow instructions cannot go in the same packet.
   2853   if (IsControlFlow(I) && IsControlFlow(J)) {
   2854     Dependence = true;
   2855     return false;
   2856   }
   2857 
   2858   // A LoopN instruction cannot appear in the same packet as a jump or call.
   2859   if (IsLoopN(I) && (   IsDirectJump(J)
   2860                      || MCIDJ.isCall()
   2861                      || QII->isDeallocRet(J))) {
   2862     Dependence = true;
   2863     return false;
   2864   }
   2865   if (IsLoopN(J) && (   IsDirectJump(I)
   2866                      || MCIDI.isCall()
   2867                      || QII->isDeallocRet(I))) {
   2868     Dependence = true;
   2869     return false;
   2870   }
   2871 
   2872   // dealloc_return cannot appear in the same packet as a conditional or
   2873   // unconditional jump.
   2874   if (QII->isDeallocRet(I) && (   MCIDJ.isBranch()
   2875                                || MCIDJ.isCall()
   2876                                || MCIDJ.isBarrier())) {
   2877     Dependence = true;
   2878     return false;
   2879   }
   2880 
   2881 
   2882   // V4 allows dual store. But does not allow second store, if the
   2883   // first store is not in SLOT0. New value store, new value jump,
   2884   // dealloc_return and memop always take SLOT0.
   2885   // Arch spec 3.4.4.2
   2886   if (QRI->Subtarget.hasV4TOps()) {
   2887     if (MCIDI.mayStore() && MCIDJ.mayStore() &&
   2888        (QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
   2889       Dependence = true;
   2890       return false;
   2891     }
   2892 
   2893     if ((QII->isMemOp(J) && MCIDI.mayStore())
   2894         || (MCIDJ.mayStore() && QII->isMemOp(I))
   2895         || (QII->isMemOp(J) && QII->isMemOp(I))) {
   2896       Dependence = true;
   2897       return false;
   2898     }
   2899 
   2900     //if dealloc_return
   2901     if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
   2902       Dependence = true;
   2903       return false;
   2904     }
   2905 
   2906     // If an instruction feeds new value jump, glue it.
   2907     MachineBasicBlock::iterator NextMII = I;
   2908     ++NextMII;
   2909     MachineInstr *NextMI = NextMII;
   2910 
   2911     if (QII->isNewValueJump(NextMI)) {
   2912 
   2913       bool secondRegMatch = false;
   2914       bool maintainNewValueJump = false;
   2915 
   2916       if (NextMI->getOperand(1).isReg() &&
   2917           I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
   2918         secondRegMatch = true;
   2919         maintainNewValueJump = true;
   2920       }
   2921 
   2922       if (!secondRegMatch &&
   2923            I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
   2924         maintainNewValueJump = true;
   2925       }
   2926 
   2927       for (std::vector<MachineInstr*>::iterator
   2928             VI = CurrentPacketMIs.begin(),
   2929              VE = CurrentPacketMIs.end();
   2930            (VI != VE && maintainNewValueJump); ++VI) {
   2931         SUnit* PacketSU = MIToSUnit[*VI];
   2932 
   2933         // NVJ can not be part of the dual jump - Arch Spec: section 7.8
   2934         if (PacketSU->getInstr()->getDesc().isCall()) {
   2935           Dependence = true;
   2936           break;
   2937         }
   2938         // Validate
   2939         // 1. Packet does not have a store in it.
   2940         // 2. If the first operand of the nvj is newified, and the second
   2941         //    operand is also a reg, it (second reg) is not defined in
   2942         //    the same packet.
   2943         // 3. If the second operand of the nvj is newified, (which means
   2944         //    first operand is also a reg), first reg is not defined in
   2945         //    the same packet.
   2946         if (PacketSU->getInstr()->getDesc().mayStore()               ||
   2947             PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
   2948             // Check #2.
   2949             (!secondRegMatch && NextMI->getOperand(1).isReg() &&
   2950              PacketSU->getInstr()->modifiesRegister(
   2951                                NextMI->getOperand(1).getReg(), QRI)) ||
   2952             // Check #3.
   2953             (secondRegMatch &&
   2954              PacketSU->getInstr()->modifiesRegister(
   2955                                NextMI->getOperand(0).getReg(), QRI))) {
   2956           Dependence = true;
   2957           break;
   2958         }
   2959       }
   2960       if (!Dependence)
   2961         GlueToNewValueJump = true;
   2962       else
   2963         return false;
   2964     }
   2965   }
   2966 
   2967   if (SUJ->isSucc(SUI)) {
   2968     for (unsigned i = 0;
   2969          (i < SUJ->Succs.size()) && !FoundSequentialDependence;
   2970          ++i) {
   2971 
   2972       if (SUJ->Succs[i].getSUnit() != SUI) {
   2973         continue;
   2974       }
   2975 
   2976       SDep::Kind DepType = SUJ->Succs[i].getKind();
   2977 
   2978       // For direct calls:
   2979       // Ignore register dependences for call instructions for
   2980       // packetization purposes except for those due to r31 and
   2981       // predicate registers.
   2982       //
   2983       // For indirect calls:
   2984       // Same as direct calls + check for true dependences to the register
   2985       // used in the indirect call.
   2986       //
   2987       // We completely ignore Order dependences for call instructions
   2988       //
   2989       // For returns:
   2990       // Ignore register dependences for return instructions like jumpr,
   2991       // dealloc return unless we have dependencies on the explicit uses
   2992       // of the registers used by jumpr (like r31) or dealloc return
   2993       // (like r29 or r30).
   2994       //
   2995       // TODO: Currently, jumpr is handling only return of r31. So, the
   2996       // following logic (specificaly IsCallDependent) is working fine.
   2997       // We need to enable jumpr for register other than r31 and then,
   2998       // we need to rework the last part, where it handles indirect call
   2999       // of that (IsCallDependent) function. Bug 6216 is opened for this.
   3000       //
   3001       unsigned DepReg = 0;
   3002       const TargetRegisterClass* RC = NULL;
   3003       if (DepType == SDep::Data) {
   3004         DepReg = SUJ->Succs[i].getReg();
   3005         RC = QRI->getMinimalPhysRegClass(DepReg);
   3006       }
   3007       if ((MCIDI.isCall() || MCIDI.isReturn()) &&
   3008           (!IsRegDependence(DepType) ||
   3009             !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
   3010         /* do nothing */
   3011       }
   3012 
   3013       // For instructions that can be promoted to dot-new, try to promote.
   3014       else if ((DepType == SDep::Data) &&
   3015                CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
   3016                PromoteToDotNew(I, DepType, II, RC)) {
   3017         PromotedToDotNew = true;
   3018         /* do nothing */
   3019       }
   3020 
   3021       else if ((DepType == SDep::Data) &&
   3022                (QII->isNewValueJump(I))) {
   3023         /* do nothing */
   3024       }
   3025 
   3026       // For predicated instructions, if the predicates are complements
   3027       // then there can be no dependence.
   3028       else if (QII->isPredicated(I) &&
   3029                QII->isPredicated(J) &&
   3030           ArePredicatesComplements(I, J, MIToSUnit)) {
   3031         /* do nothing */
   3032 
   3033       }
   3034       else if (IsDirectJump(I) &&
   3035                !MCIDJ.isBranch() &&
   3036                !MCIDJ.isCall() &&
   3037                (DepType == SDep::Order)) {
   3038         // Ignore Order dependences between unconditional direct branches
   3039         // and non-control-flow instructions
   3040         /* do nothing */
   3041       }
   3042       else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
   3043                (DepType != SDep::Output)) {
   3044         // Ignore all dependences for jumps except for true and output
   3045         // dependences
   3046         /* do nothing */
   3047       }
   3048 
   3049       // Ignore output dependences due to superregs. We can
   3050       // write to two different subregisters of R1:0 for instance
   3051       // in the same cycle
   3052       //
   3053 
   3054       //
   3055       // Let the
   3056       // If neither I nor J defines DepReg, then this is a
   3057       // superfluous output dependence. The dependence must be of the
   3058       // form:
   3059       //  R0 = ...
   3060       //  R1 = ...
   3061       // and there is an output dependence between the two instructions
   3062       // with
   3063       // DepReg = D0
   3064       // We want to ignore these dependences.
   3065       // Ideally, the dependence constructor should annotate such
   3066       // dependences. We can then avoid this relatively expensive check.
   3067       //
   3068       else if (DepType == SDep::Output) {
   3069         // DepReg is the register that's responsible for the dependence.
   3070         unsigned DepReg = SUJ->Succs[i].getReg();
   3071 
   3072         // Check if I and J really defines DepReg.
   3073         if (I->definesRegister(DepReg) ||
   3074             J->definesRegister(DepReg)) {
   3075           FoundSequentialDependence = true;
   3076           break;
   3077         }
   3078       }
   3079 
   3080       // We ignore Order dependences for
   3081       // 1. Two loads unless they are volatile.
   3082       // 2. Two stores in V4 unless they are volatile.
   3083       else if ((DepType == SDep::Order) &&
   3084                !I->hasOrderedMemoryRef() &&
   3085                !J->hasOrderedMemoryRef()) {
   3086         if (QRI->Subtarget.hasV4TOps() &&
   3087             // hexagonv4 allows dual store.
   3088             MCIDI.mayStore() && MCIDJ.mayStore()) {
   3089           /* do nothing */
   3090         }
   3091         // store followed by store-- not OK on V2
   3092         // store followed by load -- not OK on all (OK if addresses
   3093         // are not aliased)
   3094         // load followed by store -- OK on all
   3095         // load followed by load  -- OK on all
   3096         else if ( !MCIDJ.mayStore()) {
   3097           /* do nothing */
   3098         }
   3099         else {
   3100           FoundSequentialDependence = true;
   3101           break;
   3102         }
   3103       }
   3104 
   3105       // For V4, special case ALLOCFRAME. Even though there is dependency
   3106       // between ALLOCAFRAME and subsequent store, allow it to be
   3107       // packetized in a same packet. This implies that the store is using
   3108       // caller's SP. Hense, offset needs to be updated accordingly.
   3109       else if (DepType == SDep::Data
   3110                && QRI->Subtarget.hasV4TOps()
   3111                && J->getOpcode() == Hexagon::ALLOCFRAME
   3112                && (I->getOpcode() == Hexagon::STrid
   3113                    || I->getOpcode() == Hexagon::STriw
   3114                    || I->getOpcode() == Hexagon::STrib)
   3115                && I->getOperand(0).getReg() == QRI->getStackRegister()
   3116                && QII->isValidOffset(I->getOpcode(),
   3117                                      I->getOperand(1).getImm() -
   3118                                      (FrameSize + HEXAGON_LRFP_SIZE)))
   3119       {
   3120         GlueAllocframeStore = true;
   3121         // Since this store is to be glued with allocframe in the same
   3122         // packet, it will use SP of the previous stack frame, i.e
   3123         // caller's SP. Therefore, we need to recalculate offset according
   3124         // to this change.
   3125         I->getOperand(1).setImm(I->getOperand(1).getImm() -
   3126                                         (FrameSize + HEXAGON_LRFP_SIZE));
   3127       }
   3128 
   3129       //
   3130       // Skip over anti-dependences. Two instructions that are
   3131       // anti-dependent can share a packet
   3132       //
   3133       else if (DepType != SDep::Anti) {
   3134         FoundSequentialDependence = true;
   3135         break;
   3136       }
   3137     }
   3138 
   3139     if (FoundSequentialDependence) {
   3140       Dependence = true;
   3141       return false;
   3142     }
   3143   }
   3144 
   3145   return true;
   3146 }
   3147 
   3148 // isLegalToPruneDependencies
   3149 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
   3150   MachineInstr *I = SUI->getInstr();
   3151   assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
   3152 
   3153   const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
   3154 
   3155   if (Dependence) {
   3156 
   3157     // Check if the instruction was promoted to a dot-new. If so, demote it
   3158     // back into a dot-old.
   3159     if (PromotedToDotNew) {
   3160       DemoteToDotOld(I);
   3161     }
   3162 
   3163     // Check if the instruction (must be a store) was glued with an Allocframe
   3164     // instruction. If so, restore its offset to its original value, i.e. use
   3165     // curent SP instead of caller's SP.
   3166     if (GlueAllocframeStore) {
   3167       I->getOperand(1).setImm(I->getOperand(1).getImm() +
   3168                                              FrameSize + HEXAGON_LRFP_SIZE);
   3169     }
   3170 
   3171     return false;
   3172   }
   3173   return true;
   3174 }
   3175 
   3176 MachineBasicBlock::iterator
   3177 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
   3178 
   3179     MachineBasicBlock::iterator MII = MI;
   3180     MachineBasicBlock *MBB = MI->getParent();
   3181 
   3182     const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   3183 
   3184     if (GlueToNewValueJump) {
   3185 
   3186       ++MII;
   3187       MachineInstr *nvjMI = MII;
   3188       assert(ResourceTracker->canReserveResources(MI));
   3189       ResourceTracker->reserveResources(MI);
   3190       if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
   3191           !tryAllocateResourcesForConstExt(MI)) {
   3192         endPacket(MBB, MI);
   3193         ResourceTracker->reserveResources(MI);
   3194         assert(canReserveResourcesForConstExt(MI) &&
   3195                "Ensure that there is a slot");
   3196         reserveResourcesForConstExt(MI);
   3197         // Reserve resources for new value jump constant extender.
   3198         assert(canReserveResourcesForConstExt(MI) &&
   3199                "Ensure that there is a slot");
   3200         reserveResourcesForConstExt(nvjMI);
   3201         assert(ResourceTracker->canReserveResources(nvjMI) &&
   3202                "Ensure that there is a slot");
   3203 
   3204       } else if (   // Extended instruction takes two slots in the packet.
   3205         // Try reserve and allocate 4-byte in the current packet first.
   3206         (QII->isExtended(nvjMI)
   3207             && (!tryAllocateResourcesForConstExt(nvjMI)
   3208                 || !ResourceTracker->canReserveResources(nvjMI)))
   3209         || // For non-extended instruction, no need to allocate extra 4 bytes.
   3210         (!QII->isExtended(nvjMI) &&
   3211               !ResourceTracker->canReserveResources(nvjMI)))
   3212       {
   3213         endPacket(MBB, MI);
   3214         // A new and empty packet starts.
   3215         // We are sure that the resources requirements can be satisfied.
   3216         // Therefore, do not need to call "canReserveResources" anymore.
   3217         ResourceTracker->reserveResources(MI);
   3218         if (QII->isExtended(nvjMI))
   3219           reserveResourcesForConstExt(nvjMI);
   3220       }
   3221       // Here, we are sure that "reserveResources" would succeed.
   3222       ResourceTracker->reserveResources(nvjMI);
   3223       CurrentPacketMIs.push_back(MI);
   3224       CurrentPacketMIs.push_back(nvjMI);
   3225     } else {
   3226       if (   (QII->isExtended(MI) || QII->isConstExtended(MI))
   3227           && (   !tryAllocateResourcesForConstExt(MI)
   3228               || !ResourceTracker->canReserveResources(MI)))
   3229       {
   3230         endPacket(MBB, MI);
   3231         // Check if the instruction was promoted to a dot-new. If so, demote it
   3232         // back into a dot-old
   3233         if (PromotedToDotNew) {
   3234           DemoteToDotOld(MI);
   3235         }
   3236         reserveResourcesForConstExt(MI);
   3237       }
   3238       // In case that "MI" is not an extended insn,
   3239       // the resource availability has already been checked.
   3240       ResourceTracker->reserveResources(MI);
   3241       CurrentPacketMIs.push_back(MI);
   3242     }
   3243     return MII;
   3244 }
   3245 
   3246 //===----------------------------------------------------------------------===//
   3247 //                         Public Constructor Functions
   3248 //===----------------------------------------------------------------------===//
   3249 
   3250 FunctionPass *llvm::createHexagonPacketizer() {
   3251   return new HexagonPacketizer();
   3252 }
   3253 
   3254