| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 177 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
183 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
193 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
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| MipsInstrInfo.cpp | 119 MIB.addMBB(TBB);
141 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
148 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
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| Mips16ISelLowering.cpp | 453 .addMBB(sinkMBB);
470 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
471 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
517 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
534 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
535 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
582 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
599 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
600 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
618 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target)
[all...] |
| MipsLongBranch.cpp | 236 MIB.addMBB(MBBOpnd);
289 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
344 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
374 .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 274 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
277 .addReg(Cond[0].getReg()).addMBB(TBB);
283 .addReg(Cond[0].getReg()).addMBB(TBB);
284 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
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| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 206 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
208 .addMBB(TargetBB);
240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
209 BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB);
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| MBlazeISelLowering.cpp | 308 .addMBB(finish);
313 .addReg(IVAL).addMBB(MBB)
314 .addReg(NDST).addMBB(loop);
319 .addReg(IAMT).addMBB(MBB)
320 .addReg(NAMT).addMBB(loop);
337 .addMBB(loop);
341 .addReg(IVAL).addMBB(MBB)
342 .addReg(NDST).addMBB(loop);
399 .addMBB(dneBB);
405 // .addReg(MI->getOperand(1).getReg()).addMBB(flsBB
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 287 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
292 .addMBB(TBB);
301 .addMBB(TBB);
302 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 272 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
283 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
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| MSP430BranchSelector.cpp | 161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
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| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFixupHwLoops.cpp | 180 .addMBB(MII->getOperand(0).getMBB());
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| HexagonNewValueJump.cpp | 612 .addMBB(jmpTarget);
619 .addMBB(jmpTarget);
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| HexagonHardwareLoops.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCBranchSelector.cpp | 176 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
|
| PPCInstrInfo.cpp | 385 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
389 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
392 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
400 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
403 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
404 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
|
| /external/llvm/lib/CodeGen/ |
| MachineSSAUpdater.cpp | 191 InsertedPHI.addReg(PredValues[i].second).addMBB(PredValues[i].first);
318 MachineInstrBuilder(*Pred->getParent(), PHI).addReg(Val).addMBB(Pred);
|
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64BranchFixupPass.cpp | 376 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::Bimm)).addMBB(NewBB);
589 .addMBB(MI->getOperand(CondBrMBBOperand).getMBB());
|
| AArch64InstrInfo.cpp | 309 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB);
315 MIB.addMBB(TBB);
322 MIB.addMBB(TBB);
324 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(FBB);
|
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.cpp | 318 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
327 .addMBB(TBB)
337 .addMBB(TBB)
339 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
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| AMDGPUIndirectAddressing.cpp | 199 Phi.addMBB(RegBlock);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 98 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
|
