1 //===-- MBlazeISelLowering.cpp - MBlaze DAG Lowering Implementation -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that MBlaze uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "mblaze-lower" 16 #include "MBlazeISelLowering.h" 17 #include "MBlazeMachineFunction.h" 18 #include "MBlazeSubtarget.h" 19 #include "MBlazeTargetMachine.h" 20 #include "MBlazeTargetObjectFile.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/MachineFrameInfo.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/CodeGen/SelectionDAGISel.h" 27 #include "llvm/CodeGen/ValueTypes.h" 28 #include "llvm/IR/CallingConv.h" 29 #include "llvm/IR/DerivedTypes.h" 30 #include "llvm/IR/Function.h" 31 #include "llvm/IR/GlobalVariable.h" 32 #include "llvm/IR/Intrinsics.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/ErrorHandling.h" 35 #include "llvm/Support/raw_ostream.h" 36 using namespace llvm; 37 38 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 39 CCValAssign::LocInfo &LocInfo, 40 ISD::ArgFlagsTy &ArgFlags, 41 CCState &State); 42 43 const char *MBlazeTargetLowering::getTargetNodeName(unsigned Opcode) const { 44 switch (Opcode) { 45 case MBlazeISD::JmpLink : return "MBlazeISD::JmpLink"; 46 case MBlazeISD::GPRel : return "MBlazeISD::GPRel"; 47 case MBlazeISD::Wrap : return "MBlazeISD::Wrap"; 48 case MBlazeISD::ICmp : return "MBlazeISD::ICmp"; 49 case MBlazeISD::Ret : return "MBlazeISD::Ret"; 50 case MBlazeISD::Select_CC : return "MBlazeISD::Select_CC"; 51 default : return NULL; 52 } 53 } 54 55 MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM) 56 : TargetLowering(TM, new MBlazeTargetObjectFile()) { 57 Subtarget = &TM.getSubtarget<MBlazeSubtarget>(); 58 59 // MBlaze does not have i1 type, so use i32 for 60 // setcc operations results (slt, sgt, ...). 61 setBooleanContents(ZeroOrOneBooleanContent); 62 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 63 64 // Set up the register classes 65 addRegisterClass(MVT::i32, &MBlaze::GPRRegClass); 66 if (Subtarget->hasFPU()) { 67 addRegisterClass(MVT::f32, &MBlaze::GPRRegClass); 68 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 69 } 70 71 // Floating point operations which are not supported 72 setOperationAction(ISD::FREM, MVT::f32, Expand); 73 setOperationAction(ISD::FMA, MVT::f32, Expand); 74 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand); 75 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand); 76 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 77 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 78 setOperationAction(ISD::FP_ROUND, MVT::f32, Expand); 79 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand); 80 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 81 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 82 setOperationAction(ISD::FSIN, MVT::f32, Expand); 83 setOperationAction(ISD::FCOS, MVT::f32, Expand); 84 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 85 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 86 setOperationAction(ISD::FPOW, MVT::f32, Expand); 87 setOperationAction(ISD::FLOG, MVT::f32, Expand); 88 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 89 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 90 setOperationAction(ISD::FEXP, MVT::f32, Expand); 91 92 // Load extented operations for i1 types must be promoted 93 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 94 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 95 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 96 97 // Sign extended loads must be expanded 98 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 99 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); 100 101 // MBlaze has no REM or DIVREM operations. 102 setOperationAction(ISD::UREM, MVT::i32, Expand); 103 setOperationAction(ISD::SREM, MVT::i32, Expand); 104 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 105 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 106 107 // If the processor doesn't support multiply then expand it 108 if (!Subtarget->hasMul()) { 109 setOperationAction(ISD::MUL, MVT::i32, Expand); 110 } 111 112 // If the processor doesn't support 64-bit multiply then expand 113 if (!Subtarget->hasMul() || !Subtarget->hasMul64()) { 114 setOperationAction(ISD::MULHS, MVT::i32, Expand); 115 setOperationAction(ISD::MULHS, MVT::i64, Expand); 116 setOperationAction(ISD::MULHU, MVT::i32, Expand); 117 setOperationAction(ISD::MULHU, MVT::i64, Expand); 118 } 119 120 // If the processor doesn't support division then expand 121 if (!Subtarget->hasDiv()) { 122 setOperationAction(ISD::UDIV, MVT::i32, Expand); 123 setOperationAction(ISD::SDIV, MVT::i32, Expand); 124 } 125 126 // Expand unsupported conversions 127 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 128 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 129 130 // Expand SELECT_CC 131 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 132 133 // MBlaze doesn't have MUL_LOHI 134 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 135 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 136 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 137 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 138 139 // Used by legalize types to correctly generate the setcc result. 140 // Without this, every float setcc comes with a AND/OR with the result, 141 // we don't want this, since the fpcmp result goes to a flag register, 142 // which is used implicitly by brcond and select operations. 143 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 144 AddPromotedToType(ISD::SELECT, MVT::i1, MVT::i32); 145 AddPromotedToType(ISD::SELECT_CC, MVT::i1, MVT::i32); 146 147 // MBlaze Custom Operations 148 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 149 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 150 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 151 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 152 153 // Variable Argument support 154 setOperationAction(ISD::VASTART, MVT::Other, Custom); 155 setOperationAction(ISD::VAEND, MVT::Other, Expand); 156 setOperationAction(ISD::VAARG, MVT::Other, Expand); 157 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 158 159 160 // Operations not directly supported by MBlaze. 161 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 162 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 163 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 164 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 166 setOperationAction(ISD::ROTL, MVT::i32, Expand); 167 setOperationAction(ISD::ROTR, MVT::i32, Expand); 168 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 169 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 170 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 171 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 172 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 173 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 174 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 175 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 176 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 177 178 // We don't have line number support yet. 179 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 180 181 // Use the default for now 182 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 183 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 184 185 // MBlaze doesn't have extending float->double load/store 186 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 187 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 188 189 setMinFunctionAlignment(2); 190 191 setStackPointerRegisterToSaveRestore(MBlaze::R1); 192 computeRegisterProperties(); 193 } 194 195 EVT MBlazeTargetLowering::getSetCCResultType(EVT VT) const { 196 return MVT::i32; 197 } 198 199 SDValue MBlazeTargetLowering::LowerOperation(SDValue Op, 200 SelectionDAG &DAG) const { 201 switch (Op.getOpcode()) 202 { 203 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 204 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 205 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 206 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 207 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 208 case ISD::VASTART: return LowerVASTART(Op, DAG); 209 } 210 return SDValue(); 211 } 212 213 //===----------------------------------------------------------------------===// 214 // Lower helper functions 215 //===----------------------------------------------------------------------===// 216 MachineBasicBlock* 217 MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 218 MachineBasicBlock *MBB) 219 const { 220 switch (MI->getOpcode()) { 221 default: llvm_unreachable("Unexpected instr type to insert"); 222 223 case MBlaze::ShiftRL: 224 case MBlaze::ShiftRA: 225 case MBlaze::ShiftL: 226 return EmitCustomShift(MI, MBB); 227 228 case MBlaze::Select_FCC: 229 case MBlaze::Select_CC: 230 return EmitCustomSelect(MI, MBB); 231 232 case MBlaze::CAS32: 233 case MBlaze::SWP32: 234 case MBlaze::LAA32: 235 case MBlaze::LAS32: 236 case MBlaze::LAD32: 237 case MBlaze::LAO32: 238 case MBlaze::LAX32: 239 case MBlaze::LAN32: 240 return EmitCustomAtomic(MI, MBB); 241 242 case MBlaze::MEMBARRIER: 243 // The Microblaze does not need memory barriers. Just delete the pseudo 244 // instruction and finish. 245 MI->eraseFromParent(); 246 return MBB; 247 } 248 } 249 250 MachineBasicBlock* 251 MBlazeTargetLowering::EmitCustomShift(MachineInstr *MI, 252 MachineBasicBlock *MBB) const { 253 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 254 DebugLoc dl = MI->getDebugLoc(); 255 256 // To "insert" a shift left instruction, we actually have to insert a 257 // simple loop. The incoming instruction knows the destination vreg to 258 // set, the source vreg to operate over and the shift amount. 259 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 260 MachineFunction::iterator It = MBB; 261 ++It; 262 263 // start: 264 // andi samt, samt, 31 265 // beqid samt, finish 266 // add dst, src, r0 267 // loop: 268 // addik samt, samt, -1 269 // sra dst, dst 270 // bneid samt, loop 271 // nop 272 // finish: 273 MachineFunction *F = MBB->getParent(); 274 MachineRegisterInfo &R = F->getRegInfo(); 275 MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB); 276 MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB); 277 F->insert(It, loop); 278 F->insert(It, finish); 279 280 // Update machine-CFG edges by transferring adding all successors and 281 // remaining instructions from the current block to the new block which 282 // will contain the Phi node for the select. 283 finish->splice(finish->begin(), MBB, 284 llvm::next(MachineBasicBlock::iterator(MI)), 285 MBB->end()); 286 finish->transferSuccessorsAndUpdatePHIs(MBB); 287 288 // Add the true and fallthrough blocks as its successors. 289 MBB->addSuccessor(loop); 290 MBB->addSuccessor(finish); 291 292 // Next, add the finish block as a successor of the loop block 293 loop->addSuccessor(finish); 294 loop->addSuccessor(loop); 295 296 unsigned IAMT = R.createVirtualRegister(&MBlaze::GPRRegClass); 297 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT) 298 .addReg(MI->getOperand(2).getReg()) 299 .addImm(31); 300 301 unsigned IVAL = R.createVirtualRegister(&MBlaze::GPRRegClass); 302 BuildMI(MBB, dl, TII->get(MBlaze::ADDIK), IVAL) 303 .addReg(MI->getOperand(1).getReg()) 304 .addImm(0); 305 306 BuildMI(MBB, dl, TII->get(MBlaze::BEQID)) 307 .addReg(IAMT) 308 .addMBB(finish); 309 310 unsigned DST = R.createVirtualRegister(&MBlaze::GPRRegClass); 311 unsigned NDST = R.createVirtualRegister(&MBlaze::GPRRegClass); 312 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST) 313 .addReg(IVAL).addMBB(MBB) 314 .addReg(NDST).addMBB(loop); 315 316 unsigned SAMT = R.createVirtualRegister(&MBlaze::GPRRegClass); 317 unsigned NAMT = R.createVirtualRegister(&MBlaze::GPRRegClass); 318 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT) 319 .addReg(IAMT).addMBB(MBB) 320 .addReg(NAMT).addMBB(loop); 321 322 if (MI->getOpcode() == MBlaze::ShiftL) 323 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST); 324 else if (MI->getOpcode() == MBlaze::ShiftRA) 325 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST); 326 else if (MI->getOpcode() == MBlaze::ShiftRL) 327 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST); 328 else 329 llvm_unreachable("Cannot lower unknown shift instruction"); 330 331 BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT) 332 .addReg(SAMT) 333 .addImm(-1); 334 335 BuildMI(loop, dl, TII->get(MBlaze::BNEID)) 336 .addReg(NAMT) 337 .addMBB(loop); 338 339 BuildMI(*finish, finish->begin(), dl, 340 TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) 341 .addReg(IVAL).addMBB(MBB) 342 .addReg(NDST).addMBB(loop); 343 344 // The pseudo instruction is no longer needed so remove it 345 MI->eraseFromParent(); 346 return finish; 347 } 348 349 MachineBasicBlock* 350 MBlazeTargetLowering::EmitCustomSelect(MachineInstr *MI, 351 MachineBasicBlock *MBB) const { 352 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 353 DebugLoc dl = MI->getDebugLoc(); 354 355 // To "insert" a SELECT_CC instruction, we actually have to insert the 356 // diamond control-flow pattern. The incoming instruction knows the 357 // destination vreg to set, the condition code register to branch on, the 358 // true/false values to select between, and a branch opcode to use. 359 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 360 MachineFunction::iterator It = MBB; 361 ++It; 362 363 // thisMBB: 364 // ... 365 // TrueVal = ... 366 // setcc r1, r2, r3 367 // bNE r1, r0, copy1MBB 368 // fallthrough --> copy0MBB 369 MachineFunction *F = MBB->getParent(); 370 MachineBasicBlock *flsBB = F->CreateMachineBasicBlock(LLVM_BB); 371 MachineBasicBlock *dneBB = F->CreateMachineBasicBlock(LLVM_BB); 372 373 unsigned Opc; 374 switch (MI->getOperand(4).getImm()) { 375 default: llvm_unreachable("Unknown branch condition"); 376 case MBlazeCC::EQ: Opc = MBlaze::BEQID; break; 377 case MBlazeCC::NE: Opc = MBlaze::BNEID; break; 378 case MBlazeCC::GT: Opc = MBlaze::BGTID; break; 379 case MBlazeCC::LT: Opc = MBlaze::BLTID; break; 380 case MBlazeCC::GE: Opc = MBlaze::BGEID; break; 381 case MBlazeCC::LE: Opc = MBlaze::BLEID; break; 382 } 383 384 F->insert(It, flsBB); 385 F->insert(It, dneBB); 386 387 // Transfer the remainder of MBB and its successor edges to dneBB. 388 dneBB->splice(dneBB->begin(), MBB, 389 llvm::next(MachineBasicBlock::iterator(MI)), 390 MBB->end()); 391 dneBB->transferSuccessorsAndUpdatePHIs(MBB); 392 393 MBB->addSuccessor(flsBB); 394 MBB->addSuccessor(dneBB); 395 flsBB->addSuccessor(dneBB); 396 397 BuildMI(MBB, dl, TII->get(Opc)) 398 .addReg(MI->getOperand(3).getReg()) 399 .addMBB(dneBB); 400 401 // sinkMBB: 402 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 403 // ... 404 //BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) 405 // .addReg(MI->getOperand(1).getReg()).addMBB(flsBB) 406 // .addReg(MI->getOperand(2).getReg()).addMBB(BB); 407 408 BuildMI(*dneBB, dneBB->begin(), dl, 409 TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) 410 .addReg(MI->getOperand(2).getReg()).addMBB(flsBB) 411 .addReg(MI->getOperand(1).getReg()).addMBB(MBB); 412 413 MI->eraseFromParent(); // The pseudo instruction is gone now. 414 return dneBB; 415 } 416 417 MachineBasicBlock* 418 MBlazeTargetLowering::EmitCustomAtomic(MachineInstr *MI, 419 MachineBasicBlock *MBB) const { 420 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 421 DebugLoc dl = MI->getDebugLoc(); 422 423 // All atomic instructions on the Microblaze are implemented using the 424 // load-linked / store-conditional style atomic instruction sequences. 425 // Thus, all operations will look something like the following: 426 // 427 // start: 428 // lwx RV, RP, 0 429 // <do stuff> 430 // swx RV, RP, 0 431 // addic RC, R0, 0 432 // bneid RC, start 433 // 434 // exit: 435 // 436 // To "insert" a shift left instruction, we actually have to insert a 437 // simple loop. The incoming instruction knows the destination vreg to 438 // set, the source vreg to operate over and the shift amount. 439 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 440 MachineFunction::iterator It = MBB; 441 ++It; 442 443 // start: 444 // andi samt, samt, 31 445 // beqid samt, finish 446 // add dst, src, r0 447 // loop: 448 // addik samt, samt, -1 449 // sra dst, dst 450 // bneid samt, loop 451 // nop 452 // finish: 453 MachineFunction *F = MBB->getParent(); 454 MachineRegisterInfo &R = F->getRegInfo(); 455 456 // Create the start and exit basic blocks for the atomic operation 457 MachineBasicBlock *start = F->CreateMachineBasicBlock(LLVM_BB); 458 MachineBasicBlock *exit = F->CreateMachineBasicBlock(LLVM_BB); 459 F->insert(It, start); 460 F->insert(It, exit); 461 462 // Update machine-CFG edges by transferring adding all successors and 463 // remaining instructions from the current block to the new block which 464 // will contain the Phi node for the select. 465 exit->splice(exit->begin(), MBB, llvm::next(MachineBasicBlock::iterator(MI)), 466 MBB->end()); 467 exit->transferSuccessorsAndUpdatePHIs(MBB); 468 469 // Add the fallthrough block as its successors. 470 MBB->addSuccessor(start); 471 472 BuildMI(start, dl, TII->get(MBlaze::LWX), MI->getOperand(0).getReg()) 473 .addReg(MI->getOperand(1).getReg()) 474 .addReg(MBlaze::R0); 475 476 MachineBasicBlock *final = start; 477 unsigned finalReg = 0; 478 479 switch (MI->getOpcode()) { 480 default: llvm_unreachable("Cannot lower unknown atomic instruction!"); 481 482 case MBlaze::SWP32: 483 finalReg = MI->getOperand(2).getReg(); 484 start->addSuccessor(exit); 485 start->addSuccessor(start); 486 break; 487 488 case MBlaze::LAN32: 489 case MBlaze::LAX32: 490 case MBlaze::LAO32: 491 case MBlaze::LAD32: 492 case MBlaze::LAS32: 493 case MBlaze::LAA32: { 494 unsigned opcode = 0; 495 switch (MI->getOpcode()) { 496 default: llvm_unreachable("Cannot lower unknown atomic load!"); 497 case MBlaze::LAA32: opcode = MBlaze::ADDIK; break; 498 case MBlaze::LAS32: opcode = MBlaze::RSUBIK; break; 499 case MBlaze::LAD32: opcode = MBlaze::AND; break; 500 case MBlaze::LAO32: opcode = MBlaze::OR; break; 501 case MBlaze::LAX32: opcode = MBlaze::XOR; break; 502 case MBlaze::LAN32: opcode = MBlaze::AND; break; 503 } 504 505 finalReg = R.createVirtualRegister(&MBlaze::GPRRegClass); 506 start->addSuccessor(exit); 507 start->addSuccessor(start); 508 509 BuildMI(start, dl, TII->get(opcode), finalReg) 510 .addReg(MI->getOperand(0).getReg()) 511 .addReg(MI->getOperand(2).getReg()); 512 513 if (MI->getOpcode() == MBlaze::LAN32) { 514 unsigned tmp = finalReg; 515 finalReg = R.createVirtualRegister(&MBlaze::GPRRegClass); 516 BuildMI(start, dl, TII->get(MBlaze::XORI), finalReg) 517 .addReg(tmp) 518 .addImm(-1); 519 } 520 break; 521 } 522 523 case MBlaze::CAS32: { 524 finalReg = MI->getOperand(3).getReg(); 525 final = F->CreateMachineBasicBlock(LLVM_BB); 526 527 F->insert(It, final); 528 start->addSuccessor(exit); 529 start->addSuccessor(final); 530 final->addSuccessor(exit); 531 final->addSuccessor(start); 532 533 unsigned CMP = R.createVirtualRegister(&MBlaze::GPRRegClass); 534 BuildMI(start, dl, TII->get(MBlaze::CMP), CMP) 535 .addReg(MI->getOperand(0).getReg()) 536 .addReg(MI->getOperand(2).getReg()); 537 538 BuildMI(start, dl, TII->get(MBlaze::BNEID)) 539 .addReg(CMP) 540 .addMBB(exit); 541 542 final->moveAfter(start); 543 exit->moveAfter(final); 544 break; 545 } 546 } 547 548 unsigned CHK = R.createVirtualRegister(&MBlaze::GPRRegClass); 549 BuildMI(final, dl, TII->get(MBlaze::SWX)) 550 .addReg(finalReg) 551 .addReg(MI->getOperand(1).getReg()) 552 .addReg(MBlaze::R0); 553 554 BuildMI(final, dl, TII->get(MBlaze::ADDIC), CHK) 555 .addReg(MBlaze::R0) 556 .addImm(0); 557 558 BuildMI(final, dl, TII->get(MBlaze::BNEID)) 559 .addReg(CHK) 560 .addMBB(start); 561 562 // The pseudo instruction is no longer needed so remove it 563 MI->eraseFromParent(); 564 return exit; 565 } 566 567 //===----------------------------------------------------------------------===// 568 // Misc Lower Operation implementation 569 //===----------------------------------------------------------------------===// 570 // 571 572 SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op, 573 SelectionDAG &DAG) const { 574 SDValue LHS = Op.getOperand(0); 575 SDValue RHS = Op.getOperand(1); 576 SDValue TrueVal = Op.getOperand(2); 577 SDValue FalseVal = Op.getOperand(3); 578 DebugLoc dl = Op.getDebugLoc(); 579 unsigned Opc; 580 581 SDValue CompareFlag; 582 if (LHS.getValueType() == MVT::i32) { 583 Opc = MBlazeISD::Select_CC; 584 CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT::i32, LHS, RHS) 585 .getValue(1); 586 } else { 587 llvm_unreachable("Cannot lower select_cc with unknown type"); 588 } 589 590 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 591 CompareFlag); 592 } 593 594 SDValue MBlazeTargetLowering:: 595 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 596 // FIXME there isn't actually debug info here 597 DebugLoc dl = Op.getDebugLoc(); 598 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 599 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32); 600 601 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, GA); 602 } 603 604 SDValue MBlazeTargetLowering:: 605 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 606 llvm_unreachable("TLS not implemented for MicroBlaze."); 607 } 608 609 SDValue MBlazeTargetLowering:: 610 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 611 SDValue ResNode; 612 SDValue HiPart; 613 // FIXME there isn't actually debug info here 614 DebugLoc dl = Op.getDebugLoc(); 615 616 EVT PtrVT = Op.getValueType(); 617 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 618 619 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 0); 620 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, JTI); 621 } 622 623 SDValue MBlazeTargetLowering:: 624 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 625 SDValue ResNode; 626 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 627 const Constant *C = N->getConstVal(); 628 DebugLoc dl = Op.getDebugLoc(); 629 630 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 631 N->getOffset(), 0); 632 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP); 633 } 634 635 SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op, 636 SelectionDAG &DAG) const { 637 MachineFunction &MF = DAG.getMachineFunction(); 638 MBlazeFunctionInfo *FuncInfo = MF.getInfo<MBlazeFunctionInfo>(); 639 640 DebugLoc dl = Op.getDebugLoc(); 641 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 642 getPointerTy()); 643 644 // vastart just stores the address of the VarArgsFrameIndex slot into the 645 // memory location argument. 646 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 647 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 648 MachinePointerInfo(SV), 649 false, false, 0); 650 } 651 652 //===----------------------------------------------------------------------===// 653 // Calling Convention Implementation 654 //===----------------------------------------------------------------------===// 655 656 #include "MBlazeGenCallingConv.inc" 657 658 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 659 CCValAssign::LocInfo &LocInfo, 660 ISD::ArgFlagsTy &ArgFlags, 661 CCState &State) { 662 static const uint16_t ArgRegs[] = { 663 MBlaze::R5, MBlaze::R6, MBlaze::R7, 664 MBlaze::R8, MBlaze::R9, MBlaze::R10 665 }; 666 667 const unsigned NumArgRegs = array_lengthof(ArgRegs); 668 unsigned Reg = State.AllocateReg(ArgRegs, NumArgRegs); 669 if (!Reg) return false; 670 671 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 672 State.AllocateStack(SizeInBytes, SizeInBytes); 673 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 674 675 return true; 676 } 677 678 //===----------------------------------------------------------------------===// 679 // Call Calling Convention Implementation 680 //===----------------------------------------------------------------------===// 681 682 /// LowerCall - functions arguments are copied from virtual regs to 683 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 684 /// TODO: isVarArg, isTailCall. 685 SDValue MBlazeTargetLowering:: 686 LowerCall(TargetLowering::CallLoweringInfo &CLI, 687 SmallVectorImpl<SDValue> &InVals) const { 688 SelectionDAG &DAG = CLI.DAG; 689 DebugLoc &dl = CLI.DL; 690 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 691 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 692 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 693 SDValue Chain = CLI.Chain; 694 SDValue Callee = CLI.Callee; 695 bool &isTailCall = CLI.IsTailCall; 696 CallingConv::ID CallConv = CLI.CallConv; 697 bool isVarArg = CLI.IsVarArg; 698 699 // MBlaze does not yet support tail call optimization 700 isTailCall = false; 701 702 // The MBlaze requires stack slots for arguments passed to var arg 703 // functions even if they are passed in registers. 704 bool needsRegArgSlots = isVarArg; 705 706 MachineFunction &MF = DAG.getMachineFunction(); 707 MachineFrameInfo *MFI = MF.getFrameInfo(); 708 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering(); 709 710 // Analyze operands of the call, assigning locations to each operand. 711 SmallVector<CCValAssign, 16> ArgLocs; 712 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 713 getTargetMachine(), ArgLocs, *DAG.getContext()); 714 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze); 715 716 // Get a count of how many bytes are to be pushed on the stack. 717 unsigned NumBytes = CCInfo.getNextStackOffset(); 718 719 // Variable argument function calls require a minimum of 24-bytes of stack 720 if (isVarArg && NumBytes < 24) NumBytes = 24; 721 722 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 723 724 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 725 SmallVector<SDValue, 8> MemOpChains; 726 727 // Walk the register/memloc assignments, inserting copies/loads. 728 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 729 CCValAssign &VA = ArgLocs[i]; 730 MVT RegVT = VA.getLocVT(); 731 SDValue Arg = OutVals[i]; 732 733 // Promote the value if needed. 734 switch (VA.getLocInfo()) { 735 default: llvm_unreachable("Unknown loc info!"); 736 case CCValAssign::Full: break; 737 case CCValAssign::SExt: 738 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 739 break; 740 case CCValAssign::ZExt: 741 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 742 break; 743 case CCValAssign::AExt: 744 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 745 break; 746 } 747 748 // Arguments that can be passed on register must be kept at 749 // RegsToPass vector 750 if (VA.isRegLoc()) { 751 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 752 } else { 753 // Register can't get to this point... 754 assert(VA.isMemLoc()); 755 756 // Since we are alread passing values on the stack we don't 757 // need to worry about creating additional slots for the 758 // values passed via registers. 759 needsRegArgSlots = false; 760 761 // Create the frame index object for this incoming parameter 762 unsigned ArgSize = VA.getValVT().getSizeInBits()/8; 763 unsigned StackLoc = VA.getLocMemOffset() + 4; 764 int FI = MFI->CreateFixedObject(ArgSize, StackLoc, true); 765 766 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy()); 767 768 // emit ISD::STORE whichs stores the 769 // parameter value to a stack Location 770 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 771 MachinePointerInfo(), 772 false, false, 0)); 773 } 774 } 775 776 // If we need to reserve stack space for the arguments passed via registers 777 // then create a fixed stack object at the beginning of the stack. 778 if (needsRegArgSlots && TFI.hasReservedCallFrame(MF)) 779 MFI->CreateFixedObject(28,0,true); 780 781 // Transform all store nodes into one single node because all store 782 // nodes are independent of each other. 783 if (!MemOpChains.empty()) 784 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 785 &MemOpChains[0], MemOpChains.size()); 786 787 // Build a sequence of copy-to-reg nodes chained together with token 788 // chain and flag operands which copy the outgoing args into registers. 789 // The InFlag in necessary since all emitted instructions must be 790 // stuck together. 791 SDValue InFlag; 792 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 793 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 794 RegsToPass[i].second, InFlag); 795 InFlag = Chain.getValue(1); 796 } 797 798 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 799 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 800 // node so that legalize doesn't hack it. 801 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 802 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 803 getPointerTy(), 0, 0); 804 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 805 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 806 getPointerTy(), 0); 807 808 // MBlazeJmpLink = #chain, #target_address, #opt_in_flags... 809 // = Chain, Callee, Reg#1, Reg#2, ... 810 // 811 // Returns a chain & a flag for retval copy to use. 812 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 813 SmallVector<SDValue, 8> Ops; 814 Ops.push_back(Chain); 815 Ops.push_back(Callee); 816 817 // Add argument registers to the end of the list so that they are 818 // known live into the call. 819 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 820 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 821 RegsToPass[i].second.getValueType())); 822 } 823 824 if (InFlag.getNode()) 825 Ops.push_back(InFlag); 826 827 Chain = DAG.getNode(MBlazeISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 828 InFlag = Chain.getValue(1); 829 830 // Create the CALLSEQ_END node. 831 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 832 DAG.getIntPtrConstant(0, true), InFlag); 833 if (!Ins.empty()) 834 InFlag = Chain.getValue(1); 835 836 // Handle result values, copying them out of physregs into vregs that we 837 // return. 838 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 839 Ins, dl, DAG, InVals); 840 } 841 842 /// LowerCallResult - Lower the result values of a call into the 843 /// appropriate copies out of appropriate physical registers. 844 SDValue MBlazeTargetLowering:: 845 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, 846 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, 847 DebugLoc dl, SelectionDAG &DAG, 848 SmallVectorImpl<SDValue> &InVals) const { 849 // Assign locations to each value returned by this call. 850 SmallVector<CCValAssign, 16> RVLocs; 851 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 852 getTargetMachine(), RVLocs, *DAG.getContext()); 853 854 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze); 855 856 // Copy all of the result registers out of their specified physreg. 857 for (unsigned i = 0; i != RVLocs.size(); ++i) { 858 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 859 RVLocs[i].getValVT(), InFlag).getValue(1); 860 InFlag = Chain.getValue(2); 861 InVals.push_back(Chain.getValue(0)); 862 } 863 864 return Chain; 865 } 866 867 //===----------------------------------------------------------------------===// 868 // Formal Arguments Calling Convention Implementation 869 //===----------------------------------------------------------------------===// 870 871 /// LowerFormalArguments - transform physical registers into 872 /// virtual registers and generate load operations for 873 /// arguments places on the stack. 874 SDValue MBlazeTargetLowering:: 875 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 876 const SmallVectorImpl<ISD::InputArg> &Ins, 877 DebugLoc dl, SelectionDAG &DAG, 878 SmallVectorImpl<SDValue> &InVals) const { 879 MachineFunction &MF = DAG.getMachineFunction(); 880 MachineFrameInfo *MFI = MF.getFrameInfo(); 881 MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>(); 882 883 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); 884 MBlazeFI->setVarArgsFrameIndex(0); 885 886 // Used with vargs to acumulate store chains. 887 std::vector<SDValue> OutChains; 888 889 // Keep track of the last register used for arguments 890 unsigned ArgRegEnd = 0; 891 892 // Assign locations to all of the incoming arguments. 893 SmallVector<CCValAssign, 16> ArgLocs; 894 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 895 getTargetMachine(), ArgLocs, *DAG.getContext()); 896 897 CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze); 898 SDValue StackPtr; 899 900 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 901 CCValAssign &VA = ArgLocs[i]; 902 903 // Arguments stored on registers 904 if (VA.isRegLoc()) { 905 MVT RegVT = VA.getLocVT(); 906 ArgRegEnd = VA.getLocReg(); 907 const TargetRegisterClass *RC; 908 909 if (RegVT == MVT::i32) 910 RC = &MBlaze::GPRRegClass; 911 else if (RegVT == MVT::f32) 912 RC = &MBlaze::GPRRegClass; 913 else 914 llvm_unreachable("RegVT not supported by LowerFormalArguments"); 915 916 // Transform the arguments stored on 917 // physical registers into virtual ones 918 unsigned Reg = MF.addLiveIn(ArgRegEnd, RC); 919 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 920 921 // If this is an 8 or 16-bit value, it has been passed promoted 922 // to 32 bits. Insert an assert[sz]ext to capture this, then 923 // truncate to the right size. If if is a floating point value 924 // then convert to the correct type. 925 if (VA.getLocInfo() != CCValAssign::Full) { 926 unsigned Opcode = 0; 927 if (VA.getLocInfo() == CCValAssign::SExt) 928 Opcode = ISD::AssertSext; 929 else if (VA.getLocInfo() == CCValAssign::ZExt) 930 Opcode = ISD::AssertZext; 931 if (Opcode) 932 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 933 DAG.getValueType(VA.getValVT())); 934 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 935 } 936 937 InVals.push_back(ArgValue); 938 } else { // VA.isRegLoc() 939 // sanity check 940 assert(VA.isMemLoc()); 941 942 // The last argument is not a register 943 ArgRegEnd = 0; 944 945 // The stack pointer offset is relative to the caller stack frame. 946 // Since the real stack size is unknown here, a negative SPOffset 947 // is used so there's a way to adjust these offsets when the stack 948 // size get known (on EliminateFrameIndex). A dummy SPOffset is 949 // used instead of a direct negative address (which is recorded to 950 // be used on emitPrologue) to avoid mis-calc of the first stack 951 // offset on PEI::calculateFrameObjectOffsets. 952 // Arguments are always 32-bit. 953 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; 954 unsigned StackLoc = VA.getLocMemOffset() + 4; 955 int FI = MFI->CreateFixedObject(ArgSize, 0, true); 956 MBlazeFI->recordLoadArgsFI(FI, -StackLoc); 957 MBlazeFI->recordLiveIn(FI); 958 959 // Create load nodes to retrieve arguments from the stack 960 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 961 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 962 MachinePointerInfo::getFixedStack(FI), 963 false, false, false, 0)); 964 } 965 } 966 967 // To meet ABI, when VARARGS are passed on registers, the registers 968 // must have their values written to the caller stack frame. If the last 969 // argument was placed in the stack, there's no need to save any register. 970 if ((isVarArg) && ArgRegEnd) { 971 if (StackPtr.getNode() == 0) 972 StackPtr = DAG.getRegister(StackReg, getPointerTy()); 973 974 // The last register argument that must be saved is MBlaze::R10 975 const TargetRegisterClass *RC = &MBlaze::GPRRegClass; 976 977 unsigned Begin = getMBlazeRegisterNumbering(MBlaze::R5); 978 unsigned Start = getMBlazeRegisterNumbering(ArgRegEnd+1); 979 unsigned End = getMBlazeRegisterNumbering(MBlaze::R10); 980 unsigned StackLoc = Start - Begin + 1; 981 982 for (; Start <= End; ++Start, ++StackLoc) { 983 unsigned Reg = getMBlazeRegisterFromNumbering(Start); 984 unsigned LiveReg = MF.addLiveIn(Reg, RC); 985 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32); 986 987 int FI = MFI->CreateFixedObject(4, 0, true); 988 MBlazeFI->recordStoreVarArgsFI(FI, -(StackLoc*4)); 989 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 990 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 991 MachinePointerInfo(), 992 false, false, 0)); 993 994 // Record the frame index of the first variable argument 995 // which is a value necessary to VASTART. 996 if (!MBlazeFI->getVarArgsFrameIndex()) 997 MBlazeFI->setVarArgsFrameIndex(FI); 998 } 999 } 1000 1001 // All stores are grouped in one node to allow the matching between 1002 // the size of Ins and InVals. This only happens when on varg functions 1003 if (!OutChains.empty()) { 1004 OutChains.push_back(Chain); 1005 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1006 &OutChains[0], OutChains.size()); 1007 } 1008 1009 return Chain; 1010 } 1011 1012 //===----------------------------------------------------------------------===// 1013 // Return Value Calling Convention Implementation 1014 //===----------------------------------------------------------------------===// 1015 1016 SDValue MBlazeTargetLowering:: 1017 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1018 const SmallVectorImpl<ISD::OutputArg> &Outs, 1019 const SmallVectorImpl<SDValue> &OutVals, 1020 DebugLoc dl, SelectionDAG &DAG) const { 1021 // CCValAssign - represent the assignment of 1022 // the return value to a location 1023 SmallVector<CCValAssign, 16> RVLocs; 1024 1025 // CCState - Info about the registers and stack slot. 1026 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1027 getTargetMachine(), RVLocs, *DAG.getContext()); 1028 1029 // Analize return values. 1030 CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze); 1031 1032 SDValue Flag; 1033 SmallVector<SDValue, 4> RetOps(1, Chain); 1034 1035 // If this function is using the interrupt_handler calling convention 1036 // then use "rtid r14, 0" otherwise use "rtsd r15, 8" 1037 unsigned Ret = (CallConv == CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet 1038 : MBlazeISD::Ret; 1039 unsigned Reg = (CallConv == CallingConv::MBLAZE_INTR) ? MBlaze::R14 1040 : MBlaze::R15; 1041 RetOps.push_back(DAG.getRegister(Reg, MVT::i32)); 1042 1043 1044 // Copy the result values into the output registers. 1045 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1046 CCValAssign &VA = RVLocs[i]; 1047 assert(VA.isRegLoc() && "Can only return in registers!"); 1048 1049 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1050 OutVals[i], Flag); 1051 1052 // guarantee that all emitted copies are 1053 // stuck together, avoiding something bad 1054 Flag = Chain.getValue(1); 1055 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1056 } 1057 1058 RetOps[0] = Chain; // Update chain. 1059 1060 // Add the flag if we have it. 1061 if (Flag.getNode()) 1062 RetOps.push_back(Flag); 1063 1064 return DAG.getNode(Ret, dl, MVT::Other, &RetOps[0], RetOps.size()); 1065 } 1066 1067 //===----------------------------------------------------------------------===// 1068 // MBlaze Inline Assembly Support 1069 //===----------------------------------------------------------------------===// 1070 1071 /// getConstraintType - Given a constraint letter, return the type of 1072 /// constraint it is for this target. 1073 MBlazeTargetLowering::ConstraintType MBlazeTargetLowering:: 1074 getConstraintType(const std::string &Constraint) const 1075 { 1076 // MBlaze specific constrainy 1077 // 1078 // 'd' : An address register. Equivalent to r. 1079 // 'y' : Equivalent to r; retained for 1080 // backwards compatibility. 1081 // 'f' : Floating Point registers. 1082 if (Constraint.size() == 1) { 1083 switch (Constraint[0]) { 1084 default : break; 1085 case 'd': 1086 case 'y': 1087 case 'f': 1088 return C_RegisterClass; 1089 } 1090 } 1091 return TargetLowering::getConstraintType(Constraint); 1092 } 1093 1094 /// Examine constraint type and operand type and determine a weight value. 1095 /// This object must already have been set up with the operand type 1096 /// and the current alternative constraint selected. 1097 TargetLowering::ConstraintWeight 1098 MBlazeTargetLowering::getSingleConstraintMatchWeight( 1099 AsmOperandInfo &info, const char *constraint) const { 1100 ConstraintWeight weight = CW_Invalid; 1101 Value *CallOperandVal = info.CallOperandVal; 1102 // If we don't have a value, we can't do a match, 1103 // but allow it at the lowest weight. 1104 if (CallOperandVal == NULL) 1105 return CW_Default; 1106 Type *type = CallOperandVal->getType(); 1107 // Look at the constraint type. 1108 switch (*constraint) { 1109 default: 1110 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 1111 break; 1112 case 'd': 1113 case 'y': 1114 if (type->isIntegerTy()) 1115 weight = CW_Register; 1116 break; 1117 case 'f': 1118 if (type->isFloatTy()) 1119 weight = CW_Register; 1120 break; 1121 } 1122 return weight; 1123 } 1124 1125 /// Given a register class constraint, like 'r', if this corresponds directly 1126 /// to an LLVM register class, return a register of 0 and the register class 1127 /// pointer. 1128 std::pair<unsigned, const TargetRegisterClass*> MBlazeTargetLowering:: 1129 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { 1130 if (Constraint.size() == 1) { 1131 switch (Constraint[0]) { 1132 case 'r': 1133 return std::make_pair(0U, &MBlaze::GPRRegClass); 1134 // TODO: These can't possibly be right, but match what was in 1135 // getRegClassForInlineAsmConstraint. 1136 case 'd': 1137 case 'y': 1138 case 'f': 1139 if (VT == MVT::f32) 1140 return std::make_pair(0U, &MBlaze::GPRRegClass); 1141 } 1142 } 1143 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1144 } 1145 1146 bool MBlazeTargetLowering:: 1147 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1148 // The MBlaze target isn't yet aware of offsets. 1149 return false; 1150 } 1151 1152 bool MBlazeTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 1153 return VT != MVT::f32; 1154 } 1155
