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      1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // Implements the info about Hexagon target spec.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "HexagonTargetMachine.h"
     15 #include "Hexagon.h"
     16 #include "HexagonISelLowering.h"
     17 #include "HexagonMachineScheduler.h"
     18 #include "llvm/CodeGen/Passes.h"
     19 #include "llvm/IR/Module.h"
     20 #include "llvm/PassManager.h"
     21 #include "llvm/Support/CommandLine.h"
     22 #include "llvm/Support/TargetRegistry.h"
     23 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
     24 #include "llvm/Transforms/Scalar.h"
     25 
     26 using namespace llvm;
     27 
     28 static cl::
     29 opt<bool> DisableHardwareLoops(
     30                         "disable-hexagon-hwloops", cl::Hidden,
     31                         cl::desc("Disable Hardware Loops for Hexagon target"));
     32 
     33 static cl::
     34 opt<bool> DisableHexagonMISched("disable-hexagon-misched",
     35                                 cl::Hidden, cl::ZeroOrMore, cl::init(false),
     36                                 cl::desc("Disable Hexagon MI Scheduling"));
     37 
     38 /// HexagonTargetMachineModule - Note that this is used on hosts that
     39 /// cannot link in a library unless there are references into the
     40 /// library.  In particular, it seems that it is not possible to get
     41 /// things to work on Win32 without this.  Though it is unused, do not
     42 /// remove it.
     43 extern "C" int HexagonTargetMachineModule;
     44 int HexagonTargetMachineModule = 0;
     45 
     46 extern "C" void LLVMInitializeHexagonTarget() {
     47   // Register the target.
     48   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
     49 }
     50 
     51 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
     52   return new VLIWMachineScheduler(C, new ConvergingVLIWScheduler());
     53 }
     54 
     55 static MachineSchedRegistry
     56 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
     57                     createVLIWMachineSched);
     58 
     59 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
     60 ///
     61 
     62 /// Hexagon_TODO: Do I need an aggregate alignment?
     63 ///
     64 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
     65                                            StringRef CPU, StringRef FS,
     66                                            const TargetOptions &Options,
     67                                            Reloc::Model RM,
     68                                            CodeModel::Model CM,
     69                                            CodeGenOpt::Level OL)
     70   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
     71     DL("e-p:32:32:32-"
     72                 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
     73                 "f64:64:64-f32:32:32-a0:0-n32") ,
     74     Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
     75     TSInfo(*this),
     76     FrameLowering(Subtarget),
     77     InstrItins(&Subtarget.getInstrItineraryData()) {
     78   setMCUseCFI(false);
     79 }
     80 
     81 // addPassesForOptimizations - Allow the backend (target) to add Target
     82 // Independent Optimization passes to the Pass Manager.
     83 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
     84 
     85   PM.add(createConstantPropagationPass());
     86   PM.add(createLoopSimplifyPass());
     87   PM.add(createDeadCodeEliminationPass());
     88   PM.add(createConstantPropagationPass());
     89   PM.add(createLoopUnrollPass());
     90   PM.add(createLoopStrengthReducePass());
     91   return true;
     92 }
     93 
     94 namespace {
     95 /// Hexagon Code Generator Pass Configuration Options.
     96 class HexagonPassConfig : public TargetPassConfig {
     97 public:
     98   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
     99     : TargetPassConfig(TM, PM) {
    100     // Enable MI scheduler.
    101     if (!DisableHexagonMISched) {
    102       enablePass(&MachineSchedulerID);
    103       MachineSchedRegistry::setDefault(createVLIWMachineSched);
    104     }
    105   }
    106 
    107   HexagonTargetMachine &getHexagonTargetMachine() const {
    108     return getTM<HexagonTargetMachine>();
    109   }
    110 
    111   virtual bool addInstSelector();
    112   virtual bool addPreRegAlloc();
    113   virtual bool addPostRegAlloc();
    114   virtual bool addPreSched2();
    115   virtual bool addPreEmitPass();
    116 };
    117 } // namespace
    118 
    119 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
    120   return new HexagonPassConfig(this, PM);
    121 }
    122 
    123 bool HexagonPassConfig::addInstSelector() {
    124   addPass(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
    125   addPass(createHexagonISelDag(getHexagonTargetMachine(), getOptLevel()));
    126   addPass(createHexagonPeephole());
    127   return false;
    128 }
    129 
    130 
    131 bool HexagonPassConfig::addPreRegAlloc() {
    132   if (!DisableHardwareLoops) {
    133     addPass(createHexagonHardwareLoops());
    134   }
    135   return false;
    136 }
    137 
    138 bool HexagonPassConfig::addPostRegAlloc() {
    139   addPass(createHexagonCFGOptimizer(getHexagonTargetMachine()));
    140   return true;
    141 }
    142 
    143 
    144 bool HexagonPassConfig::addPreSched2() {
    145   addPass(&IfConverterID);
    146   return true;
    147 }
    148 
    149 bool HexagonPassConfig::addPreEmitPass() {
    150 
    151   if (!DisableHardwareLoops) {
    152     addPass(createHexagonFixupHwLoops());
    153   }
    154 
    155   addPass(createHexagonNewValueJump());
    156 
    157   // Expand Spill code for predicate registers.
    158   addPass(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
    159 
    160   // Split up TFRcondsets into conditional transfers.
    161   addPass(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
    162 
    163   // Create Packets.
    164   addPass(createHexagonPacketizer());
    165 
    166   return false;
    167 }
    168