| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 43 .addReg(SrcReg, getKillRegState(KillSrc));
47 .addReg(SrcReg, getKillRegState(KillSrc));
51 .addReg(SrcReg, getKillRegState(KillSrc));
55 .addReg(SrcReg, getKillRegState(KillSrc));
59 .addReg(SrcReg, getKillRegState(KillSrc));
63 .addReg(SrcReg, getKillRegState(KillSrc));
67 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 46 .addReg(SrcReg, getKillRegState(KillSrc)));
74 .addReg(SrcReg, getKillRegState(isKill))
|
| MLxExpansionPass.cpp | 293 .addReg(Src1Reg, getKillRegState(Src1Kill))
294 .addReg(Src2Reg, getKillRegState(Src2Kill));
304 MIB.addReg(TmpReg, getKillRegState(true))
305 .addReg(AccReg, getKillRegState(AccKill));
307 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| ARMLoadStoreOptimizer.cpp | 339 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
350 .addReg(Base, getKillRegState(BaseKill))
354 | getKillRegState(Regs[i].second));
779 .addReg(Base, getKillRegState(BaseKill))
932 .addReg(Base, getKillRegState(isLd ? BaseKill : false))
935 getKillRegState(MO.isKill())));
[all...] |
| ARMBaseInstrInfo.cpp | 661 .addReg(SrcReg, getKillRegState(KillSrc))));
682 MIB.addReg(SrcReg, getKillRegState(KillSrc));
684 MIB.addReg(SrcReg, getKillRegState(KillSrc));
783 .addReg(SrcReg, getKillRegState(isKill))
787 .addReg(SrcReg, getKillRegState(isKill))
795 .addReg(SrcReg, getKillRegState(isKill))
802 MIB = AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
813 .addReg(SrcReg, getKillRegState(isKill))
817 .addReg(SrcReg, getKillRegState(isKill))
830 .addReg(SrcReg, getKillRegState(isKill)
[all...] |
| ARMExpandPseudoInsts.cpp | 548 getKillRegState(MO.isKill()));
[all...] |
| Thumb2InstrInfo.cpp | 121 .addReg(SrcReg, getKillRegState(KillSrc)));
143 .addReg(SrcReg, getKillRegState(isKill))
|
| Thumb1FrameLowering.cpp | 361 MIB.addReg(Reg, getKillRegState(isKill));
|
| ARMFrameLowering.cpp | 632 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
636 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 71 .addReg(SrcReg, getKillRegState(KillSrc));
77 .addReg(SrcReg, getKillRegState(KillSrc));
99 .addReg(SrcReg, getKillRegState(KillSrc));
134 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 286 .addReg(SrcReg, getKillRegState(KillSrc));
289 .addReg(SrcReg, getKillRegState(KillSrc));
292 .addReg(SrcReg, getKillRegState(KillSrc));
308 .addReg(SrcReg, getKillRegState(isKill));
311 .addReg(SrcReg, getKillRegState(isKill));
314 .addReg(SrcReg, getKillRegState(isKill));
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 179 .addReg(Reg2, getKillRegState(Reg2IsKill))
180 .addReg(Reg1, getKillRegState(Reg1IsKill))
431 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
433 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
449 getKillRegState(isKill)),
458 getKillRegState(isKill)),
465 getKillRegState(isKill)),
474 getKillRegState(isKill)),
480 getKillRegState(isKill)),
485 getKillRegState(isKill))
[all...] |
| PPCRegisterInfo.cpp | 295 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
308 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 177 .addReg(Reg, getKillRegState(isKill))
198 .addReg(Reg, getKillRegState(isKill))
227 .addReg(Reg, getKillRegState(isKill))
|
| XCoreInstrInfo.cpp | 343 .addReg(SrcReg, getKillRegState(KillSrc))
355 .addReg(SrcReg, getKillRegState(KillSrc));
371 .addReg(SrcReg, getKillRegState(isKill))
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
101 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 610 .addReg(cmpReg1, getKillRegState(MO1IsKill))
611 .addReg(cmpOp2, getKillRegState(MO2IsKill))
617 .addReg(cmpReg1, getKillRegState(MO1IsKill))
|
| HexagonInstrInfo.cpp | 432 addReg(SrcReg, getKillRegState(KillSrc));
438 addReg(SrcReg, getKillRegState(KillSrc));
467 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
471 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
475 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 89 .addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0);
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 467 StLow = getKillRegState(determinePrologueDeath(MBB, CSI[i+1].getReg()));
468 StHigh = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
483 State = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 97 MIB.addReg(SrcReg, getKillRegState(KillSrc));
112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
|
| MipsSEInstrInfo.cpp | 148 MIB.addReg(SrcReg, getKillRegState(KillSrc));
177 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 344 inline unsigned getKillRegState(bool B) {
|
