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    Searched refs:hasSubClassEq (Results 1 - 11 of 11) sorted by null

  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 165 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
167 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
169 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
171 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
173 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
192 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
194 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
196 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
198 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
200 else if (Mips::FGR64RegClass.hasSubClassEq(RC)
    [all...]
Mips16InstrInfo.cpp 109 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
126 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 445 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
461 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
477 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
482 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
487 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
493 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
527 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
577 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
586 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
595 } else if (PPC::F8RCRegClass.hasSubClassEq(RC))
    [all...]
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 126 return RC != this && hasSubClassEq(RC);
129 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
145 return RC->hasSubClassEq(this);
149 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
    [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 781 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
785 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
793 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
797 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
808 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
825 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
845 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
867 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
    [all...]
Thumb1RegisterInfo.cpp 51 if (ARM::tGPRRegClass.hasSubClassEq(RC))
  /external/llvm/lib/Target/X86/
X86InstrInfo.cpp     [all...]
  /external/llvm/lib/CodeGen/
TargetInstrInfo.cpp 331 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 464 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
468 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
472 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
    [all...]
  /external/llvm/lib/Target/R600/
SIISelLowering.cpp 515 return TRI->getRegClass(RegClass)->hasSubClassEq(TRI->getRegClass(OpClass));
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 536 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
    [all...]

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