| /external/oprofile/module/ia64/ |
| IA64minstate.h | 192 st8.spill [r17]=rR1, 16; /* save original r1 */ \
194 .mem.offset 0, 0; st8.spill [r16]=r2, 16; \
195 .mem.offset 8, 0; st8.spill [r17]=r3, 16; \
198 .mem.offset 0, 0; st8.spill [r16]=r12, 16; \
199 .mem.offset 8, 0; st8.spill [r17]=r13, 16; \
203 .mem.offset 0, 0; st8.spill [r16]=r14, 16; \
204 .mem.offset 8, 0; st8.spill [r17]=r15, 16; \
207 .mem.offset 0, 0; st8.spill [r16]=r8, 16; \
208 .mem.offset 8, 0; st8.spill [r17]=r9, 16; \
212 .mem.offset 0, 0; st8.spill [r16]=r10, 16;
[all...] |
| oprofile_stubs.S | 95 stf.spill [sp]=f0
|
| /external/llvm/lib/CodeGen/ |
| Spiller.h | 22 /// Implementations are utility classes which insert spill or remat code on
29 /// spill - Spill the LRE.getParent() live interval.
30 virtual void spill(LiveRangeEdit &LRE) = 0;
39 /// Create and return a spiller that will insert spill code directly instead
|
| RegAllocBasic.cpp | 56 /// algorithm. It prioritizes live virtual registers by spill weight and spills
164 // Spill or split all live virtual registers currently unified under PhysReg
190 // Spill each interfering vreg allocated to PhysReg or an alias.
192 LiveInterval &Spill = *Intfs[i];
195 if (!VRM->hasPhys(Spill.reg))
200 Matrix->unassign(Spill);
202 // Spill the extracted interval.
203 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM);
204 spiller().spill(LRE);
223 // Populate a list of physical register spill candidates
[all...] |
| Spiller.cpp | 72 /// Add spill ranges for every use/def of the live interval, inserting loads
81 "Attempting to spill already spilled value.");
84 "Trying to spill a stack slot.");
86 DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
167 /// Spills any live range using the spill-everywhere method with no attempt at
176 void spill(LiveRangeEdit &LRE) { function in class:__anon11496::TrivialSpiller
|
| RegAllocPBQP.cpp | 14 // register assignment. If any variables are selected for spilling then spill
367 ++pregOpt; // +1 to account for spill option.
495 spiller->spill(LRE);
504 assert(!(*itr)->empty() && "Empty spill range.");
511 // We need another round if spill intervals were added.
564 // * Spill if necessary
|
| InlineSpiller.cpp | 50 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
51 cl::desc("Disable inline spill hoisting"));
67 // Variables that are valid during spill(), but used by multiple methods.
73 // All registers to spill to StackSlot, including the main register.
87 // True when all reaching defs were reloads: No spill is necessary.
96 // The preferred register to spill.
151 void spill(LiveRangeEdit &);
199 // When spilling a virtual register, we also spill any snippets it is connected
205 // spill slots which can be important in tight loops.
230 // %Reg = COPY %snip / SPILL %snip, fi
1268 void InlineSpiller::spill(LiveRangeEdit &edit) { function in class:InlineSpiller
[all...] |
| RegAllocGreedy.cpp | 53 SplitSpillMode("split-spill-mode", cl::Hidden,
54 cl::desc("Spill mode for splitting live ranges"),
157 float MaxWeight; ///< Maximum spill weight evicted.
542 // Never evict spill products. They cannot split or spill.
546 // register for it. This is indicated by an infinite spill weight. These
637 // hints, and only evict smaller spill weights.
721 // Number of spill code instructions to insert.
744 // Accumulate the total frequency of inserted spill code.
874 // Use the spill placer to determine the live bundles. GrowRegion pretend
[all...] |
| /external/libffi/src/ia64/ |
| unix.S | 304 /* Spill all of the possible argument registers. */
308 stf.spill [r16] = f8, 32
309 stf.spill [r17] = f9, 32
312 stf.spill [r16] = f10, 32
313 stf.spill [r17] = f11, 32
315 stf.spill [r16] = f12, 32
316 stf.spill [r17] = f13, 32
318 stf.spill [r16] = f14, 32
319 stf.spill [r17] = f15, 24
322 st8.spill [r16] = in0, 1
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CompilationCallback_Win64.asm | 24 ; WARNING: We cannot use register spill area - we're generating stubs by hands!
33 ; Save all XMM arg registers. Also allocate reg spill area.
|
| /external/v8/test/mjsunit/ |
| codegen-coverage.js | 53 // The call will spill registers and leave x in {eax,rax}.
55 // The add will spill x and reuse {eax,rax} for the result.
|
| /external/openssl/crypto/bn/asm/ |
| ia64-mont.pl | 389 stf.spill [sp]=f16,-16
391 stf.spill [r17]=f17,32
394 stf.spill [r16]=f18,32
396 stf.spill [r17]=f19,32
399 stf.spill [r16]=f20,32
401 stf.spill [r17]=f21,32
404 stf.spill [r16]=f22
406 stf.spill [r17]=f23
|
| /external/webkit/Source/JavaScriptCore/dfg/ |
| DFGJITCodeGenerator.h | 56 // These constants are used to set priorities for spill order for
60 SpillOrderConstant = 1, // no spill, and cheap fill
61 SpillOrderSpilled = 2, // no spill
62 SpillOrderJS = 4, // needs spill
63 SpillOrderCell = 4, // needs spill
64 SpillOrderInteger = 5, // needs spill and box
65 SpillOrderDouble = 6, // needs spill and convert
118 spill(spillMe);
126 spill(spillMe);
203 // Spill a VirtualRegister to the RegisterFile
204 void spill(VirtualRegister spillMe) function in class:JSC::DFG::JITCodeGenerator
[all...] |
| DFGGenerationInfo.h | 167 void spill(DataFormat spillFormat) function in class:JSC::DFG::GenerationInfo
169 // We shouldn't be spill values that don't need spilling.
174 // We only spill values that have been boxed as a JSValue; otherwise the GC
|
| /system/core/libpixelflinger/codeflinger/ |
| texturing.cpp | 387 CONTEXT_STORE(s.reg, generated_vars.texture[i].spill[0]);
388 CONTEXT_STORE(t.reg, generated_vars.texture[i].spill[1]);
411 // We don't have a way to spill registers automatically
412 // spill depth and AA regs, when we know we may have to.
413 // build the spill list...
437 Spill spill(registerFile(), *this, spill_list);
463 CONTEXT_LOAD(s.reg, generated_vars.texture[i].spill[0]);
464 CONTEXT_LOAD(t.reg, generated_vars.texture[i].spill[1]);
614 CONTEXT_STORE(s.reg, generated_vars.texture[i].spill[0])
[all...] |
| /system/core/include/private/pixelflinger/ |
| ggl_context.h | 486 int32_t spill[2]; member in struct:android::generated_tex_vars_t
499 int32_t spill[3]; member in struct:android::generated_vars_t
|
| /dalvik/vm/mterp/x86/ |
| footer.S | 280 SPILL(rIBASE)
509 movl %edx, TMP_SPILL1(%ebp) # spill self->interpStackEnd
[all...] |
| /dalvik/vm/mterp/out/ |
| InterpAsm-x86.S | 45 sub FrameSize,%esp # Allocate storage for spill, locals & outs
57 will also have an associated spill location (mostly useful for those assigned
89 /* Spill offsets relative to %ebp */
110 /* for spill region: increase size by 48 (to keep 16-byte alignment) */
118 #define SPILL(reg) movl reg##,reg##_SPILL(%ebp)
621 SPILL(rIBASE) # preserve rIBASE (cltd trashes it)
635 SPILL(rIBASE) # save rIBASE (cltd trashes it)
698 SPILL(rIBASE)
735 SPILL(rIBASE)
773 SPILL(rIBASE
[all...] |
