/external/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 185 { ISD::FP_EXTEND, MVT::v4f32, 4 } 223 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 224 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 233 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 234 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 235 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 236 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 237 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 247 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 } [all...] |
ARMISelLowering.cpp | 463 addQRTypeForNEON(MVT::v4f32); 472 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively 473 // supported for v4f32. 509 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); 510 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); 511 setOperationAction(ISD::FCOS, MVT::v4f32, Expand); 512 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand); 513 setOperationAction(ISD::FPOW, MVT::v4f32, Expand); 514 setOperationAction(ISD::FLOG, MVT::v4f32, Expand); 515 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand) [all...] |
ARMISelDAGToDAG.cpp | [all...] |
/external/clang/test/CodeGen/ |
x86_64-arguments.c | 155 typedef float v4f32 __attribute__((__vector_size__(16))); typedef 156 v4f32 f25(v4f32 X) { 179 v4f32 v;
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/external/llvm/include/llvm/CodeGen/ |
ValueTypes.h | 98 v4f32 = 43, // 4 x f32 enumerator in enum:llvm::MVT::SimpleValueType 213 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64); 292 case v4f32: 328 case v4f32: 391 case v4f32: 525 if (NumElements == 4) return MVT::v4f32;
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/external/llvm/lib/Target/X86/ |
X86TargetTransformInfo.cpp | 252 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 }, 254 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 }, 256 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 288 { ISD::SETCC, MVT::v4f32, 1 },
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X86ISelLowering.cpp | [all...] |
X86FastISel.cpp | 265 case MVT::v4f32: [all...] |
/external/llvm/lib/Target/R600/ |
AMDGPUISelLowering.cpp | 54 setOperationAction(ISD::STORE, MVT::v4f32, Promote); 55 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32); 60 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); 61 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
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R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass); 38 setOperationAction(ISD::FADD, MVT::v4f32, Expand); 39 setOperationAction(ISD::FMUL, MVT::v4f32, Expand); 40 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); 41 setOperationAction(ISD::FSUB, MVT::v4f32, Expand); 374 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32)); 852 // non constant ptr cant be folded, keeps it as a v4f32 load [all...] |
AMDILISelLowering.cpp | 54 (int)MVT::v4f32, 79 (int)MVT::v4f32, 412 FLTTY = MVT::v4f32;
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SIISelLowering.cpp | 51 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
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/external/llvm/lib/Target/X86/InstPrinter/ |
X86InstComments.cpp | 317 DecodeSHUFPMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(), 356 DecodeUNPCKLMask(MVT::v4f32, ShuffleMask); 392 DecodeUNPCKHMask(MVT::v4f32, ShuffleMask); 408 DecodePSHUFMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
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/external/llvm/lib/IR/ |
ValueTypes.cpp | 161 case MVT::v4f32: return "v4f32"; 224 case MVT::v4f32: return VectorType::get(Type::getFloatTy(Context), 4);
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/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | 638 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32). 651 // v4f32 != v4f32 could be translate to unordered not equal 652 else if (VecVT == MVT::v4f32) 665 else if (VecVT == MVT::v4f32) 680 if (VecVT == MVT::v4f32) 686 if (VecVT == MVT::v4f32) 690 if (VecVT == MVT::v4f32) 701 // types (v16i8, v8i16, v4i32, and v4f32). 710 case MVT::v4f32 [all...] |
PPCISelLowering.cpp | 411 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 412 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); 413 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); 414 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); 416 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); 421 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 422 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 427 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 433 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 436 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand) [all...] |
/external/llvm/utils/TableGen/ |
CodeGenTarget.cpp | 102 case MVT::v4f32: return "MVT::v4f32";
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/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 63 case MVT::v4f32: [all...] |