| /external/llvm/lib/Target/MBlaze/ |
| MBlazeDelaySlotFiller.cpp | 137 bool aop_is_def = a->getOperand(aop).isDef();
145 bool mop_is_def = m->getOperand(mop).isDef();
|
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 218 if (MO.isDef()) {
271 if (MO.isDef())
|
| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.cpp | 237 if (!MO.isDef()) continue;
324 if (RefOper->isDef() && RefOper->isEarlyClobber())
335 if (!CheckOper.isReg() || !CheckOper.isDef() ||
341 if (RefOper->isDef())
585 if (MO.isDef() && Reg != AntiDepReg)
|
| MachineCSE.cpp | 201 if (!MO.isReg() || MO.isDef())
220 if (!MO.isReg() || !MO.isDef())
296 if (!MO.isReg() || !MO.isDef())
519 if (!MO.isReg() || !MO.isDef())
|
| Spiller.cpp | 114 hasDef |= mi->getOperand(i).isDef();
|
| LiveRangeCalc.cpp | 83 assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
92 if (MO.isDef()) {
|
| VirtRegMap.cpp | 297 if (MO.readsReg() && (MO.isDef() || MO.isKill()))
300 if (MO.isDef()) {
|
| AggressiveAntiDepBreaker.cpp | 234 if (MO.isDef())
247 if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
348 if (!MO.isReg() || !MO.isDef()) continue;
358 if (!MO.isReg() || !MO.isDef()) continue;
398 if (!MO.isReg() || !MO.isDef()) continue;
[all...] |
| RegAllocFast.cpp | 687 if (MO.isDef() && MO.isUndef())
717 if (!MO.isReg() || !MO.isDef()) continue;
772 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
[all...] |
| ExpandPostRAPseudos.cpp | 80 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
|
| TargetSchedule.cpp | 153 if (MO.isReg() && MO.isDef())
163 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
|
| RegisterCoalescer.cpp | 797 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveVariables.h | 253 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
|
| MachineRegisterInfo.h | 515 (!ReturnDefs && op->isDef()) ||
555 while (Op && ((!ReturnDefs && Op->isDef()) ||
|
| LiveIntervalAnalysis.h | 103 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 481 if (MO.isReg() && MO.isDef() &&
516 if (MO.isReg() && MO.isDef()) {
530 if (OPO.isReg() && OPO.isDef()) {
573 if (!MO.isReg() || !MO.isDef())
|
| /external/skia/src/svg/ |
| SkSVGGradient.cpp | 21 bool SkSVGGradient::isDef() {
|
| /external/clang/tools/libclang/ |
| IndexingContext.cpp | 372 bool isDef = D->isThisDeclarationADefinition();
373 bool isContainer = isDef;
377 isDef = true;
381 DeclInfo DInfo(!D->isFirstDeclaration(), isDef, isContainer);
566 bool isDef = D->isThisDeclarationADefinition();
567 bool isContainer = isDef;
571 isDef = true;
575 DeclInfo DInfo(!D->isCanonicalDecl(), isDef, isContainer);
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUIndirectAddressing.cpp | 221 if (MO.isReg() && MO.isDef() &&
230 false, // isDef
332 if (!MO.isReg() || MO.isDef()) {
|
| AMDGPUInstrInfo.cpp | 256 if (MO.isReg() && MO.isDef()) {
|
| /external/llvm/lib/Transforms/Scalar/ |
| DeadStoreElimination.cpp | 512 if (!InstDep.isDef() && !InstDep.isClobber())
548 while (InstDep.isDef() || InstDep.isClobber()) {
670 while (Dep.isDef() || Dep.isClobber()) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 132 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
496 MI->getOperand(0).isDef() &&
|
| HexagonPeephole.cpp | 208 false /*isDef*/,
307 Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
|
| /external/llvm/include/llvm/Analysis/ |
| MemoryDependenceAnalysis.h | 130 /// isDef - Return true if this MemDepResult represents a query that is
132 bool isDef() const { return Value.getInt() == Def; }
|
| /external/llvm/lib/Analysis/ |
| MemDepPrinter.cpp | 67 if (dep.isDef())
|
