| /external/llvm/lib/Target/X86/ |
| X86PadShortFunction.cpp | 40 // Cycles - Number of cycles until return if HasReturn is true, otherwise
41 // number of cycles until end of the BB
42 unsigned int Cycles;
44 VisitedBBInfo() : HasReturn(false), Cycles(0) {}
45 VisitedBBInfo(bool HasReturn, unsigned int Cycles)
46 : HasReturn(HasReturn), Cycles(Cycles) {}
62 unsigned int Cycles = 0);
65 unsigned int &Cycles);
[all...] |
| /external/oprofile/events/arm/armv6/ |
| events.h | 5 "cycles instruction fetch pipe is stalled"},
7 "cycles stall occurs for due to data dependency"},
33 "cycles stalled because Load Store request queque is full"},
37 "nuber of cycles ETMEXTOUT[0] signal was asserted"},
39 "nuber of cycles ETMEXTOUT[1] signal was asserted"},
41 "nuber of cycles both ETMEXTOUT [0] and [1] were asserted * 2"},
43 "clock cycles counter"},
|
| events | 4 event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
5 event:0x02 counters:0,1 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
18 event:0x11 counters:0,1 um:zero minimum:500 name:LSU_STALL : cycles stalled because Load Store request queque is full
20 event:0x20 counters:0,1 um:zero minimum:500 name:ETMEXTOUT0 : nuber of cycles ETMEXTOUT[0] signal was asserted
21 event:0x21 counters:0,1 um:zero minimum:500 name:ETMEXTOUT1 : nuber of cycles ETMEXTOUT[1] signal was asserted
22 event:0x22 counters:0,1 um:zero minimum:500 name:ETMEXTOUT_BOTH : nuber of cycles both ETMEXTOUT [0] and [1] were asserted * 2
23 event:0xff counters:0,1,2 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
|
| /external/oprofile/events/mips/24K/ |
| events.h | 2 {0x0, CTR(0) | CTR(1), 0, "CYCLES",
3 "0-0 Cycles"},
37 "18-0 Stall cycles, including ALU and IFU"},
49 "24-0 Cache fixup cycles (specific to the 24K family microarchitecture)"},
51 "25-0 IFU stall cycles"},
63 "37-0 Stall cycles due to an instruction cache miss"},
65 "38-0 SYNC stall cycles"},
67 "39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline"},
69 "40-0 Uncached stall cycles"},
71 "41-0 MDU stall cycles"},
[all...] |
| events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 24K family microarchitecture)
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
53 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
55 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
56 event:0x26 counters:0 um:zero minimum:500 name:SYNC_STALLS : 38-0 SYNC stall cycles
57 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipelin
[all...] |
| /external/antlr/antlr-3.4/tool/src/main/java/org/antlr/tool/ |
| LeftRecursionCyclesMessage.java | 35 * cycles found by walking rules without decisions; the other msg is
39 public Collection cycles; field in class:LeftRecursionCyclesMessage
41 public LeftRecursionCyclesMessage(Collection cycles) {
43 this.cycles = cycles;
48 st.add("listOfCycles", cycles);
|
| /external/oprofile/events/i386/arch_perfmon/ |
| events.h | 3 "Clock cycles when not halted"},
5 "Unhalted reference cycles"},
|
| /external/oprofile/events/mips/1004K/ |
| events.h | 2 {0x0, CTR(0) | CTR(1), 0, "CYCLES",
3 "0-0 Cycles"},
37 "18-0 Stall cycles, including ALU and IFU"},
49 "24-0 Cache fixup cycles (specific to the 34K family microarchitecture)"},
51 "25-0 IFU stall cycles"},
71 "36-0 Cache coherence intervention processing stall cycles"},
73 "37-0 Stall cycles due to an instruction cache miss"},
75 "39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline"},
77 "40-0 Uncached stall cycles"},
79 "41-0 MDU stall cycles"},
[all...] |
| /external/oprofile/events/mips/rm9000/ |
| events | 4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
12 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
24 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache-miss stall cycles
26 event:0x17 counters:0,1 um:zero minimum:500 name:FP_POSSIBLE_EXCEPTION_CYCLES : Floating-point possible exception cycles
27 event:0x18 counters:0,1 um:zero minimum:500 name:MULTIPLIER_BUSY_SLIP_CYCLES : Slip cycles due to busy multiplier
28 event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Co-processor 0 slip cycles
29 event:0x1a counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_SLIP_CYCLES : Slip cycles due to pending non-blocking loads
30 event:0x1b counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Stall cycles due to a full write buffer
31 event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cache instruction
[all...] |
| /external/oprofile/events/ia64/ia64/ |
| events | 2 event:0x12 counters:0,1,2,3 um:zero minimum:500 name:CPU_CYCLES : CPU Cycles
|
| /external/oprofile/events/mips/34K/ |
| events.h | 2 {0x0, CTR(0) | CTR(1), 0, "CYCLES",
3 "0-0 Cycles"},
37 "18-0 Stall cycles, including ALU and IFU"},
49 "24-0 Cache fixup cycles (specific to the 34K family microarchitecture)"},
51 "25-0 IFU stall cycles"},
71 "37-0 Stall cycles due to an instruction cache miss"},
73 "39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline"},
75 "40-0 Uncached stall cycles"},
77 "41-0 MDU stall cycles"},
79 "42-0 CP2 stall cycles"},
[all...] |
| /external/chromium-trace/trace-viewer/src/importer/linux_perf/ |
| bus_parser_test.html | 23 'bus=RIGHT rw_bytes=0 r_bytes=0 w_bytes=0 cycles=2681746 ns=16760792',
27 'cycles=6705198 ns=16763375',
31 'cycles=6670677 ns=16676375',
35 'cycles=6670521 ns=16676500',
39 'cycles=6669885 ns=16674833',
42 'bus=RIGHT rw_bytes=0 r_bytes=0 w_bytes=0 cycles=2667378 ns=16671250',
46 'cycles=6672156 ns=16680458',
50 'cycles=6689562 ns=16723458',
54 'cycles=6690012 ns=16725083',
58 'cycles=6690156 ns=16725375
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeSchedule3.td | 25 [ 2 // result ready after two cycles
32 // pipeline stages except the execute stage, which takes three cycles. The
38 , InstrStage<3,[EX]>], // three cycles in execute stage
39 [ 4 // result ready after four cycles
45 // stages except the execute stage, which takes 34 cycles. The two
51 , InstrStage<34,[EX]>], // 34 cycles in execute stage
52 [ 35 // result ready after 35 cycles
59 // except the execute stage, which takes two cycles. The two source operands
65 , InstrStage<2,[EX]>], // two cycles in execute stage
66 [ 3 // result ready after three cycles
[all...] |
| MBlazeSchedule5.td | 27 [ 2 // result ready after two cycles
42 [ 2 // result ready after two cycles
48 // stages except the memory access stage, which takes 31 cycles. The two
55 , InstrStage<31,[MA]> // 31 cycles in memory access stage
57 [ 33 // result ready after 33 cycles
72 [ 3 // result ready after three cycles
109 [ 4 // result ready after four cycles
114 // except the memory access stage, which takes two cycles. The source
120 , InstrStage<2,[MA]> // two cycles in memory access stage
128 // cycles. The source operands are read during the decode stage and th
[all...] |
| /external/oprofile/events/avr32/ |
| events | 4 event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
5 event:0x02 counters:1,2 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall due to data dependency
12 event:0x09 counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_WBUF_FULL : cycles stalled due to data cache write buffers full
14 event:0x0b counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_READ_MISS : cycles stalled due to data cache read miss
16 event:0x0d counters:1,2 um:zero minimum:500 name:CYCLES_WRITE_ACCESS : cycles when write access is ongoing
18 event:0x0f counters:1,2 um:zero minimum:500 name:CYCLES_READ_ACCESS : cycles when read access is ongoing
20 event:0x11 counters:1,2 um:zero minimum:500 name:CYCLES_CACHE_STALL : cycles stalled doing read or write access
22 event:0x13 counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_ACCESS : cycles when data cache access is ongoing
27 event:0xff counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
|
| /external/oprofile/events/mips/74K/ |
| events.h | 2 {0x0, CTR(0) | CTR(1) | CTR(2) | CTR(3), 0, "CYCLES",
3 "0-0 Cycles"},
9 "3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception"},
15 "7-0 Instruction cache miss stall cycles"},
17 "8-0 Uncached instruction fetch stall cycles"},
21 "11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch"},
23 "12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS"},
25 "13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full"},
27 "14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full"},
29 "15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) full"}
[all...] |
| /external/oprofile/events/mips/rm7000/ |
| events | 4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles
13 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
25 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss stall cycles (cycles where both cache miss tokens taken and a third try is requested)
27 event:0x17 counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_STALL_CYCLES : FP possible exception cycles
28 event:0x18 counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_DUE_MULTIPLIER_BUSY : Slip Cycles due to multiplier busy
29 event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Coprocessor 0 slip cycles
30 event:0x1a counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_PENDING_NON_BLKING_LOAD : Slip cycles due to pending non-blocking loads
31 event:0x1c counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Write buffer full stall cycles
[all...] |
| /external/chromium/chrome/browser/ui/gtk/ |
| hover_controller_gtk.h | 27 // Throb for |cycles| cycles. This will override the current remaining
28 // number of cycles. Note that a "cycle" is (somewhat unintuitively) half of
30 void StartThrobbing(int cycles);
|
| /external/oprofile/events/ppc64/cell-be/ |
| unit_masks | 10 0x000 Count cycles [mandatory]
12 0x001 Count cycles [mandatory]
22 0x001 Count cycles [mandatory]
32 0x001 Count cycles [mandatory]
45 0x001 Count cycles [default ]
51 0x001 Count cycles [mandatory]
64 0x001 Count cycles [default ]
70 0x001 Count cycles [mandatory]
76 0x0001 Count cycles [mandatory]
91 0x0001 Count cycles [default
[all...] |
| /frameworks/base/core/java/android/view/animation/ |
| CycleInterpolator.java | 24 * Repeats the animation for a specified number of cycles. The
29 public CycleInterpolator(float cycles) {
30 mCycles = cycles;
|
| /external/llvm/include/llvm/MC/ |
| MCSchedule.h | 35 // resources always consume their resource some fixed number of cycles after
46 /// scheduling class for the specified number of cycles.
49 unsigned Cycles;
52 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
56 /// Specify the latency in cpu cycles for a particular scheduling class and def
62 int Cycles;
66 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
70 /// Specify the number of cycles allowed after instruction issue before
[all...] |
| /external/oprofile/events/arm/armv7-ca9/ |
| events | 12 event:0x60 counters:1,2,3,4,5,6 um:zero minimum:500 name:IC_DEP_STALL : Number of cycles where CPU is ready to accept new instructions but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill
13 event:0x61 counters:1,2,3,4,5,6 um:zero minimum:500 name:DC_DEP_STALL : Number of cycles where CPU has some instructions that it cannot issue to any pipeline and the LSU has at least one pending linefill request but no pending TLB requests
17 event:0x66 counters:1,2,3,4,5,6 um:zero minimum:500 name:ISS_NO_DISP : Number of cycles where the issue stage does not dispatch any instruction
18 event:0x67 counters:1,2,3,4,5,6 um:zero minimum:500 name:ISS_EMPTY : Number of cycles where the issue stage is empty
29 event:0x80 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_PLD : Number of cycles where CPU is stalled because PLD slots are all full
30 event:0x81 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_WRITE : Number of cycles where CPU is stalled because data side is full and executing writes to external memory
31 event:0x82 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_INS_TLB : Number of cycles where CPU is stalled because of main TLB misses on requests issued by the instruction side
32 event:0x83 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DATA_TLB : Number of cycles where CPU is stalled because of main TLB misses on requests issued by the data side
33 event:0x84 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_INS_UTLB : Number of cycles where CPU is stalled because of micro TLB misses on the instruction side
34 event:0x85 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DATA_ULTB : Number of cycles where CPU is stalled because of micro TLB misses on the data sid
[all...] |
| /external/kernel-headers/original/asm-mips/sgi/ |
| hpc3.h | 85 #define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */
86 #define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */
87 #define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */
96 #define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */
97 #define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */
98 #define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */
99 #define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */
137 #define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
138 #define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
139 #define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO *
[all...] |
| /external/oprofile/events/ppc64/970MP/ |
| events | 19 event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles
23 event:0X0010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles
24 event:0X0011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
28 event:0X0015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
33 event:0X0020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
34 event:0X0021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
44 event:0X0031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles
55 event:0X0042 counters:2 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_lsu) Processor cycles
67 event:0X0054 counters:4 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_fpu1) Processor cycles
[all...] |
| /external/oprofile/events/ppc64/970/ |
| events | 14 event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles
18 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles
19 event:0X011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
23 event:0X015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
28 event:0X020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
29 event:0X021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
39 event:0X031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles
50 event:0X042 counters:2 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_lsu) Processor cycles
62 event:0X054 counters:4 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_fpu1) Processor cycles
[all...] |
