/external/llvm/test/CodeGen/Mips/ |
buildpairextractelementf64.ll | 16 ; CHECK: mfc1 17 ; CHECK: mfc1
|
2008-08-04-Bitconvert.ll | 12 ; CHECK: mfc1
|
o32_cc_byval.ll | 61 ; CHECK: mfc1 $6, $f[[F0]]
|
/external/valgrind/main/none/tests/mips32/ |
MoveIns.c | 24 // mfc1 rt, fs 110 "mfc1 %1, $" #FD"\n\t" \ 129 "mfc1 %1, $" #FD"\n\t" \ 198 "mfc1 %1, $f4\n\t" \ 199 "mfc1 %2, $f5\n\t" \ 220 "mfc1 %1, $" #FD"\n\t" \ 242 "mfc1 %1, $" #FD"\n\t" \ 253 printf("MFC1\n"); 254 TESTINSNMOVE("mfc1 $t1, $f0", 0, f0, t1); 255 TESTINSNMOVE("mfc1 $t2, $f1", 4, f1, t2) [all...] |
MoveIns.stdout.exp | 0 MFC1 2 mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266 3 mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666 4 mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000 5 mfc1 $t4, $f3 :: fs 0.000000, rt 0x0 6 mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000 7 mfc1 $t6, $f5 :: fs 0.000000, rt 0x0 8 mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b 9 mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a 10 mfc1 $v1, $f8 :: fs nan, rt 0xfffffff [all...] |
MoveIns.stdout.exp-BE | 0 MFC1 2 mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266 3 mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666 4 mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000 5 mfc1 $t4, $f3 :: fs 0.000000, rt 0x0 6 mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000 7 mfc1 $t6, $f5 :: fs 0.000000, rt 0x0 8 mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b 9 mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a 10 mfc1 $v1, $f8 :: fs nan, rt 0xfffffff [all...] |
vfp.c | 57 "mfc1 %1, $" #RT "\n\t" \ 58 "mfc1 %2, $f1\n\t" \ 77 "mfc1 %1, $" #RT "\n\t" \ 94 "mfc1 %0, $" #fd "\n\t" \ 114 "mfc1 %1, $" #fd "\n\t" \ 115 "mfc1 %2, $f1\n\t" \
|
round.c | 94 "mfc1 %0, $f0\n\t" \ 102 "mfc1 %0, $f0\n\t" \
|
/frameworks/native/opengl/libagl/arch-mips/ |
fixed_asm.S | 32 mfc1 $a0,$f12
|
/external/v8/test/cctest/ |
test-assembler-mips.cc | 367 __ mfc1(t0, f4); 368 __ mfc1(t1, f5); 369 __ mfc1(t2, f6); 370 __ mfc1(t3, f7); 432 __ mfc1(t2, f8); 437 __ mfc1(t3, f10); 789 __ mfc1(t0, f0); 790 __ mfc1(t1, f1); 796 __ mfc1(t0, f0); // f0 has LS 32 bits of long. 797 __ mfc1(t1, f1); // f1 has MS 32 bits of long [all...] |
/external/llvm/lib/Target/Mips/ |
MipsInstrFPU.td | 280 def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>; 459 // This pseudo instr gets expanded into 2 mfc1 instrs after register 474 def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>; 480 (MFC1 (TRUNC_W_D32 AFGR64:$src))>; 497 (MFC1 (TRUNC_W_D64 FGR64:$src))>;
|
MipsSEInstrInfo.cpp | 97 Opc = Mips::MFC1; 337 const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1);
|
/dalvik/vm/arch/mips/ |
CallO32.S | 246 mfc1 $t0,$f0 /* Get float ($f0) or double ($f1$f0) result */ 247 mfc1 $t1,$f1
|
/external/llvm/test/MC/Mips/ |
mips-fpu-instructions.s | 143 # CHECK: mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44] 162 mfc1 $a2,$f7
|
/external/llvm/test/MC/Disassembler/Mips/ |
mips32.txt | 249 # CHECK: mfc1 $6, $f7
|
mips32_le.txt | 249 # CHECK: mfc1 $6, $f7
|
mips32r2.txt | 258 # CHECK: mfc1 $6, $f7
|
mips32r2_le.txt | 258 # CHECK: mfc1 $6, $f7
|
/external/oprofile/events/mips/74K/ |
events.h | 37 "19-0 DDQ0 (ALU out-of-order dispatch queue) bubbles due to MFC1 data write"},
|
events | 37 event:0x13 counters:0,2 um:zero minimum:500 name:ALU_BUBBLE_CYCLES : 19-0 DDQ0 (ALU out-of-order dispatch queue) bubbles due to MFC1 data write
|
/external/v8/src/mips/ |
lithium-codegen-mips.cc | [all...] |
disasm-mips.cc | 469 case MFC1: 470 Format(instr, "mfc1 'rt, 'fs");
|
macro-assembler-mips.cc | 978 mfc1(t8, fs); 1030 mfc1(t8, FPURegister::from_code(fs.code() + 1)); 1040 mfc1(t8, FPURegister::from_code(fs.code() + 1)); 1051 mfc1(t8, FPURegister::from_code(fs.code() + 1)); 1062 mfc1(t8, FPURegister::from_code(fs.code() + 1)); 1090 mfc1(rs, scratch); 1098 mfc1(rs, scratch); [all...] |
/external/webkit/Source/JavaScriptCore/assembler/ |
MacroAssemblerMIPS.h | [all...] |
/dalvik/vm/compiler/codegen/mips/ |
MipsLIR.h | 483 kMipsMfc1, /* mfc1 t,s [01000100000] t[20..16] s[15..11] [00000000000] */
|