| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 79 unsigned NumRegs = RC->getNumRegs();
82 RCI.Order.reset(new MCPhysReg[NumRegs]);
111 RCI.NumRegs = N + CSRAlias.size();
112 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
125 if (StressRA && RCI.NumRegs > StressRA)
126 RCI.NumRegs = StressRA;
130 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
138 for (unsigned I = 0; I != RCI.NumRegs; ++I)
|
| ExecutionDepsFix.cpp | 134 const unsigned NumRegs;
149 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
251 assert(unsigned(rx) < NumRegs && "Invalid index");
263 assert(unsigned(rx) < NumRegs && "Invalid index");
274 assert(unsigned(rx) < NumRegs && "Invalid index");
306 for (unsigned rx = 0; rx != NumRegs; ++rx)
330 for (unsigned rx = 0; rx != NumRegs; ++rx)
346 LiveRegs = new LiveReg[NumRegs];
349 for (unsigned rx = 0; rx != NumRegs; ++rx) {
380 for (unsigned rx = 0; rx != NumRegs; ++rx)
[all...] |
| LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
506 unsigned NumRegs = TRI->getNumRegs();
507 PhysRegDef = new MachineInstr*[NumRegs];
508 PhysRegUse = new MachineInstr*[NumRegs];
510 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
511 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
641 for (unsigned i = 0; i != NumRegs; ++i)
645 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
646 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0)
[all...] |
| VirtRegMap.cpp | 67 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
68 Virt2PhysMap.resize(NumRegs);
69 Virt2StackSlotMap.resize(NumRegs);
70 Virt2SplitMap.resize(NumRegs);
|
| MachineLICM.cpp | 496 unsigned NumRegs = TRI->getNumRegs();
497 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
498 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
533 BitVector TermRegs(NumRegs);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.h | 110 /// NumRegs if they are all allocated.
111 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
112 for (unsigned i = 0; i != NumRegs; ++i)
115 return NumRegs;
138 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
139 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
140 if (FirstUnalloc == NumRegs)
151 unsigned NumRegs) {
152 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
153 if (FirstUnalloc == NumRegs)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 232 /// NumRegs if they are all allocated.
233 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const {
234 for (unsigned i = 0; i != NumRegs; ++i)
237 return NumRegs;
260 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) {
261 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
262 if (FirstUnalloc == NumRegs)
273 unsigned NumRegs) {
274 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
275 if (FirstUnalloc == NumRegs)
[all...] |
| RegisterClassInfo.h | 30 unsigned NumRegs;
37 : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0),
41 return makeArrayRef(Order.get(), NumRegs);
86 return get(RC).NumRegs;
|
| FastISel.h | 355 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
|
| /external/llvm/include/llvm/CodeGen/PBQP/Heuristics/ |
| Briggs.h | 315 unsigned numRegs = eCosts.getRows() - 1,
318 std::vector<unsigned> rowInfCounts(numRegs, 0),
324 ed.unsafe.resize(numRegs, 0);
328 for (unsigned i = 0; i < numRegs; ++i) {
361 unsigned numRegs = getGraph().getNodeCosts(nItr).getLength() - 1;
368 for (unsigned r = 0; r < numRegs; ++r) {
388 unsigned numRegs = getGraph().getNodeCosts(nItr).getLength() - 1;
395 for (unsigned r = 0; r < numRegs; ++r) {
407 unsigned numRegs = getGraph().getNodeCosts(nItr).getLength() - 1;
408 nd.isAllocable = nd.numDenied < numRegs || nd.numSafe > 0
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 107 uint8_t NumRegs; // D registers loaded or stored
381 unsigned NumRegs = TableEntry->NumRegs;
392 if (NumRegs > 1 && TableEntry->copyAllListRegs)
394 if (NumRegs > 2 && TableEntry->copyAllListRegs)
396 if (NumRegs > 3 && TableEntry->copyAllListRegs)
446 unsigned NumRegs = TableEntry->NumRegs;
467 if (NumRegs > 1 && TableEntry->copyAllListRegs)
469 if (NumRegs > 2 && TableEntry->copyAllListRegs
[all...] |
| Thumb1FrameLowering.cpp | 384 bool NumRegs = false;
397 NumRegs = true;
401 if (NumRegs)
|
| ARMLoadStoreOptimizer.cpp | 290 unsigned NumRegs = Regs.size();
291 if (NumRegs <= 1)
300 else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA)
302 else if (Offset == -4 * (int)NumRegs && isNotVFP)
313 if (NumRegs <= 2)
320 NewBase = Regs[NumRegs-1].first;
352 for (unsigned i = 0; i != NumRegs; ++i)
[all...] |
| ARMCodeEmitter.cpp | [all...] |
| ARMFrameLowering.cpp | 756 // the stack pointer by numregs * 8 before aligning the stack pointer.
764 // sub r4, sp, #numregs * 8
772 // sub r4, sp, #numregs * 8
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 153 unsigned NumRegs; // Number of entries in the array
246 NumRegs = NR;
309 assert(RegNo < NumRegs &&
344 return NumRegs;
390 assert(RegNo < NumRegs &&
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 233 unsigned NumRegs =
236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
237 NumParts = NumRegs; // Silence a compiler warning.
533 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
538 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
539 NumParts = NumRegs; // Silence a compiler warning.
616 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
618 for (unsigned i = 0; i != NumRegs; ++i)
621 Reg += NumRegs;
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT)
[all...] |
| FunctionLoweringInfo.cpp | 230 unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
231 for (unsigned i = 0; i != NumRegs; ++i) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 212 unsigned NumRegs; // Number of registers used for this argument.
215 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
|
| MipsISelLowering.cpp | [all...] |
| /dalvik/vm/compiler/codegen/ |
| RallocUtil.cpp | 71 static void dumpRegPool(RegisterInfo *p, int numRegs)
75 for (i=0; i < numRegs; i++ ){
581 int numRegs)
584 for (i=0; i < numRegs; i++) {
|
| /dalvik/vm/compiler/codegen/mips/ |
| RallocUtil.cpp | 73 static void dumpRegPool(RegisterInfo *p, int numRegs)
77 for (i=0; i < numRegs; i++ ){
653 int numRegs)
656 for (i=0; i < numRegs; i++) {
[all...] |
| /external/quake/quake/src/QW/gas2masm/ |
| gas2masm.c | 97 int numregs = sizeof (reglist) / sizeof (reglist[0]);
variable
114 for (i=0 ; i<numregs ; i++)
244 for (i=0 ; i<numregs ; i++)
|
| /external/quake/quake/src/WinQuake/gas2masm/ |
| gas2masm.c | 97 int numregs = sizeof (reglist) / sizeof (reglist[0]);
variable
114 for (i=0 ; i<numregs ; i++)
244 for (i=0 ; i<numregs ; i++)
|
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 782 unsigned NumRegs;
791 : NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0),
801 return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds
803 || ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds
810 return NumRegs == ~0u;
869 ++NumRegs;
[all...] |
