1 /* 2 * Licensed to the Apache Software Foundation (ASF) under one or more 3 * contributor license agreements. See the NOTICE file distributed with 4 * this work for additional information regarding copyright ownership. 5 * The ASF licenses this file to You under the Apache License, Version 2.0 6 * (the "License"); you may not use this file except in compliance with 7 * the License. You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 /** 18 * @author Alexander V. Astapchuk 19 */ 20 #include <stdio.h> 21 #include <assert.h> 22 23 #include <limits.h> 24 25 #include "enc_base.h" 26 27 #ifdef NO_ENCODER_INLINE 28 #include "encoder.h" 29 #include "encoder.inl" 30 #else 31 #define NO_ENCODER_INLINE 32 #include "encoder.h" 33 #undef NO_ENCODER_INLINE 34 #endif 35 36 37 38 #ifdef _EM64T_ 39 40 R_Opnd rax_opnd(rax_reg); 41 R_Opnd rcx_opnd(rcx_reg); 42 R_Opnd rdx_opnd(rdx_reg); 43 R_Opnd rbx_opnd(rbx_reg); 44 R_Opnd rsp_opnd(rsp_reg); 45 R_Opnd rbp_opnd(rbp_reg); 46 R_Opnd rsi_opnd(rsi_reg); 47 R_Opnd rdi_opnd(rdi_reg); 48 49 R_Opnd r8_opnd(r8_reg); 50 R_Opnd r9_opnd(r9_reg); 51 R_Opnd r10_opnd(r10_reg); 52 R_Opnd r11_opnd(r11_reg); 53 R_Opnd r12_opnd(r12_reg); 54 R_Opnd r13_opnd(r13_reg); 55 R_Opnd r14_opnd(r14_reg); 56 R_Opnd r15_opnd(r15_reg); 57 58 XMM_Opnd xmm8_opnd(xmm8_reg); 59 XMM_Opnd xmm9_opnd(xmm9_reg); 60 XMM_Opnd xmm10_opnd(xmm10_reg); 61 XMM_Opnd xmm11_opnd(xmm11_reg); 62 XMM_Opnd xmm12_opnd(xmm12_reg); 63 XMM_Opnd xmm13_opnd(xmm13_reg); 64 XMM_Opnd xmm14_opnd(xmm14_reg); 65 XMM_Opnd xmm15_opnd(xmm15_reg); 66 67 #else 68 69 R_Opnd eax_opnd(eax_reg); 70 R_Opnd ecx_opnd(ecx_reg); 71 R_Opnd edx_opnd(edx_reg); 72 R_Opnd ebx_opnd(ebx_reg); 73 R_Opnd esp_opnd(esp_reg); 74 R_Opnd ebp_opnd(ebp_reg); 75 R_Opnd esi_opnd(esi_reg); 76 R_Opnd edi_opnd(edi_reg); 77 78 #endif //_EM64T_ 79 80 XMM_Opnd xmm0_opnd(xmm0_reg); 81 XMM_Opnd xmm1_opnd(xmm1_reg); 82 XMM_Opnd xmm2_opnd(xmm2_reg); 83 XMM_Opnd xmm3_opnd(xmm3_reg); 84 XMM_Opnd xmm4_opnd(xmm4_reg); 85 XMM_Opnd xmm5_opnd(xmm5_reg); 86 XMM_Opnd xmm6_opnd(xmm6_reg); 87 XMM_Opnd xmm7_opnd(xmm7_reg); 88 89 90 #define countof(a) (sizeof(a)/sizeof(a[0])) 91 92 extern const RegName map_of_regno_2_regname[]; 93 extern const OpndSize map_of_EncoderOpndSize_2_RealOpndSize[]; 94 extern const Mnemonic map_of_alu_opcode_2_mnemonic[]; 95 extern const Mnemonic map_of_shift_opcode_2_mnemonic[]; 96 97 const RegName map_of_regno_2_regname [] = { 98 #ifdef _EM64T_ 99 RegName_RAX, RegName_RBX, RegName_RCX, RegName_RDX, 100 RegName_RDI, RegName_RSI, RegName_RSP, RegName_RBP, 101 RegName_R8, RegName_R9, RegName_R10, RegName_R11, 102 RegName_R12, RegName_R13, RegName_R14, RegName_R15, 103 RegName_XMM0, RegName_XMM1, RegName_XMM2, RegName_XMM3, 104 RegName_XMM4, RegName_XMM5, RegName_XMM6, RegName_XMM7, 105 RegName_XMM8, RegName_XMM9, RegName_XMM10, RegName_XMM11, 106 RegName_XMM12, RegName_XMM13, RegName_XMM14, RegName_XMM15, 107 108 #else 109 RegName_EAX, RegName_EBX, RegName_ECX, RegName_EDX, 110 RegName_EDI, RegName_ESI, RegName_ESP, RegName_EBP, 111 RegName_XMM0, RegName_XMM1, RegName_XMM2, RegName_XMM3, 112 RegName_XMM4, RegName_XMM5, RegName_XMM6, RegName_XMM7, 113 RegName_FS, 114 #endif // _EM64T_ 115 116 RegName_Null, 117 }; 118 119 const OpndSize map_of_EncoderOpndSize_2_RealOpndSize[] = { 120 OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64, OpndSize_Any 121 }; 122 123 const Mnemonic map_of_alu_opcode_2_mnemonic[] = { 124 //add_opc=0, or_opc, adc_opc, sbb_opc, 125 //and_opc, sub_opc, xor_opc, cmp_opc, 126 //n_alu 127 Mnemonic_ADD, Mnemonic_OR, Mnemonic_ADC, Mnemonic_SBB, 128 Mnemonic_AND, Mnemonic_SUB, Mnemonic_XOR, Mnemonic_CMP, 129 }; 130 131 const Mnemonic map_of_shift_opcode_2_mnemonic[] = { 132 //shld_opc, shrd_opc, 133 // shl_opc, shr_opc, sar_opc, ror_opc, max_shift_opcode=6, 134 // n_shift = 6 135 Mnemonic_SHLD, Mnemonic_SHRD, 136 Mnemonic_SHL, Mnemonic_SHR, Mnemonic_SAR, Mnemonic_ROR 137 }; 138 139 #ifdef _DEBUG 140 141 static int debug_check() { 142 // Checks some assumptions. 143 144 // 1. all items of Encoder.h:enum Reg_No must be mapped plus n_reg->RegName_Null 145 assert(countof(map_of_regno_2_regname) == n_reg + 1); 146 assert(countof(map_of_alu_opcode_2_mnemonic) == n_alu); 147 assert(countof(map_of_shift_opcode_2_mnemonic) == n_shift); 148 return 0; 149 } 150 151 static int dummy = debug_check(); 152 153 // can have this - initialization order problems.... static int dummy_run_the_debug_test = debug_check(); 154 155 #endif 156
