1 #ifndef _UAPI_MEDIA_MSMB_ISP_H 2 #define _UAPI_MEDIA_MSMB_ISP_H 3 4 #include <linux/videodev2.h> 5 6 #define MAX_PLANES_PER_STREAM 3 7 #define MAX_NUM_STREAM 7 8 9 #define ISP_VERSION_40 40 10 #define ISP_VERSION_32 32 11 #define ISP_NATIVE_BUF_BIT 0x10000 12 #define ISP0_BIT 0x20000 13 #define ISP1_BIT 0x40000 14 #define ISP_STATS_STREAM_BIT 0x80000000 15 16 enum ISP_START_PIXEL_PATTERN { 17 ISP_BAYER_RGRGRG, 18 ISP_BAYER_GRGRGR, 19 ISP_BAYER_BGBGBG, 20 ISP_BAYER_GBGBGB, 21 ISP_YUV_YCbYCr, 22 ISP_YUV_YCrYCb, 23 ISP_YUV_CbYCrY, 24 ISP_YUV_CrYCbY, 25 ISP_PIX_PATTERN_MAX 26 }; 27 28 enum msm_vfe_plane_fmt { 29 Y_PLANE, 30 CB_PLANE, 31 CR_PLANE, 32 CRCB_PLANE, 33 CBCR_PLANE, 34 VFE_PLANE_FMT_MAX 35 }; 36 37 enum msm_vfe_input_src { 38 VFE_PIX_0, 39 VFE_RAW_0, 40 VFE_RAW_1, 41 VFE_RAW_2, 42 VFE_SRC_MAX, 43 }; 44 45 enum msm_vfe_axi_stream_src { 46 PIX_ENCODER, 47 PIX_VIEWFINDER, 48 CAMIF_RAW, 49 IDEAL_RAW, 50 RDI_INTF_0, 51 RDI_INTF_1, 52 RDI_INTF_2, 53 VFE_AXI_SRC_MAX 54 }; 55 56 enum msm_vfe_frame_skip_pattern { 57 NO_SKIP, 58 EVERY_2FRAME, 59 EVERY_3FRAME, 60 EVERY_4FRAME, 61 EVERY_5FRAME, 62 EVERY_6FRAME, 63 EVERY_7FRAME, 64 EVERY_8FRAME, 65 EVERY_16FRAME, 66 EVERY_32FRAME, 67 MAX_SKIP, 68 }; 69 70 enum msm_vfe_camif_input { 71 CAMIF_DISABLED, 72 CAMIF_PAD_REG_INPUT, 73 CAMIF_MIDDI_INPUT, 74 CAMIF_MIPI_INPUT, 75 }; 76 77 struct msm_vfe_camif_cfg { 78 uint32_t lines_per_frame; 79 uint32_t pixels_per_line; 80 uint32_t first_pixel; 81 uint32_t last_pixel; 82 uint32_t first_line; 83 uint32_t last_line; 84 uint32_t epoch_line0; 85 uint32_t epoch_line1; 86 enum msm_vfe_camif_input camif_input; 87 }; 88 89 enum msm_vfe_inputmux { 90 CAMIF, 91 TESTGEN, 92 EXTERNAL_READ, 93 }; 94 95 struct msm_vfe_pix_cfg { 96 struct msm_vfe_camif_cfg camif_cfg; 97 enum msm_vfe_inputmux input_mux; 98 enum ISP_START_PIXEL_PATTERN pixel_pattern; 99 }; 100 101 struct msm_vfe_rdi_cfg { 102 uint8_t cid; 103 uint8_t frame_based; 104 }; 105 106 struct msm_vfe_input_cfg { 107 union { 108 struct msm_vfe_pix_cfg pix_cfg; 109 struct msm_vfe_rdi_cfg rdi_cfg; 110 } d; 111 enum msm_vfe_input_src input_src; 112 uint32_t input_pix_clk; 113 }; 114 115 struct msm_vfe_axi_plane_cfg { 116 uint32_t output_width; /*Include padding*/ 117 uint32_t output_height; 118 uint32_t output_stride; 119 uint32_t output_scan_lines; 120 uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/ 121 uint32_t plane_addr_offset; 122 uint8_t csid_src; /*RDI 0-2*/ 123 uint8_t rdi_cid;/*CID 1-16*/ 124 }; 125 126 struct msm_vfe_axi_stream_request_cmd { 127 uint32_t session_id; 128 uint32_t stream_id; 129 uint32_t output_format;/*Planar/RAW/Misc*/ 130 enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/ 131 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 132 133 uint32_t burst_count; 134 uint32_t hfr_mode; 135 uint8_t frame_base; 136 137 uint32_t init_frame_drop; /*MAX 31 Frames*/ 138 enum msm_vfe_frame_skip_pattern frame_skip_pattern; 139 uint8_t buf_divert; /* if TRUE no vb2 buf done. */ 140 /*Return values*/ 141 uint32_t axi_stream_handle; 142 }; 143 144 struct msm_vfe_axi_stream_release_cmd { 145 uint32_t stream_handle; 146 }; 147 148 enum msm_vfe_axi_stream_cmd { 149 STOP_STREAM, 150 START_STREAM, 151 }; 152 153 struct msm_vfe_axi_stream_cfg_cmd { 154 uint8_t num_streams; 155 uint32_t stream_handle[MAX_NUM_STREAM]; 156 enum msm_vfe_axi_stream_cmd cmd; 157 }; 158 159 enum msm_vfe_axi_stream_update_type { 160 ENABLE_STREAM_BUF_DIVERT, 161 DISABLE_STREAM_BUF_DIVERT, 162 UPDATE_STREAM_FRAMEDROP_PATTERN, 163 }; 164 165 struct msm_vfe_axi_stream_update_cmd { 166 uint32_t stream_handle; 167 enum msm_vfe_axi_stream_update_type update_type; 168 enum msm_vfe_frame_skip_pattern skip_pattern; 169 }; 170 171 enum msm_isp_stats_type { 172 MSM_ISP_STATS_AEC, /* legacy based AEC */ 173 MSM_ISP_STATS_AF, /* legacy based AF */ 174 MSM_ISP_STATS_AWB, /* legacy based AWB */ 175 MSM_ISP_STATS_RS, /* legacy based RS */ 176 MSM_ISP_STATS_CS, /* legacy based CS */ 177 MSM_ISP_STATS_IHIST, /* legacy based HIST */ 178 MSM_ISP_STATS_SKIN, /* legacy based SKIN */ 179 MSM_ISP_STATS_BG, /* Bayer Grids */ 180 MSM_ISP_STATS_BF, /* Bayer Focus */ 181 MSM_ISP_STATS_BE, /* Bayer Exposure*/ 182 MSM_ISP_STATS_BHIST, /* Bayer Hist */ 183 MSM_ISP_STATS_MAX /* MAX */ 184 }; 185 186 struct msm_vfe_stats_stream_request_cmd { 187 uint32_t session_id; 188 uint32_t stream_id; 189 enum msm_isp_stats_type stats_type; 190 uint32_t composite_flag; 191 uint32_t framedrop_pattern; 192 uint32_t irq_subsample_pattern; 193 uint32_t buffer_offset; 194 uint32_t stream_handle; 195 }; 196 197 struct msm_vfe_stats_stream_release_cmd { 198 uint32_t stream_handle; 199 }; 200 201 struct msm_vfe_stats_stream_cfg_cmd { 202 uint8_t num_streams; 203 uint32_t stream_handle[MSM_ISP_STATS_MAX]; 204 uint8_t enable; 205 }; 206 207 enum msm_vfe_reg_cfg_type { 208 VFE_WRITE, 209 VFE_WRITE_MB, 210 VFE_READ, 211 VFE_CFG_MASK, 212 VFE_WRITE_DMI_16BIT, 213 VFE_WRITE_DMI_32BIT, 214 VFE_WRITE_DMI_64BIT, 215 VFE_READ_DMI_16BIT, 216 VFE_READ_DMI_32BIT, 217 VFE_READ_DMI_64BIT, 218 }; 219 220 struct msm_vfe_cfg_cmd2 { 221 uint16_t num_cfg; 222 uint16_t cmd_len; 223 void __user *cfg_data; 224 void __user *cfg_cmd; 225 }; 226 227 struct msm_vfe_reg_rw_info { 228 uint32_t reg_offset; 229 uint32_t cmd_data_offset; 230 uint32_t len; 231 }; 232 233 struct msm_vfe_reg_mask_info { 234 uint32_t reg_offset; 235 uint32_t mask; 236 uint32_t val; 237 }; 238 239 struct msm_vfe_reg_dmi_info { 240 uint32_t hi_tbl_offset; /*Optional*/ 241 uint32_t lo_tbl_offset; /*Required*/ 242 uint32_t len; 243 }; 244 245 struct msm_vfe_reg_cfg_cmd { 246 union { 247 struct msm_vfe_reg_rw_info rw_info; 248 struct msm_vfe_reg_mask_info mask_info; 249 struct msm_vfe_reg_dmi_info dmi_info; 250 } u; 251 enum msm_vfe_reg_cfg_type cmd_type; 252 }; 253 254 enum msm_isp_buf_type { 255 ISP_PRIVATE_BUF, 256 ISP_SHARE_BUF, 257 MAX_ISP_BUF_TYPE, 258 }; 259 260 struct msm_isp_buf_request { 261 uint32_t session_id; 262 uint32_t stream_id; 263 uint8_t num_buf; 264 uint32_t handle; 265 enum msm_isp_buf_type buf_type; 266 }; 267 268 struct msm_isp_qbuf_info { 269 uint32_t handle; 270 int buf_idx; 271 /*Only used for prepare buffer*/ 272 struct v4l2_buffer buffer; 273 /*Only used for diverted buffer*/ 274 uint32_t dirty_buf; 275 }; 276 277 struct msm_vfe_axi_src_state { 278 enum msm_vfe_input_src input_src; 279 uint32_t src_active; 280 }; 281 282 enum msm_isp_event_idx { 283 ISP_REG_UPDATE = 0, 284 ISP_START_ACK = 1, 285 ISP_STOP_ACK = 2, 286 ISP_IRQ_VIOLATION = 3, 287 ISP_WM_BUS_OVERFLOW = 4, 288 ISP_STATS_OVERFLOW = 5, 289 ISP_CAMIF_ERROR = 6, 290 ISP_SOF = 7, 291 ISP_EOF = 8, 292 ISP_EVENT_MAX = 9 293 }; 294 295 #define ISP_EVENT_OFFSET 8 296 #define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) 297 #define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) 298 #define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) 299 #define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) 300 #define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) 301 #define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) 302 #define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) 303 #define ISP_EVENT_WM_BUS_OVERFLOW (ISP_EVENT_BASE + ISP_WM_BUS_OVERFLOW) 304 #define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) 305 #define ISP_EVENT_CAMIF_ERROR (ISP_EVENT_BASE + ISP_CAMIF_ERROR) 306 #define ISP_EVENT_SOF (ISP_EVENT_BASE + ISP_SOF) 307 #define ISP_EVENT_EOF (ISP_EVENT_BASE + ISP_EOF) 308 #define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) 309 #define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) 310 #define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) 311 /* The msm_v4l2_event_data structure should match the 312 * v4l2_event.u.data field. 313 * should not exceed 64 bytes */ 314 315 struct msm_isp_buf_event { 316 uint32_t session_id; 317 uint32_t stream_id; 318 uint32_t handle; 319 int8_t buf_idx; 320 }; 321 struct msm_isp_stats_event { 322 uint32_t stats_mask; /* 4 bytes */ 323 uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */ 324 }; 325 326 struct msm_isp_stream_ack { 327 uint32_t session_id; 328 uint32_t stream_id; 329 uint32_t handle; 330 }; 331 332 struct msm_isp_event_data { 333 /*Wall clock except for buffer divert events 334 *which use monotonic clock 335 */ 336 struct timeval timestamp; 337 /* Monotonic timestamp since bootup */ 338 struct timeval mono_timestamp; 339 /* if pix is a src frame_id is from camif */ 340 uint32_t frame_id; 341 union { 342 /* START_ACK, STOP_ACK */ 343 struct msm_isp_stream_ack stream_ack; 344 /* REG_UPDATE_TRIGGER, bus over flow */ 345 enum msm_vfe_input_src input_src; 346 /* stats notify */ 347 struct msm_isp_stats_event stats; 348 /* IRQ_VIOLATION, STATS_OVER_FLOW, WM_OVER_FLOW */ 349 uint32_t irq_status_mask; 350 struct msm_isp_buf_event buf_done; 351 } u; /* union can have max 52 bytes */ 352 }; 353 354 #define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') 355 #define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') 356 #define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') 357 #define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') 358 #define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') 359 #define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') 360 #define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') 361 #define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') 362 #define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') 363 #define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') 364 #define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') 365 #define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') 366 367 #define VIDIOC_MSM_VFE_REG_CFG \ 368 _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2) 369 370 #define VIDIOC_MSM_ISP_REQUEST_BUF \ 371 _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request) 372 373 #define VIDIOC_MSM_ISP_ENQUEUE_BUF \ 374 _IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info) 375 376 #define VIDIOC_MSM_ISP_RELEASE_BUF \ 377 _IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request) 378 379 #define VIDIOC_MSM_ISP_REQUEST_STREAM \ 380 _IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd) 381 382 #define VIDIOC_MSM_ISP_CFG_STREAM \ 383 _IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd) 384 385 #define VIDIOC_MSM_ISP_RELEASE_STREAM \ 386 _IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd) 387 388 #define VIDIOC_MSM_ISP_INPUT_CFG \ 389 _IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg) 390 391 #define VIDIOC_MSM_ISP_SET_SRC_STATE \ 392 _IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state) 393 394 #define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \ 395 _IOWR('V', BASE_VIDIOC_PRIVATE+9, \ 396 struct msm_vfe_stats_stream_request_cmd) 397 398 #define VIDIOC_MSM_ISP_CFG_STATS_STREAM \ 399 _IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd) 400 401 #define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \ 402 _IOWR('V', BASE_VIDIOC_PRIVATE+11, \ 403 struct msm_vfe_stats_stream_release_cmd) 404 405 #define VIDIOC_MSM_ISP_CFG_STATS_COMP_POLICY \ 406 _IOWR('V', BASE_VIDIOC_PRIVATE+12, \ 407 struct msm_vfe_stats_comp_policy_cfg) 408 409 #define VIDIOC_MSM_ISP_UPDATE_STREAM \ 410 _IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd) 411 412 #endif /* _UAPI_MEDIA_MSMB_ISP_H */ 413
