1 //===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This describes the calling conventions for ARM architecture. 10 //===----------------------------------------------------------------------===// 11 12 /// CCIfAlign - Match of the original alignment of the arg 13 class CCIfAlign<string Align, CCAction A>: 14 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>; 15 16 //===----------------------------------------------------------------------===// 17 // ARM APCS Calling Convention 18 //===----------------------------------------------------------------------===// 19 def CC_ARM_APCS : CallingConv<[ 20 21 // Handles byval parameters. 22 CCIfByVal<CCPassByVal<4, 4>>, 23 24 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 25 26 // Handle all vector types as either f64 or v2f64. 27 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 29 30 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack 31 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>, 32 33 CCIfType<[f32], CCBitConvertToType<i32>>, 34 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 35 36 CCIfType<[i32], CCAssignToStack<4, 4>>, 37 CCIfType<[f64], CCAssignToStack<8, 4>>, 38 CCIfType<[v2f64], CCAssignToStack<16, 4>> 39 ]>; 40 41 def RetCC_ARM_APCS : CallingConv<[ 42 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 43 CCIfType<[f32], CCBitConvertToType<i32>>, 44 45 // Handle all vector types as either f64 or v2f64. 46 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 48 49 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>, 50 51 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 52 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 53 ]>; 54 55 //===----------------------------------------------------------------------===// 56 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available) 57 //===----------------------------------------------------------------------===// 58 def FastCC_ARM_APCS : CallingConv<[ 59 // Handle all vector types as either f64 or v2f64. 60 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 62 63 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 64 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 65 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 66 S9, S10, S11, S12, S13, S14, S15]>>, 67 CCDelegateTo<CC_ARM_APCS> 68 ]>; 69 70 def RetFastCC_ARM_APCS : CallingConv<[ 71 // Handle all vector types as either f64 or v2f64. 72 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 73 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 74 75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 76 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 77 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 78 S9, S10, S11, S12, S13, S14, S15]>>, 79 CCDelegateTo<RetCC_ARM_APCS> 80 ]>; 81 82 //===----------------------------------------------------------------------===// 83 // ARM APCS Calling Convention for GHC 84 //===----------------------------------------------------------------------===// 85 86 def CC_ARM_APCS_GHC : CallingConv<[ 87 // Handle all vector types as either f64 or v2f64. 88 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 89 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 90 91 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 92 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, 93 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, 94 95 // Promote i8/i16 arguments to i32. 96 CCIfType<[i8, i16], CCPromoteToType<i32>>, 97 98 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim 99 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>> 100 ]>; 101 102 //===----------------------------------------------------------------------===// 103 // ARM AAPCS (EABI) Calling Convention, common parts 104 //===----------------------------------------------------------------------===// 105 106 def CC_ARM_AAPCS_Common : CallingConv<[ 107 108 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 109 110 // i64/f64 is passed in even pairs of GPRs 111 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register 112 // (and the same is true for f64 if VFP is not enabled) 113 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>, 114 CCIfType<[i32], CCIf<"State.getNextStackOffset() == 0 &&" 115 "ArgFlags.getOrigAlign() != 8", 116 CCAssignToReg<[R0, R1, R2, R3]>>>, 117 118 CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, R3>>>, 119 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 120 CCIfType<[f64], CCAssignToStack<8, 8>>, 121 CCIfType<[v2f64], CCAssignToStack<16, 8>> 122 ]>; 123 124 def RetCC_ARM_AAPCS_Common : CallingConv<[ 125 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 126 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 127 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 128 ]>; 129 130 //===----------------------------------------------------------------------===// 131 // ARM AAPCS (EABI) Calling Convention 132 //===----------------------------------------------------------------------===// 133 134 def CC_ARM_AAPCS : CallingConv<[ 135 // Handles byval parameters. 136 CCIfByVal<CCPassByVal<4, 4>>, 137 138 // Handle all vector types as either f64 or v2f64. 139 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 140 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 141 142 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>, 143 CCIfType<[f32], CCBitConvertToType<i32>>, 144 CCDelegateTo<CC_ARM_AAPCS_Common> 145 ]>; 146 147 def RetCC_ARM_AAPCS : CallingConv<[ 148 // Handle all vector types as either f64 or v2f64. 149 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 150 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 151 152 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>, 153 CCIfType<[f32], CCBitConvertToType<i32>>, 154 CCDelegateTo<RetCC_ARM_AAPCS_Common> 155 ]>; 156 157 //===----------------------------------------------------------------------===// 158 // ARM AAPCS-VFP (EABI) Calling Convention 159 // Also used for FastCC (when VFP2 or later is available) 160 //===----------------------------------------------------------------------===// 161 162 def CC_ARM_AAPCS_VFP : CallingConv<[ 163 // Handles byval parameters. 164 CCIfByVal<CCPassByVal<4, 4>>, 165 166 // Handle all vector types as either f64 or v2f64. 167 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 168 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 169 170 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 171 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 172 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 173 S9, S10, S11, S12, S13, S14, S15]>>, 174 CCDelegateTo<CC_ARM_AAPCS_Common> 175 ]>; 176 177 def RetCC_ARM_AAPCS_VFP : CallingConv<[ 178 // Handle all vector types as either f64 or v2f64. 179 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 180 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 181 182 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 183 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 184 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 185 S9, S10, S11, S12, S13, S14, S15]>>, 186 CCDelegateTo<RetCC_ARM_AAPCS_Common> 187 ]>; 188 189 //===----------------------------------------------------------------------===// 190 // Callee-saved register lists. 191 //===----------------------------------------------------------------------===// 192 193 def CSR_NoRegs : CalleeSavedRegs<(add)>; 194 195 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4, 196 (sequence "D%u", 15, 8))>; 197 198 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register. 199 // Also save R7-R4 first to match the stack frame fixed spill areas. 200 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>; 201 202 // GHC set of callee saved regs is empty as all those regs are 203 // used for passing STG regs around 204 // add is a workaround for not being able to compile empty list: 205 // def CSR_GHC : CalleeSavedRegs<()>; 206 def CSR_GHC : CalleeSavedRegs<(add)>; 207
